1//===-- X86InstrCMovSetCC.td - Conditional Move and SetCC --*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the X86 conditional move and set on condition
10// instructions.
11//
12//===----------------------------------------------------------------------===//
13
14
15// CMOV instructions.
16let isCodeGenOnly = 1, ForceDisassemble = 1 in {
17let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
18    isCommutable = 1, SchedRW = [WriteCMOV] in {
19  def CMOV16rr
20    : I<0x40, MRMSrcRegCC, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, ccode:$cond),
21        "cmov${cond}{w}\t{$src2, $dst|$dst, $src2}",
22        [(set GR16:$dst,
23              (X86cmov GR16:$src1, GR16:$src2, timm:$cond, EFLAGS))]>,
24              TB, OpSize16;
25  def CMOV32rr
26    : I<0x40, MRMSrcRegCC, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, ccode:$cond),
27        "cmov${cond}{l}\t{$src2, $dst|$dst, $src2}",
28        [(set GR32:$dst,
29              (X86cmov GR32:$src1, GR32:$src2, timm:$cond, EFLAGS))]>,
30              TB, OpSize32;
31  def CMOV64rr
32    :RI<0x40, MRMSrcRegCC, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, ccode:$cond),
33        "cmov${cond}{q}\t{$src2, $dst|$dst, $src2}",
34        [(set GR64:$dst,
35              (X86cmov GR64:$src1, GR64:$src2, timm:$cond, EFLAGS))]>, TB;
36}
37
38let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
39    SchedRW = [WriteCMOV.Folded, WriteCMOV.ReadAfterFold] in {
40  def CMOV16rm
41    : I<0x40, MRMSrcMemCC, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2, ccode:$cond),
42        "cmov${cond}{w}\t{$src2, $dst|$dst, $src2}",
43        [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
44                                  timm:$cond, EFLAGS))]>, TB, OpSize16;
45  def CMOV32rm
46    : I<0x40, MRMSrcMemCC, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2, ccode:$cond),
47        "cmov${cond}{l}\t{$src2, $dst|$dst, $src2}",
48        [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
49                                  timm:$cond, EFLAGS))]>, TB, OpSize32;
50  def CMOV64rm
51    :RI<0x40, MRMSrcMemCC, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2, ccode:$cond),
52        "cmov${cond}{q}\t{$src2, $dst|$dst, $src2}",
53        [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
54                                  timm:$cond, EFLAGS))]>, TB;
55} // Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst"
56} // isCodeGenOnly = 1, ForceDisassemble = 1
57
58def inv_cond_XFORM : SDNodeXForm<imm, [{
59  X86::CondCode CC = static_cast<X86::CondCode>(N->getZExtValue());
60  return CurDAG->getTargetConstant(X86::GetOppositeBranchCondition(CC),
61                                   SDLoc(N), MVT::i8);
62}]>;
63
64// Conditional moves with folded loads with operands swapped and conditions
65// inverted.
66let Predicates = [HasCMov] in {
67  def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, timm:$cond, EFLAGS),
68            (CMOV16rm GR16:$src2, addr:$src1, (inv_cond_XFORM timm:$cond))>;
69  def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, timm:$cond, EFLAGS),
70            (CMOV32rm GR32:$src2, addr:$src1, (inv_cond_XFORM timm:$cond))>;
71  def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, timm:$cond, EFLAGS),
72            (CMOV64rm GR64:$src2, addr:$src1, (inv_cond_XFORM timm:$cond))>;
73}
74
75// SetCC instructions.
76let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1 in {
77  def SETCCr : I<0x90, MRMXrCC, (outs GR8:$dst), (ins ccode:$cond),
78                "set${cond}\t$dst",
79                [(set GR8:$dst, (X86setcc timm:$cond, EFLAGS))]>,
80                TB, Sched<[WriteSETCC]>;
81  def SETCCm : I<0x90, MRMXmCC, (outs), (ins i8mem:$dst, ccode:$cond),
82                "set${cond}\t$dst",
83                [(store (X86setcc timm:$cond, EFLAGS), addr:$dst)]>,
84                TB, Sched<[WriteSETCCStore]>;
85} // Uses = [EFLAGS]
86
87multiclass CMOV_SETCC_Aliases<string Cond, int CC> {
88  def : InstAlias<"cmov"#Cond#"{w}\t{$src, $dst|$dst, $src}",
89                  (CMOV16rr GR16:$dst, GR16:$src, CC), 0>;
90  def : InstAlias<"cmov"#Cond#"{w}\t{$src, $dst|$dst, $src}",
91                  (CMOV16rm GR16:$dst, i16mem:$src, CC), 0>;
92  def : InstAlias<"cmov"#Cond#"{l}\t{$src, $dst|$dst, $src}",
93                  (CMOV32rr GR32:$dst, GR32:$src, CC), 0>;
94  def : InstAlias<"cmov"#Cond#"{l}\t{$src, $dst|$dst, $src}",
95                  (CMOV32rm GR32:$dst, i32mem:$src, CC), 0>;
96  def : InstAlias<"cmov"#Cond#"{q}\t{$src, $dst|$dst, $src}",
97                  (CMOV64rr GR64:$dst, GR64:$src, CC), 0>;
98  def : InstAlias<"cmov"#Cond#"{q}\t{$src, $dst|$dst, $src}",
99                  (CMOV64rm GR64:$dst, i64mem:$src, CC), 0>;
100
101  def : InstAlias<"set"#Cond#"\t$dst", (SETCCr GR8:$dst, CC), 0>;
102  def : InstAlias<"set"#Cond#"\t$dst", (SETCCm i8mem:$dst, CC), 0>;
103}
104
105defm : CMOV_SETCC_Aliases<"o" ,  0>;
106defm : CMOV_SETCC_Aliases<"no",  1>;
107defm : CMOV_SETCC_Aliases<"b" ,  2>;
108defm : CMOV_SETCC_Aliases<"ae",  3>;
109defm : CMOV_SETCC_Aliases<"e" ,  4>;
110defm : CMOV_SETCC_Aliases<"ne",  5>;
111defm : CMOV_SETCC_Aliases<"be",  6>;
112defm : CMOV_SETCC_Aliases<"a" ,  7>;
113defm : CMOV_SETCC_Aliases<"s" ,  8>;
114defm : CMOV_SETCC_Aliases<"ns",  9>;
115defm : CMOV_SETCC_Aliases<"p" , 10>;
116defm : CMOV_SETCC_Aliases<"np", 11>;
117defm : CMOV_SETCC_Aliases<"l" , 12>;
118defm : CMOV_SETCC_Aliases<"ge", 13>;
119defm : CMOV_SETCC_Aliases<"le", 14>;
120defm : CMOV_SETCC_Aliases<"g" , 15>;
121
122// SALC is an undocumented instruction. Information for this instruction can be found
123// here http://www.rcollins.org/secrets/opcodes/SALC.html
124// Set AL if carry.
125let Uses = [EFLAGS], Defs = [AL], SchedRW = [WriteALU] in {
126  def SALC : I<0xD6, RawFrm, (outs), (ins), "salc", []>, Requires<[Not64BitMode]>;
127}
128