1//=- X86SchedBroadwell.td - X86 Broadwell Scheduling ---------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for Broadwell to support instruction 10// scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14def BroadwellModel : SchedMachineModel { 15 // All x86 instructions are modeled as a single micro-op, and BW can decode 4 16 // instructions per cycle. 17 let IssueWidth = 4; 18 let MicroOpBufferSize = 192; // Based on the reorder buffer. 19 let LoadLatency = 5; 20 let MispredictPenalty = 16; 21 22 // Based on the LSD (loop-stream detector) queue size and benchmarking data. 23 let LoopMicroOpBufferSize = 50; 24 25 // This flag is set to allow the scheduler to assign a default model to 26 // unrecognized opcodes. 27 let CompleteModel = 0; 28} 29 30let SchedModel = BroadwellModel in { 31 32// Broadwell can issue micro-ops to 8 different ports in one cycle. 33 34// Ports 0, 1, 5, and 6 handle all computation. 35// Port 4 gets the data half of stores. Store data can be available later than 36// the store address, but since we don't model the latency of stores, we can 37// ignore that. 38// Ports 2 and 3 are identical. They handle loads and the address half of 39// stores. Port 7 can handle address calculations. 40def BWPort0 : ProcResource<1>; 41def BWPort1 : ProcResource<1>; 42def BWPort2 : ProcResource<1>; 43def BWPort3 : ProcResource<1>; 44def BWPort4 : ProcResource<1>; 45def BWPort5 : ProcResource<1>; 46def BWPort6 : ProcResource<1>; 47def BWPort7 : ProcResource<1>; 48 49// Many micro-ops are capable of issuing on multiple ports. 50def BWPort01 : ProcResGroup<[BWPort0, BWPort1]>; 51def BWPort23 : ProcResGroup<[BWPort2, BWPort3]>; 52def BWPort237 : ProcResGroup<[BWPort2, BWPort3, BWPort7]>; 53def BWPort04 : ProcResGroup<[BWPort0, BWPort4]>; 54def BWPort05 : ProcResGroup<[BWPort0, BWPort5]>; 55def BWPort06 : ProcResGroup<[BWPort0, BWPort6]>; 56def BWPort15 : ProcResGroup<[BWPort1, BWPort5]>; 57def BWPort16 : ProcResGroup<[BWPort1, BWPort6]>; 58def BWPort56 : ProcResGroup<[BWPort5, BWPort6]>; 59def BWPort015 : ProcResGroup<[BWPort0, BWPort1, BWPort5]>; 60def BWPort056 : ProcResGroup<[BWPort0, BWPort5, BWPort6]>; 61def BWPort0156: ProcResGroup<[BWPort0, BWPort1, BWPort5, BWPort6]>; 62 63// 60 Entry Unified Scheduler 64def BWPortAny : ProcResGroup<[BWPort0, BWPort1, BWPort2, BWPort3, BWPort4, 65 BWPort5, BWPort6, BWPort7]> { 66 let BufferSize=60; 67} 68 69// Integer division issued on port 0. 70def BWDivider : ProcResource<1>; 71// FP division and sqrt on port 0. 72def BWFPDivider : ProcResource<1>; 73 74// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 75// cycles after the memory operand. 76def : ReadAdvance<ReadAfterLd, 5>; 77 78// Vector loads are 5/5/6 cycles, so ReadAfterVec*Ld registers needn't be available 79// until 5/5/6 cycles after the memory operand. 80def : ReadAdvance<ReadAfterVecLd, 5>; 81def : ReadAdvance<ReadAfterVecXLd, 5>; 82def : ReadAdvance<ReadAfterVecYLd, 6>; 83 84def : ReadAdvance<ReadInt2Fpu, 0>; 85 86// Many SchedWrites are defined in pairs with and without a folded load. 87// Instructions with folded loads are usually micro-fused, so they only appear 88// as two micro-ops when queued in the reservation station. 89// This multiclass defines the resource usage for variants with and without 90// folded loads. 91multiclass BWWriteResPair<X86FoldableSchedWrite SchedRW, 92 list<ProcResourceKind> ExePorts, 93 int Lat, list<int> Res = [1], int UOps = 1, 94 int LoadLat = 5> { 95 // Register variant is using a single cycle on ExePort. 96 def : WriteRes<SchedRW, ExePorts> { 97 let Latency = Lat; 98 let ResourceCycles = Res; 99 let NumMicroOps = UOps; 100 } 101 102 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to 103 // the latency (default = 5). 104 def : WriteRes<SchedRW.Folded, !listconcat([BWPort23], ExePorts)> { 105 let Latency = !add(Lat, LoadLat); 106 let ResourceCycles = !listconcat([1], Res); 107 let NumMicroOps = !add(UOps, 1); 108 } 109} 110 111// A folded store needs a cycle on port 4 for the store data, and an extra port 112// 2/3/7 cycle to recompute the address. 113def : WriteRes<WriteRMW, [BWPort237,BWPort4]>; 114 115// Arithmetic. 116defm : BWWriteResPair<WriteALU, [BWPort0156], 1>; // Simple integer ALU op. 117defm : BWWriteResPair<WriteADC, [BWPort06], 1>; // Integer ALU + flags op. 118 119// Integer multiplication. 120defm : BWWriteResPair<WriteIMul8, [BWPort1], 3>; 121defm : BWWriteResPair<WriteIMul16, [BWPort1,BWPort06,BWPort0156], 4, [1,1,2], 4>; 122defm : X86WriteRes<WriteIMul16Imm, [BWPort1,BWPort0156], 4, [1,1], 2>; 123defm : X86WriteRes<WriteIMul16ImmLd, [BWPort1,BWPort0156,BWPort23], 8, [1,1,1], 3>; 124defm : BWWriteResPair<WriteIMul16Reg, [BWPort1], 3>; 125defm : BWWriteResPair<WriteIMul32, [BWPort1,BWPort06,BWPort0156], 4, [1,1,1], 3>; 126defm : BWWriteResPair<WriteIMul32Imm, [BWPort1], 3>; 127defm : BWWriteResPair<WriteIMul32Reg, [BWPort1], 3>; 128defm : BWWriteResPair<WriteIMul64, [BWPort1,BWPort5], 4, [1,1], 2>; 129defm : BWWriteResPair<WriteIMul64Imm, [BWPort1], 3>; 130defm : BWWriteResPair<WriteIMul64Reg, [BWPort1], 3>; 131def : WriteRes<WriteIMulH, []> { let Latency = 3; } 132 133// TODO: Why isn't the BWDivider used consistently? 134defm : X86WriteRes<WriteDiv8, [BWPort0, BWDivider], 25, [1, 10], 1>; 135defm : X86WriteRes<WriteDiv16, [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>; 136defm : X86WriteRes<WriteDiv32, [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>; 137defm : X86WriteRes<WriteDiv64, [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>; 138defm : X86WriteRes<WriteDiv8Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>; 139defm : X86WriteRes<WriteDiv16Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>; 140defm : X86WriteRes<WriteDiv32Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>; 141defm : X86WriteRes<WriteDiv64Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>; 142 143defm : X86WriteRes<WriteIDiv8, [BWPort0, BWDivider], 25, [1,10], 1>; 144defm : X86WriteRes<WriteIDiv16, [BWPort0, BWDivider], 25, [1,10], 1>; 145defm : X86WriteRes<WriteIDiv32, [BWPort0, BWDivider], 25, [1,10], 1>; 146defm : X86WriteRes<WriteIDiv64, [BWPort0, BWDivider], 25, [1,10], 1>; 147defm : X86WriteRes<WriteIDiv8Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>; 148defm : X86WriteRes<WriteIDiv16Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>; 149defm : X86WriteRes<WriteIDiv32Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>; 150defm : X86WriteRes<WriteIDiv64Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>; 151 152defm : X86WriteRes<WriteCMPXCHG,[BWPort06, BWPort0156], 5, [2, 3], 5>; 153defm : X86WriteRes<WriteCMPXCHGRMW,[BWPort23, BWPort06, BWPort0156, BWPort237, BWPort4], 8, [1, 2, 1, 1, 1], 6>; 154defm : X86WriteRes<WriteBSWAP32, [BWPort15], 1, [1], 1>; 155defm : X86WriteRes<WriteBSWAP64, [BWPort06, BWPort15], 2, [1, 1], 2>; 156defm : X86WriteRes<WriteXCHG, [BWPort0156], 2, [3], 3>; 157 158defm : BWWriteResPair<WriteCRC32, [BWPort1], 3>; 159 160def : WriteRes<WriteLEA, [BWPort15]>; // LEA instructions can't fold loads. 161 162defm : BWWriteResPair<WriteCMOV, [BWPort06], 1>; // Conditional move. 163defm : X86WriteRes<WriteFCMOV, [BWPort1], 3, [1], 1>; // x87 conditional move. 164 165def : WriteRes<WriteSETCC, [BWPort06]>; // Setcc. 166def : WriteRes<WriteSETCCStore, [BWPort06,BWPort4,BWPort237]> { 167 let Latency = 2; 168 let NumMicroOps = 3; 169} 170 171defm : X86WriteRes<WriteLAHFSAHF, [BWPort06], 1, [1], 1>; 172defm : X86WriteRes<WriteBitTest, [BWPort06], 1, [1], 1>; // Bit Test instrs 173defm : X86WriteRes<WriteBitTestImmLd, [BWPort06,BWPort23], 6, [1,1], 2>; 174defm : X86WriteRes<WriteBitTestRegLd, [BWPort0156,BWPort23], 6, [1,1], 2>; 175defm : X86WriteRes<WriteBitTestSet, [BWPort06], 1, [1], 1>; // Bit Test + Set instrs 176defm : X86WriteRes<WriteBitTestSetImmLd, [BWPort06,BWPort23], 5, [1,1], 3>; 177defm : X86WriteRes<WriteBitTestSetRegLd, [BWPort0156,BWPort23], 5, [1,1], 2>; 178 179// Bit counts. 180defm : BWWriteResPair<WriteBSF, [BWPort1], 3>; 181defm : BWWriteResPair<WriteBSR, [BWPort1], 3>; 182defm : BWWriteResPair<WriteLZCNT, [BWPort1], 3>; 183defm : BWWriteResPair<WriteTZCNT, [BWPort1], 3>; 184defm : BWWriteResPair<WritePOPCNT, [BWPort1], 3>; 185 186// Integer shifts and rotates. 187defm : BWWriteResPair<WriteShift, [BWPort06], 1>; 188defm : BWWriteResPair<WriteShiftCL, [BWPort06,BWPort0156], 3, [2,1], 3>; 189defm : BWWriteResPair<WriteRotate, [BWPort06], 1, [1], 1>; 190defm : BWWriteResPair<WriteRotateCL, [BWPort06,BWPort0156], 3, [2,1], 3>; 191 192// SHLD/SHRD. 193defm : X86WriteRes<WriteSHDrri, [BWPort1], 3, [1], 1>; 194defm : X86WriteRes<WriteSHDrrcl,[BWPort1,BWPort06,BWPort0156], 6, [1, 1, 2], 4>; 195defm : X86WriteRes<WriteSHDmri, [BWPort1,BWPort23,BWPort237,BWPort0156], 9, [1, 1, 1, 1], 4>; 196defm : X86WriteRes<WriteSHDmrcl,[BWPort1,BWPort23,BWPort237,BWPort06,BWPort0156], 11, [1, 1, 1, 1, 2], 6>; 197 198// BMI1 BEXTR/BLS, BMI2 BZHI 199defm : BWWriteResPair<WriteBEXTR, [BWPort06,BWPort15], 2, [1,1], 2>; 200defm : BWWriteResPair<WriteBLS, [BWPort15], 1>; 201defm : BWWriteResPair<WriteBZHI, [BWPort15], 1>; 202 203// Loads, stores, and moves, not folded with other operations. 204defm : X86WriteRes<WriteLoad, [BWPort23], 5, [1], 1>; 205defm : X86WriteRes<WriteStore, [BWPort237, BWPort4], 1, [1,1], 1>; 206defm : X86WriteRes<WriteStoreNT, [BWPort237, BWPort4], 1, [1,1], 2>; 207defm : X86WriteRes<WriteMove, [BWPort0156], 1, [1], 1>; 208 209// Model the effect of clobbering the read-write mask operand of the GATHER operation. 210// Does not cost anything by itself, only has latency, matching that of the WriteLoad, 211defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>; 212 213// Idioms that clear a register, like xorps %xmm0, %xmm0. 214// These can often bypass execution ports completely. 215def : WriteRes<WriteZero, []>; 216 217// Treat misc copies as a move. 218def : InstRW<[WriteMove], (instrs COPY)>; 219 220// Branches don't produce values, so they have no latency, but they still 221// consume resources. Indirect branches can fold loads. 222defm : BWWriteResPair<WriteJump, [BWPort06], 1>; 223 224// Floating point. This covers both scalar and vector operations. 225defm : X86WriteRes<WriteFLD0, [BWPort01], 1, [1], 1>; 226defm : X86WriteRes<WriteFLD1, [BWPort01], 1, [2], 2>; 227defm : X86WriteRes<WriteFLDC, [BWPort01], 1, [2], 2>; 228defm : X86WriteRes<WriteFLoad, [BWPort23], 5, [1], 1>; 229defm : X86WriteRes<WriteFLoadX, [BWPort23], 5, [1], 1>; 230defm : X86WriteRes<WriteFLoadY, [BWPort23], 6, [1], 1>; 231defm : X86WriteRes<WriteFMaskedLoad, [BWPort23,BWPort5], 7, [1,2], 3>; 232defm : X86WriteRes<WriteFMaskedLoadY, [BWPort23,BWPort5], 8, [1,2], 3>; 233defm : X86WriteRes<WriteFStore, [BWPort237,BWPort4], 1, [1,1], 2>; 234defm : X86WriteRes<WriteFStoreX, [BWPort237,BWPort4], 1, [1,1], 2>; 235defm : X86WriteRes<WriteFStoreY, [BWPort237,BWPort4], 1, [1,1], 2>; 236defm : X86WriteRes<WriteFStoreNT, [BWPort237,BWPort4], 1, [1,1], 2>; 237defm : X86WriteRes<WriteFStoreNTX, [BWPort237,BWPort4], 1, [1,1], 2>; 238defm : X86WriteRes<WriteFStoreNTY, [BWPort237,BWPort4], 1, [1,1], 2>; 239 240defm : X86WriteRes<WriteFMaskedStore32, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>; 241defm : X86WriteRes<WriteFMaskedStore32Y, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>; 242defm : X86WriteRes<WriteFMaskedStore64, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>; 243defm : X86WriteRes<WriteFMaskedStore64Y, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>; 244 245defm : X86WriteRes<WriteFMove, [BWPort5], 1, [1], 1>; 246defm : X86WriteRes<WriteFMoveX, [BWPort5], 1, [1], 1>; 247defm : X86WriteRes<WriteFMoveY, [BWPort5], 1, [1], 1>; 248 249defm : BWWriteResPair<WriteFAdd, [BWPort1], 3, [1], 1, 5>; // Floating point add/sub. 250defm : BWWriteResPair<WriteFAddX, [BWPort1], 3, [1], 1, 5>; // Floating point add/sub (XMM). 251defm : BWWriteResPair<WriteFAddY, [BWPort1], 3, [1], 1, 6>; // Floating point add/sub (YMM/ZMM). 252defm : X86WriteResPairUnsupported<WriteFAddZ>; 253defm : BWWriteResPair<WriteFAdd64, [BWPort1], 3, [1], 1, 5>; // Floating point double add/sub. 254defm : BWWriteResPair<WriteFAdd64X, [BWPort1], 3, [1], 1, 5>; // Floating point double add/sub (XMM). 255defm : BWWriteResPair<WriteFAdd64Y, [BWPort1], 3, [1], 1, 6>; // Floating point double add/sub (YMM/ZMM). 256defm : X86WriteResPairUnsupported<WriteFAdd64Z>; 257 258defm : BWWriteResPair<WriteFCmp, [BWPort1], 3, [1], 1, 5>; // Floating point compare. 259defm : BWWriteResPair<WriteFCmpX, [BWPort1], 3, [1], 1, 5>; // Floating point compare (XMM). 260defm : BWWriteResPair<WriteFCmpY, [BWPort1], 3, [1], 1, 6>; // Floating point compare (YMM/ZMM). 261defm : X86WriteResPairUnsupported<WriteFCmpZ>; 262defm : BWWriteResPair<WriteFCmp64, [BWPort1], 3, [1], 1, 5>; // Floating point double compare. 263defm : BWWriteResPair<WriteFCmp64X, [BWPort1], 3, [1], 1, 5>; // Floating point double compare (XMM). 264defm : BWWriteResPair<WriteFCmp64Y, [BWPort1], 3, [1], 1, 6>; // Floating point double compare (YMM/ZMM). 265defm : X86WriteResPairUnsupported<WriteFCmp64Z>; 266 267defm : BWWriteResPair<WriteFCom, [BWPort1], 3>; // Floating point compare to flags (X87). 268defm : BWWriteResPair<WriteFComX, [BWPort1], 3>; // Floating point compare to flags (SSE). 269 270defm : BWWriteResPair<WriteFMul, [BWPort01], 3, [1], 1, 5>; // Floating point multiplication. 271defm : BWWriteResPair<WriteFMulX, [BWPort01], 3, [1], 1, 5>; // Floating point multiplication (XMM). 272defm : BWWriteResPair<WriteFMulY, [BWPort01], 3, [1], 1, 6>; // Floating point multiplication (YMM/ZMM). 273defm : X86WriteResPairUnsupported<WriteFMulZ>; 274defm : BWWriteResPair<WriteFMul64, [BWPort01], 3, [1], 1, 5>; // Floating point double multiplication. 275defm : BWWriteResPair<WriteFMul64X, [BWPort01], 3, [1], 1, 5>; // Floating point double multiplication (XMM). 276defm : BWWriteResPair<WriteFMul64Y, [BWPort01], 3, [1], 1, 6>; // Floating point double multiplication (YMM/ZMM). 277defm : X86WriteResPairUnsupported<WriteFMul64Z>; 278 279//defm : BWWriteResPair<WriteFDiv, [BWPort0,BWFPDivider], 11, [1,3], 1, 5>; // Floating point division. 280defm : BWWriteResPair<WriteFDivX, [BWPort0,BWFPDivider], 11, [1,5], 1, 5>; // Floating point division (XMM). 281defm : BWWriteResPair<WriteFDivY, [BWPort0,BWPort015,BWFPDivider], 17, [2,1,10], 3, 6>; // Floating point division (YMM). 282defm : X86WriteResPairUnsupported<WriteFDivZ>; 283//defm : BWWriteResPair<WriteFDiv64, [BWPort0,BWFPDivider], 14, [1,8], 1, 5>; // Floating point division. 284defm : BWWriteResPair<WriteFDiv64X, [BWPort0,BWFPDivider], 14, [1,8], 1, 5>; // Floating point division (XMM). 285defm : BWWriteResPair<WriteFDiv64Y, [BWPort0,BWPort015,BWFPDivider], 23, [2,1,16], 3, 6>; // Floating point division (YMM). 286defm : X86WriteResPairUnsupported<WriteFDiv64Z>; 287 288defm : X86WriteRes<WriteFSqrt, [BWPort0,BWFPDivider], 11, [1,4], 1>; // Floating point square root. 289defm : X86WriteRes<WriteFSqrtLd, [BWPort0,BWPort23,BWFPDivider], 16, [1,1,7], 2>; 290defm : BWWriteResPair<WriteFSqrtX, [BWPort0,BWFPDivider], 11, [1,7], 1, 5>; // Floating point square root (XMM). 291defm : BWWriteResPair<WriteFSqrtY, [BWPort0,BWPort015,BWFPDivider], 21, [2,1,14], 3, 6>; // Floating point square root (YMM). 292defm : X86WriteResPairUnsupported<WriteFSqrtZ>; 293defm : X86WriteRes<WriteFSqrt64, [BWPort0,BWFPDivider], 16, [1,8], 1>; // Floating point double square root. 294defm : X86WriteRes<WriteFSqrt64Ld, [BWPort0,BWPort23,BWFPDivider], 21, [1,1,14], 2>; 295defm : BWWriteResPair<WriteFSqrt64X, [BWPort0,BWFPDivider], 16, [1,14],1, 5>; // Floating point double square root (XMM). 296defm : BWWriteResPair<WriteFSqrt64Y, [BWPort0,BWPort015,BWFPDivider], 29, [2,1,28], 3, 6>; // Floating point double square root (YMM). 297defm : X86WriteResPairUnsupported<WriteFSqrt64Z>; 298defm : BWWriteResPair<WriteFSqrt80, [BWPort0,BWFPDivider], 23, [1,9]>; // Floating point long double square root. 299 300defm : BWWriteResPair<WriteFRcp, [BWPort0], 5, [1], 1, 5>; // Floating point reciprocal estimate. 301defm : BWWriteResPair<WriteFRcpX, [BWPort0], 5, [1], 1, 5>; // Floating point reciprocal estimate (XMM). 302defm : BWWriteResPair<WriteFRcpY, [BWPort0,BWPort015], 11, [2,1], 3, 6>; // Floating point reciprocal estimate (YMM/ZMM). 303defm : X86WriteResPairUnsupported<WriteFRcpZ>; 304 305defm : BWWriteResPair<WriteFRsqrt, [BWPort0], 5, [1], 1, 5>; // Floating point reciprocal square root estimate. 306defm : BWWriteResPair<WriteFRsqrtX,[BWPort0], 5, [1], 1, 5>; // Floating point reciprocal square root estimate (XMM). 307defm : BWWriteResPair<WriteFRsqrtY,[BWPort0,BWPort015], 11, [2,1], 3, 6>; // Floating point reciprocal square root estimate (YMM/ZMM). 308defm : X86WriteResPairUnsupported<WriteFRsqrtZ>; 309 310defm : BWWriteResPair<WriteFMA, [BWPort01], 5, [1], 1, 5>; // Fused Multiply Add. 311defm : BWWriteResPair<WriteFMAX, [BWPort01], 5, [1], 1, 5>; // Fused Multiply Add (XMM). 312defm : BWWriteResPair<WriteFMAY, [BWPort01], 5, [1], 1, 6>; // Fused Multiply Add (YMM/ZMM). 313defm : X86WriteResPairUnsupported<WriteFMAZ>; 314defm : BWWriteResPair<WriteDPPD, [BWPort0,BWPort1,BWPort5], 9, [1,1,1], 3, 5>; // Floating point double dot product. 315defm : BWWriteResPair<WriteDPPS, [BWPort0,BWPort1,BWPort5], 14, [2,1,1], 4, 5>; // Floating point single dot product. 316defm : BWWriteResPair<WriteDPPSY, [BWPort0,BWPort1,BWPort5], 14, [2,1,1], 4, 6>; // Floating point single dot product (YMM). 317defm : X86WriteResPairUnsupported<WriteDPPSZ>; 318defm : BWWriteResPair<WriteFSign, [BWPort5], 1>; // Floating point fabs/fchs. 319defm : X86WriteRes<WriteFRnd, [BWPort23], 6, [1], 1>; // Floating point rounding. 320defm : X86WriteRes<WriteFRndY, [BWPort23], 6, [1], 1>; // Floating point rounding (YMM/ZMM). 321defm : X86WriteResPairUnsupported<WriteFRndZ>; 322defm : X86WriteRes<WriteFRndLd, [BWPort1,BWPort23], 11, [2,1], 3>; 323defm : X86WriteRes<WriteFRndYLd, [BWPort1,BWPort23], 12, [2,1], 3>; 324defm : BWWriteResPair<WriteFLogic, [BWPort5], 1, [1], 1, 5>; // Floating point and/or/xor logicals. 325defm : BWWriteResPair<WriteFLogicY, [BWPort5], 1, [1], 1, 6>; // Floating point and/or/xor logicals (YMM/ZMM). 326defm : X86WriteResPairUnsupported<WriteFLogicZ>; 327defm : BWWriteResPair<WriteFTest, [BWPort0], 1, [1], 1, 5>; // Floating point TEST instructions. 328defm : BWWriteResPair<WriteFTestY, [BWPort0], 1, [1], 1, 6>; // Floating point TEST instructions (YMM/ZMM). 329defm : X86WriteResPairUnsupported<WriteFTestZ>; 330defm : BWWriteResPair<WriteFShuffle, [BWPort5], 1, [1], 1, 5>; // Floating point vector shuffles. 331defm : BWWriteResPair<WriteFShuffleY, [BWPort5], 1, [1], 1, 6>; // Floating point vector shuffles (YMM/ZMM). 332defm : X86WriteResPairUnsupported<WriteFShuffleZ>; 333defm : BWWriteResPair<WriteFVarShuffle, [BWPort5], 1, [1], 1, 5>; // Floating point vector variable shuffles. 334defm : BWWriteResPair<WriteFVarShuffleY, [BWPort5], 1, [1], 1, 6>; // Floating point vector variable shuffles. 335defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>; 336defm : BWWriteResPair<WriteFBlend, [BWPort015], 1, [1], 1, 5>; // Floating point vector blends. 337defm : BWWriteResPair<WriteFBlendY, [BWPort015], 1, [1], 1, 6>; // Floating point vector blends. 338defm : X86WriteResPairUnsupported<WriteFBlendZ>; 339defm : BWWriteResPair<WriteFVarBlend, [BWPort5], 2, [2], 2, 5>; // Fp vector variable blends. 340defm : BWWriteResPair<WriteFVarBlendY, [BWPort5], 2, [2], 2, 6>; // Fp vector variable blends. 341defm : X86WriteResPairUnsupported<WriteFVarBlendZ>; 342 343// FMA Scheduling helper class. 344// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } 345 346// Vector integer operations. 347defm : X86WriteRes<WriteVecLoad, [BWPort23], 5, [1], 1>; 348defm : X86WriteRes<WriteVecLoadX, [BWPort23], 5, [1], 1>; 349defm : X86WriteRes<WriteVecLoadY, [BWPort23], 6, [1], 1>; 350defm : X86WriteRes<WriteVecLoadNT, [BWPort23], 5, [1], 1>; 351defm : X86WriteRes<WriteVecLoadNTY, [BWPort23], 6, [1], 1>; 352defm : X86WriteRes<WriteVecMaskedLoad, [BWPort23,BWPort5], 7, [1,2], 3>; 353defm : X86WriteRes<WriteVecMaskedLoadY, [BWPort23,BWPort5], 8, [1,2], 3>; 354defm : X86WriteRes<WriteVecStore, [BWPort237,BWPort4], 1, [1,1], 2>; 355defm : X86WriteRes<WriteVecStoreX, [BWPort237,BWPort4], 1, [1,1], 2>; 356defm : X86WriteRes<WriteVecStoreY, [BWPort237,BWPort4], 1, [1,1], 2>; 357defm : X86WriteRes<WriteVecStoreNT, [BWPort237,BWPort4], 1, [1,1], 2>; 358defm : X86WriteRes<WriteVecStoreNTY, [BWPort237,BWPort4], 1, [1,1], 2>; 359defm : X86WriteRes<WriteVecMaskedStore32, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>; 360defm : X86WriteRes<WriteVecMaskedStore32Y, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>; 361defm : X86WriteRes<WriteVecMaskedStore64, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>; 362defm : X86WriteRes<WriteVecMaskedStore64Y, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>; 363defm : X86WriteRes<WriteVecMove, [BWPort015], 1, [1], 1>; 364defm : X86WriteRes<WriteVecMoveX, [BWPort015], 1, [1], 1>; 365defm : X86WriteRes<WriteVecMoveY, [BWPort015], 1, [1], 1>; 366defm : X86WriteRes<WriteVecMoveToGpr, [BWPort0], 1, [1], 1>; 367defm : X86WriteRes<WriteVecMoveFromGpr, [BWPort5], 1, [1], 1>; 368 369defm : X86WriteRes<WriteEMMS, [BWPort01,BWPort15,BWPort015,BWPort0156], 31, [8,1,21,1], 31>; 370 371defm : BWWriteResPair<WriteVecALU, [BWPort15], 1, [1], 1, 5>; // Vector integer ALU op, no logicals. 372defm : BWWriteResPair<WriteVecALUX, [BWPort15], 1, [1], 1, 5>; // Vector integer ALU op, no logicals. 373defm : BWWriteResPair<WriteVecALUY, [BWPort15], 1, [1], 1, 6>; // Vector integer ALU op, no logicals (YMM/ZMM). 374defm : X86WriteResPairUnsupported<WriteVecALUZ>; 375defm : BWWriteResPair<WriteVecLogic, [BWPort015], 1, [1], 1, 5>; // Vector integer and/or/xor. 376defm : BWWriteResPair<WriteVecLogicX,[BWPort015], 1, [1], 1, 5>; // Vector integer and/or/xor. 377defm : BWWriteResPair<WriteVecLogicY,[BWPort015], 1, [1], 1, 6>; // Vector integer and/or/xor (YMM/ZMM). 378defm : X86WriteResPairUnsupported<WriteVecLogicZ>; 379defm : BWWriteResPair<WriteVecTest, [BWPort0,BWPort5], 2, [1,1], 2, 5>; // Vector integer TEST instructions. 380defm : BWWriteResPair<WriteVecTestY, [BWPort0,BWPort5], 4, [1,1], 2, 6>; // Vector integer TEST instructions (YMM/ZMM). 381defm : X86WriteResPairUnsupported<WriteVecTestZ>; 382defm : BWWriteResPair<WriteVecIMul, [BWPort0], 5, [1], 1, 5>; // Vector integer multiply. 383defm : BWWriteResPair<WriteVecIMulX, [BWPort0], 5, [1], 1, 5>; // Vector integer multiply. 384defm : BWWriteResPair<WriteVecIMulY, [BWPort0], 5, [1], 1, 6>; // Vector integer multiply. 385defm : X86WriteResPairUnsupported<WriteVecIMulZ>; 386defm : BWWriteResPair<WritePMULLD, [BWPort0], 10, [2], 2, 5>; // Vector PMULLD. 387defm : BWWriteResPair<WritePMULLDY, [BWPort0], 10, [2], 2, 6>; // Vector PMULLD (YMM/ZMM). 388defm : X86WriteResPairUnsupported<WritePMULLDZ>; 389defm : BWWriteResPair<WriteShuffle, [BWPort5], 1, [1], 1, 5>; // Vector shuffles. 390defm : BWWriteResPair<WriteShuffleX, [BWPort5], 1, [1], 1, 5>; // Vector shuffles. 391defm : BWWriteResPair<WriteShuffleY, [BWPort5], 1, [1], 1, 6>; // Vector shuffles (YMM/ZMM). 392defm : X86WriteResPairUnsupported<WriteShuffleZ>; 393defm : BWWriteResPair<WriteVarShuffle, [BWPort5], 1, [1], 1, 5>; // Vector variable shuffles. 394defm : BWWriteResPair<WriteVarShuffleX,[BWPort5], 1, [1], 1, 5>; // Vector variable shuffles. 395defm : BWWriteResPair<WriteVarShuffleY,[BWPort5], 1, [1], 1, 6>; // Vector variable shuffles (YMM/ZMM). 396defm : X86WriteResPairUnsupported<WriteVarShuffleZ>; 397defm : BWWriteResPair<WriteBlend, [BWPort5], 1, [1], 1, 5>; // Vector blends. 398defm : BWWriteResPair<WriteBlendY, [BWPort5], 1, [1], 1, 6>; // Vector blends (YMM/ZMM). 399defm : X86WriteResPairUnsupported<WriteBlendZ>; 400defm : BWWriteResPair<WriteVarBlend, [BWPort5], 2, [2], 2, 5>; // Vector variable blends. 401defm : BWWriteResPair<WriteVarBlendY, [BWPort5], 2, [2], 2, 6>; // Vector variable blends (YMM/ZMM). 402defm : X86WriteResPairUnsupported<WriteVarBlendZ>; 403defm : BWWriteResPair<WriteMPSAD, [BWPort0, BWPort5], 7, [1, 2], 3, 5>; // Vector MPSAD. 404defm : BWWriteResPair<WriteMPSADY, [BWPort0, BWPort5], 7, [1, 2], 3, 6>; // Vector MPSAD. 405defm : X86WriteResPairUnsupported<WriteMPSADZ>; 406defm : BWWriteResPair<WritePSADBW, [BWPort0], 5, [1], 1, 5>; // Vector PSADBW. 407defm : BWWriteResPair<WritePSADBWX, [BWPort0], 5, [1], 1, 5>; // Vector PSADBW. 408defm : BWWriteResPair<WritePSADBWY, [BWPort0], 5, [1], 1, 6>; // Vector PSADBW (YMM/ZMM). 409defm : X86WriteResPairUnsupported<WritePSADBWZ>; 410defm : BWWriteResPair<WritePHMINPOS, [BWPort0], 5>; // Vector PHMINPOS. 411 412// Vector integer shifts. 413defm : BWWriteResPair<WriteVecShift, [BWPort0], 1, [1], 1, 5>; 414defm : BWWriteResPair<WriteVecShiftX, [BWPort0,BWPort5], 2, [1,1], 2, 5>; 415defm : X86WriteRes<WriteVecShiftY, [BWPort0,BWPort5], 4, [1,1], 2>; 416defm : X86WriteRes<WriteVecShiftYLd, [BWPort0,BWPort23], 7, [1,1], 2>; 417defm : X86WriteResPairUnsupported<WriteVecShiftZ>; 418 419defm : BWWriteResPair<WriteVecShiftImm, [BWPort0], 1, [1], 1, 5>; 420defm : BWWriteResPair<WriteVecShiftImmX, [BWPort0], 1, [1], 1, 5>; // Vector integer immediate shifts (XMM). 421defm : BWWriteResPair<WriteVecShiftImmY, [BWPort0], 1, [1], 1, 6>; // Vector integer immediate shifts (YMM/ZMM). 422defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>; 423defm : BWWriteResPair<WriteVarVecShift, [BWPort0, BWPort5], 3, [2,1], 3, 5>; // Variable vector shifts. 424defm : BWWriteResPair<WriteVarVecShiftY, [BWPort0, BWPort5], 3, [2,1], 3, 6>; // Variable vector shifts (YMM/ZMM). 425defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>; 426 427// Vector insert/extract operations. 428def : WriteRes<WriteVecInsert, [BWPort5]> { 429 let Latency = 2; 430 let NumMicroOps = 2; 431 let ResourceCycles = [2]; 432} 433def : WriteRes<WriteVecInsertLd, [BWPort5,BWPort23]> { 434 let Latency = 6; 435 let NumMicroOps = 2; 436} 437 438def : WriteRes<WriteVecExtract, [BWPort0,BWPort5]> { 439 let Latency = 2; 440 let NumMicroOps = 2; 441} 442def : WriteRes<WriteVecExtractSt, [BWPort4,BWPort5,BWPort237]> { 443 let Latency = 2; 444 let NumMicroOps = 3; 445} 446 447// Conversion between integer and float. 448defm : BWWriteResPair<WriteCvtSS2I, [BWPort1], 3>; 449defm : BWWriteResPair<WriteCvtPS2I, [BWPort1], 3>; 450defm : BWWriteResPair<WriteCvtPS2IY, [BWPort1], 3>; 451defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>; 452defm : BWWriteResPair<WriteCvtSD2I, [BWPort1], 3>; 453defm : BWWriteResPair<WriteCvtPD2I, [BWPort1], 3>; 454defm : BWWriteResPair<WriteCvtPD2IY, [BWPort1], 3>; 455defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>; 456 457defm : BWWriteResPair<WriteCvtI2SS, [BWPort1], 4>; 458defm : BWWriteResPair<WriteCvtI2PS, [BWPort1], 4>; 459defm : BWWriteResPair<WriteCvtI2PSY, [BWPort1], 4>; 460defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>; 461defm : BWWriteResPair<WriteCvtI2SD, [BWPort1], 4>; 462defm : BWWriteResPair<WriteCvtI2PD, [BWPort1], 4>; 463defm : BWWriteResPair<WriteCvtI2PDY, [BWPort1], 4>; 464defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>; 465 466defm : BWWriteResPair<WriteCvtSS2SD, [BWPort1], 3>; 467defm : BWWriteResPair<WriteCvtPS2PD, [BWPort1], 3>; 468defm : BWWriteResPair<WriteCvtPS2PDY, [BWPort1], 3>; 469defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>; 470defm : BWWriteResPair<WriteCvtSD2SS, [BWPort1], 3>; 471defm : BWWriteResPair<WriteCvtPD2PS, [BWPort1], 3>; 472defm : BWWriteResPair<WriteCvtPD2PSY, [BWPort1], 3>; 473defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>; 474 475defm : X86WriteRes<WriteCvtPH2PS, [BWPort0,BWPort5], 2, [1,1], 2>; 476defm : X86WriteRes<WriteCvtPH2PSY, [BWPort0,BWPort5], 2, [1,1], 2>; 477defm : X86WriteResUnsupported<WriteCvtPH2PSZ>; 478defm : X86WriteRes<WriteCvtPH2PSLd, [BWPort0,BWPort23], 6, [1,1], 2>; 479defm : X86WriteRes<WriteCvtPH2PSYLd, [BWPort0,BWPort23], 6, [1,1], 2>; 480defm : X86WriteResUnsupported<WriteCvtPH2PSZLd>; 481 482defm : X86WriteRes<WriteCvtPS2PH, [BWPort1,BWPort5], 4, [1,1], 2>; 483defm : X86WriteRes<WriteCvtPS2PHY, [BWPort1,BWPort5], 6, [1,1], 2>; 484defm : X86WriteResUnsupported<WriteCvtPS2PHZ>; 485defm : X86WriteRes<WriteCvtPS2PHSt, [BWPort1,BWPort4,BWPort237], 5, [1,1,1], 3>; 486defm : X86WriteRes<WriteCvtPS2PHYSt, [BWPort1,BWPort4,BWPort237], 7, [1,1,1], 3>; 487defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>; 488 489// Strings instructions. 490 491// Packed Compare Implicit Length Strings, Return Mask 492def : WriteRes<WritePCmpIStrM, [BWPort0]> { 493 let Latency = 11; 494 let NumMicroOps = 3; 495 let ResourceCycles = [3]; 496} 497def : WriteRes<WritePCmpIStrMLd, [BWPort0, BWPort23]> { 498 let Latency = 16; 499 let NumMicroOps = 4; 500 let ResourceCycles = [3,1]; 501} 502 503// Packed Compare Explicit Length Strings, Return Mask 504def : WriteRes<WritePCmpEStrM, [BWPort0, BWPort5, BWPort015, BWPort0156]> { 505 let Latency = 19; 506 let NumMicroOps = 9; 507 let ResourceCycles = [4,3,1,1]; 508} 509def : WriteRes<WritePCmpEStrMLd, [BWPort0, BWPort5, BWPort23, BWPort015, BWPort0156]> { 510 let Latency = 24; 511 let NumMicroOps = 10; 512 let ResourceCycles = [4,3,1,1,1]; 513} 514 515// Packed Compare Implicit Length Strings, Return Index 516def : WriteRes<WritePCmpIStrI, [BWPort0]> { 517 let Latency = 11; 518 let NumMicroOps = 3; 519 let ResourceCycles = [3]; 520} 521def : WriteRes<WritePCmpIStrILd, [BWPort0, BWPort23]> { 522 let Latency = 16; 523 let NumMicroOps = 4; 524 let ResourceCycles = [3,1]; 525} 526 527// Packed Compare Explicit Length Strings, Return Index 528def : WriteRes<WritePCmpEStrI, [BWPort0, BWPort5, BWPort0156]> { 529 let Latency = 18; 530 let NumMicroOps = 8; 531 let ResourceCycles = [4,3,1]; 532} 533def : WriteRes<WritePCmpEStrILd, [BWPort0, BWPort5, BWPort23, BWPort0156]> { 534 let Latency = 23; 535 let NumMicroOps = 9; 536 let ResourceCycles = [4,3,1,1]; 537} 538 539// MOVMSK Instructions. 540def : WriteRes<WriteFMOVMSK, [BWPort0]> { let Latency = 3; } 541def : WriteRes<WriteVecMOVMSK, [BWPort0]> { let Latency = 3; } 542def : WriteRes<WriteVecMOVMSKY, [BWPort0]> { let Latency = 3; } 543def : WriteRes<WriteMMXMOVMSK, [BWPort0]> { let Latency = 1; } 544 545// AES instructions. 546def : WriteRes<WriteAESDecEnc, [BWPort5]> { // Decryption, encryption. 547 let Latency = 7; 548 let NumMicroOps = 1; 549 let ResourceCycles = [1]; 550} 551def : WriteRes<WriteAESDecEncLd, [BWPort5, BWPort23]> { 552 let Latency = 12; 553 let NumMicroOps = 2; 554 let ResourceCycles = [1,1]; 555} 556 557def : WriteRes<WriteAESIMC, [BWPort5]> { // InvMixColumn. 558 let Latency = 14; 559 let NumMicroOps = 2; 560 let ResourceCycles = [2]; 561} 562def : WriteRes<WriteAESIMCLd, [BWPort5, BWPort23]> { 563 let Latency = 19; 564 let NumMicroOps = 3; 565 let ResourceCycles = [2,1]; 566} 567 568def : WriteRes<WriteAESKeyGen, [BWPort0, BWPort5, BWPort015]> { // Key Generation. 569 let Latency = 29; 570 let NumMicroOps = 11; 571 let ResourceCycles = [2,7,2]; 572} 573def : WriteRes<WriteAESKeyGenLd, [BWPort0, BWPort5, BWPort23, BWPort015]> { 574 let Latency = 33; 575 let NumMicroOps = 11; 576 let ResourceCycles = [2,7,1,1]; 577} 578 579// Carry-less multiplication instructions. 580defm : BWWriteResPair<WriteCLMul, [BWPort0], 5>; 581 582// Catch-all for expensive system instructions. 583def : WriteRes<WriteSystem, [BWPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite; 584 585// AVX2. 586defm : BWWriteResPair<WriteFShuffle256, [BWPort5], 3, [1], 1, 6>; // Fp 256-bit width vector shuffles. 587defm : BWWriteResPair<WriteFVarShuffle256, [BWPort5], 3, [1], 1, 6>; // Fp 256-bit width vector variable shuffles. 588defm : BWWriteResPair<WriteShuffle256, [BWPort5], 3, [1], 1, 6>; // 256-bit width vector shuffles. 589defm : BWWriteResPair<WriteVPMOV256, [BWPort5], 3, [1], 1, 6>; // 256-bit width packed vector width-changing move. 590defm : BWWriteResPair<WriteVarShuffle256, [BWPort5], 3, [1], 1, 6>; // 256-bit width vector variable shuffles. 591 592// Old microcoded instructions that nobody use. 593def : WriteRes<WriteMicrocoded, [BWPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite; 594 595// Fence instructions. 596def : WriteRes<WriteFence, [BWPort23, BWPort4]>; 597 598// Load/store MXCSR. 599def : WriteRes<WriteLDMXCSR, [BWPort0,BWPort23,BWPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 600def : WriteRes<WriteSTMXCSR, [BWPort4,BWPort5,BWPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 601 602// Nop, not very useful expect it provides a model for nops! 603def : WriteRes<WriteNop, []>; 604 605//////////////////////////////////////////////////////////////////////////////// 606// Horizontal add/sub instructions. 607//////////////////////////////////////////////////////////////////////////////// 608 609defm : BWWriteResPair<WriteFHAdd, [BWPort1,BWPort5], 5, [1,2], 3, 5>; 610defm : BWWriteResPair<WriteFHAddY, [BWPort1,BWPort5], 5, [1,2], 3, 6>; 611defm : BWWriteResPair<WritePHAdd, [BWPort5,BWPort15], 3, [2,1], 3, 5>; 612defm : BWWriteResPair<WritePHAddX, [BWPort5,BWPort15], 3, [2,1], 3, 5>; 613defm : BWWriteResPair<WritePHAddY, [BWPort5,BWPort15], 3, [2,1], 3, 6>; 614 615// Remaining instrs. 616 617def BWWriteResGroup1 : SchedWriteRes<[BWPort0]> { 618 let Latency = 1; 619 let NumMicroOps = 1; 620 let ResourceCycles = [1]; 621} 622def: InstRW<[BWWriteResGroup1], (instregex "VPSLLVQ(Y?)rr", 623 "VPSRLVQ(Y?)rr")>; 624 625def BWWriteResGroup2 : SchedWriteRes<[BWPort1]> { 626 let Latency = 1; 627 let NumMicroOps = 1; 628 let ResourceCycles = [1]; 629} 630def: InstRW<[BWWriteResGroup2], (instregex "COM(P?)_FST0r", 631 "UCOM_F(P?)r")>; 632 633def BWWriteResGroup3 : SchedWriteRes<[BWPort5]> { 634 let Latency = 1; 635 let NumMicroOps = 1; 636 let ResourceCycles = [1]; 637} 638def: InstRW<[BWWriteResGroup3], (instrs MMX_MOVQ2DQrr)>; 639 640def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> { 641 let Latency = 1; 642 let NumMicroOps = 1; 643 let ResourceCycles = [1]; 644} 645def: InstRW<[BWWriteResGroup4], (instregex "JMP(16|32|64)r")>; 646 647def BWWriteResGroup5 : SchedWriteRes<[BWPort01]> { 648 let Latency = 1; 649 let NumMicroOps = 1; 650 let ResourceCycles = [1]; 651} 652def: InstRW<[BWWriteResGroup5], (instrs FINCSTP, FNOP)>; 653 654def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> { 655 let Latency = 1; 656 let NumMicroOps = 1; 657 let ResourceCycles = [1]; 658} 659def: InstRW<[BWWriteResGroup6], (instrs CDQ, CQO)>; 660 661def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> { 662 let Latency = 1; 663 let NumMicroOps = 1; 664 let ResourceCycles = [1]; 665} 666def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr")>; 667 668def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> { 669 let Latency = 1; 670 let NumMicroOps = 1; 671 let ResourceCycles = [1]; 672} 673def: InstRW<[BWWriteResGroup8], (instregex "VPBLENDD(Y?)rri")>; 674 675def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> { 676 let Latency = 1; 677 let NumMicroOps = 1; 678 let ResourceCycles = [1]; 679} 680def: InstRW<[BWWriteResGroup9], (instrs SGDT64m, 681 SIDT64m, 682 SMSW16m, 683 STRm, 684 SYSCALL)>; 685 686def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> { 687 let Latency = 1; 688 let NumMicroOps = 2; 689 let ResourceCycles = [1,1]; 690} 691def: InstRW<[BWWriteResGroup10], (instrs FBSTPm)>; 692def: InstRW<[BWWriteResGroup10], (instregex "ST_FP(32|64|80)m")>; 693 694def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> { 695 let Latency = 2; 696 let NumMicroOps = 2; 697 let ResourceCycles = [2]; 698} 699def: InstRW<[BWWriteResGroup12], (instrs FDECSTP)>; 700 701def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> { 702 let Latency = 2; 703 let NumMicroOps = 2; 704 let ResourceCycles = [2]; 705} 706def: InstRW<[BWWriteResGroup14], (instrs LFENCE, 707 MFENCE, 708 WAIT, 709 XGETBV)>; 710 711def BWWriteResGroup15 : SchedWriteRes<[BWPort0,BWPort5]> { 712 let Latency = 2; 713 let NumMicroOps = 2; 714 let ResourceCycles = [1,1]; 715} 716def: InstRW<[BWWriteResGroup15], (instregex "(V?)CVTPS2PDrr", 717 "(V?)CVTSS2SDrr")>; 718 719def BWWriteResGroup16 : SchedWriteRes<[BWPort6,BWPort0156]> { 720 let Latency = 2; 721 let NumMicroOps = 2; 722 let ResourceCycles = [1,1]; 723} 724def: InstRW<[BWWriteResGroup16], (instregex "CLFLUSH")>; 725 726def BWWriteResGroup17 : SchedWriteRes<[BWPort01,BWPort015]> { 727 let Latency = 2; 728 let NumMicroOps = 2; 729 let ResourceCycles = [1,1]; 730} 731def: InstRW<[BWWriteResGroup17], (instrs MMX_MOVDQ2Qrr)>; 732 733def BWWriteResGroup18 : SchedWriteRes<[BWPort237,BWPort0156]> { 734 let Latency = 2; 735 let NumMicroOps = 2; 736 let ResourceCycles = [1,1]; 737} 738def: InstRW<[BWWriteResGroup18], (instrs SFENCE)>; 739 740def BWWriteResGroup20 : SchedWriteRes<[BWPort06,BWPort0156]> { 741 let Latency = 2; 742 let NumMicroOps = 2; 743 let ResourceCycles = [1,1]; 744} 745def: InstRW<[BWWriteResGroup20], (instrs CWD, 746 JCXZ, JECXZ, JRCXZ, 747 ADC8i8, SBB8i8, 748 ADC16i16, SBB16i16, 749 ADC32i32, SBB32i32, 750 ADC64i32, SBB64i32)>; 751 752def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> { 753 let Latency = 2; 754 let NumMicroOps = 3; 755 let ResourceCycles = [1,1,1]; 756} 757def: InstRW<[BWWriteResGroup22], (instrs FNSTCW16m)>; 758 759def BWWriteResGroup24 : SchedWriteRes<[BWPort4,BWPort237,BWPort15]> { 760 let Latency = 2; 761 let NumMicroOps = 3; 762 let ResourceCycles = [1,1,1]; 763} 764def: InstRW<[BWWriteResGroup24], (instregex "MOVBE(16|32|64)mr")>; 765 766def BWWriteResGroup25 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> { 767 let Latency = 2; 768 let NumMicroOps = 3; 769 let ResourceCycles = [1,1,1]; 770} 771def: InstRW<[BWWriteResGroup25], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8, 772 STOSB, STOSL, STOSQ, STOSW)>; 773def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)rmr")>; 774 775def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> { 776 let Latency = 3; 777 let NumMicroOps = 1; 778 let ResourceCycles = [1]; 779} 780def: InstRW<[BWWriteResGroup27], (instrs MMX_CVTPI2PSirr)>; 781def: InstRW<[BWWriteResGroup27], (instregex "P(DEP|EXT)(32|64)rr", 782 "(V?)CVTDQ2PS(Y?)rr")>; 783 784def BWWriteResGroup28 : SchedWriteRes<[BWPort5]> { 785 let Latency = 3; 786 let NumMicroOps = 1; 787 let ResourceCycles = [1]; 788} 789def: InstRW<[BWWriteResGroup28], (instrs VPBROADCASTBrr, 790 VPBROADCASTWrr)>; 791 792def BWWriteResGroup33 : SchedWriteRes<[BWPort5,BWPort0156]> { 793 let Latency = 3; 794 let NumMicroOps = 3; 795 let ResourceCycles = [2,1]; 796} 797def: InstRW<[BWWriteResGroup33], (instrs MMX_PACKSSDWirr, 798 MMX_PACKSSWBirr, 799 MMX_PACKUSWBirr)>; 800 801def BWWriteResGroup34 : SchedWriteRes<[BWPort6,BWPort0156]> { 802 let Latency = 3; 803 let NumMicroOps = 3; 804 let ResourceCycles = [1,2]; 805} 806def: InstRW<[BWWriteResGroup34], (instregex "CLD")>; 807 808def BWWriteResGroup35 : SchedWriteRes<[BWPort06,BWPort0156]> { 809 let Latency = 3; 810 let NumMicroOps = 3; 811 let ResourceCycles = [1,2]; 812} 813def: InstRW<[BWWriteResGroup35], (instregex "RCL(8|16|32|64)r(1|i)", 814 "RCR(8|16|32|64)r(1|i)")>; 815 816def BWWriteResGroup37 : SchedWriteRes<[BWPort4,BWPort6,BWPort237,BWPort0156]> { 817 let Latency = 3; 818 let NumMicroOps = 4; 819 let ResourceCycles = [1,1,1,1]; 820} 821def: InstRW<[BWWriteResGroup37], (instregex "CALL(16|32|64)r")>; 822 823def BWWriteResGroup38 : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> { 824 let Latency = 3; 825 let NumMicroOps = 4; 826 let ResourceCycles = [1,1,1,1]; 827} 828def: InstRW<[BWWriteResGroup38], (instrs CALL64pcrel32)>; 829 830def BWWriteResGroup39 : SchedWriteRes<[BWPort0,BWPort1]> { 831 let Latency = 4; 832 let NumMicroOps = 2; 833 let ResourceCycles = [1,1]; 834} 835def: InstRW<[BWWriteResGroup39], (instregex "(V?)CVT(T?)SD2SI64rr", 836 "(V?)CVT(T?)SD2SIrr", 837 "(V?)CVT(T?)SS2SI64rr", 838 "(V?)CVT(T?)SS2SIrr")>; 839 840def BWWriteResGroup40 : SchedWriteRes<[BWPort0,BWPort5]> { 841 let Latency = 4; 842 let NumMicroOps = 2; 843 let ResourceCycles = [1,1]; 844} 845def: InstRW<[BWWriteResGroup40], (instrs VCVTPS2PDYrr)>; 846 847def BWWriteResGroup41 : SchedWriteRes<[BWPort0,BWPort0156]> { 848 let Latency = 4; 849 let NumMicroOps = 2; 850 let ResourceCycles = [1,1]; 851} 852def: InstRW<[BWWriteResGroup41], (instrs FNSTSW16r)>; 853 854def BWWriteResGroup42 : SchedWriteRes<[BWPort1,BWPort5]> { 855 let Latency = 4; 856 let NumMicroOps = 2; 857 let ResourceCycles = [1,1]; 858} 859def: InstRW<[BWWriteResGroup42], (instrs MMX_CVTPI2PDirr)>; 860def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVT(T?)PD2PIirr", 861 "MMX_CVT(T?)PS2PIirr", 862 "(V?)CVTDQ2PDrr", 863 "(V?)CVTPD2PSrr", 864 "(V?)CVTSD2SSrr", 865 "(V?)CVTSI642SDrr", 866 "(V?)CVTSI2SDrr", 867 "(V?)CVTSI2SSrr", 868 "(V?)CVT(T?)PD2DQrr")>; 869 870def BWWriteResGroup43 : SchedWriteRes<[BWPort0,BWPort4,BWPort237]> { 871 let Latency = 4; 872 let NumMicroOps = 3; 873 let ResourceCycles = [1,1,1]; 874} 875def: InstRW<[BWWriteResGroup43], (instrs FNSTSWm)>; 876 877def BWWriteResGroup44 : SchedWriteRes<[BWPort1,BWPort4,BWPort237]> { 878 let Latency = 4; 879 let NumMicroOps = 3; 880 let ResourceCycles = [1,1,1]; 881} 882def: InstRW<[BWWriteResGroup44], (instregex "IST(T?)_FP(16|32|64)m", 883 "IST_F(16|32)m")>; 884 885def BWWriteResGroup45 : SchedWriteRes<[BWPort0156]> { 886 let Latency = 4; 887 let NumMicroOps = 4; 888 let ResourceCycles = [4]; 889} 890def: InstRW<[BWWriteResGroup45], (instrs FNCLEX)>; 891 892def BWWriteResGroup46 : SchedWriteRes<[]> { 893 let Latency = 0; 894 let NumMicroOps = 4; 895 let ResourceCycles = []; 896} 897def: InstRW<[BWWriteResGroup46], (instrs VZEROUPPER)>; 898 899def BWWriteResGroup47 : SchedWriteRes<[BWPort0]> { 900 let Latency = 5; 901 let NumMicroOps = 1; 902 let ResourceCycles = [1]; 903} 904def: InstRW<[BWWriteResGroup47], (instregex "MUL_(FPrST0|FST0r|FrST0)")>; 905 906def BWWriteResGroup49 : SchedWriteRes<[BWPort23]> { 907 let Latency = 5; 908 let NumMicroOps = 1; 909 let ResourceCycles = [1]; 910} 911def: InstRW<[BWWriteResGroup49], (instregex "MOVSX(16|32|64)rm(8|16|32)", 912 "MOVZX(16|32|64)rm(8|16)")>; 913def: InstRW<[BWWriteResGroup49], (instrs VBROADCASTSSrm, 914 VMOVDDUPrm, MOVDDUPrm, 915 VMOVSHDUPrm, MOVSHDUPrm, 916 VMOVSLDUPrm, MOVSLDUPrm, 917 VPBROADCASTDrm, 918 VPBROADCASTQrm)>; 919 920def BWWriteResGroup50 : SchedWriteRes<[BWPort1,BWPort5]> { 921 let Latency = 5; 922 let NumMicroOps = 3; 923 let ResourceCycles = [1,2]; 924} 925def: InstRW<[BWWriteResGroup50], (instregex "(V?)CVTSI642SSrr")>; 926 927def BWWriteResGroup51 : SchedWriteRes<[BWPort1,BWPort6,BWPort06]> { 928 let Latency = 5; 929 let NumMicroOps = 3; 930 let ResourceCycles = [1,1,1]; 931} 932def: InstRW<[BWWriteResGroup51], (instregex "STR(16|32|64)r")>; 933 934def BWWriteResGroup54 : SchedWriteRes<[BWPort6,BWPort0156]> { 935 let Latency = 5; 936 let NumMicroOps = 5; 937 let ResourceCycles = [1,4]; 938} 939def: InstRW<[BWWriteResGroup54], (instrs PAUSE)>; 940 941def BWWriteResGroup55 : SchedWriteRes<[BWPort06,BWPort0156]> { 942 let Latency = 5; 943 let NumMicroOps = 5; 944 let ResourceCycles = [1,4]; 945} 946def: InstRW<[BWWriteResGroup55], (instrs XSETBV)>; 947 948def BWWriteResGroup57 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> { 949 let Latency = 5; 950 let NumMicroOps = 6; 951 let ResourceCycles = [1,1,4]; 952} 953def: InstRW<[BWWriteResGroup57], (instregex "PUSHF(16|64)")>; 954 955def BWWriteResGroup58 : SchedWriteRes<[BWPort23]> { 956 let Latency = 6; 957 let NumMicroOps = 1; 958 let ResourceCycles = [1]; 959} 960def: InstRW<[BWWriteResGroup58], (instregex "LD_F(32|64|80)m")>; 961def: InstRW<[BWWriteResGroup58], (instrs VBROADCASTF128, 962 VBROADCASTI128, 963 VBROADCASTSDYrm, 964 VBROADCASTSSYrm, 965 VMOVDDUPYrm, 966 VMOVSHDUPYrm, 967 VMOVSLDUPYrm, 968 VPBROADCASTDYrm, 969 VPBROADCASTQYrm)>; 970 971def BWWriteResGroup59 : SchedWriteRes<[BWPort0,BWPort23]> { 972 let Latency = 6; 973 let NumMicroOps = 2; 974 let ResourceCycles = [1,1]; 975} 976def: InstRW<[BWWriteResGroup59], (instrs CVTPS2PDrm, VCVTPS2PDrm, 977 CVTSS2SDrm, VCVTSS2SDrm, 978 CVTSS2SDrm_Int, VCVTSS2SDrm_Int, 979 VPSLLVQrm, 980 VPSRLVQrm)>; 981 982def BWWriteResGroup60 : SchedWriteRes<[BWPort1,BWPort5]> { 983 let Latency = 6; 984 let NumMicroOps = 2; 985 let ResourceCycles = [1,1]; 986} 987def: InstRW<[BWWriteResGroup60], (instrs VCVTDQ2PDYrr, 988 VCVTPD2PSYrr, 989 VCVTPD2DQYrr, 990 VCVTTPD2DQYrr)>; 991 992def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> { 993 let Latency = 6; 994 let NumMicroOps = 2; 995 let ResourceCycles = [1,1]; 996} 997def: InstRW<[BWWriteResGroup62], (instrs FARJMP64m)>; 998def: InstRW<[BWWriteResGroup62], (instregex "JMP(16|32|64)m")>; 999 1000def BWWriteResGroup64 : SchedWriteRes<[BWPort23,BWPort15]> { 1001 let Latency = 6; 1002 let NumMicroOps = 2; 1003 let ResourceCycles = [1,1]; 1004} 1005def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm", 1006 "MOVBE(16|32|64)rm")>; 1007 1008def BWWriteResGroup65 : SchedWriteRes<[BWPort23,BWPort015]> { 1009 let Latency = 6; 1010 let NumMicroOps = 2; 1011 let ResourceCycles = [1,1]; 1012} 1013def: InstRW<[BWWriteResGroup65], (instrs VINSERTF128rm, 1014 VINSERTI128rm, 1015 VPBLENDDrmi)>; 1016 1017def BWWriteResGroup66 : SchedWriteRes<[BWPort23,BWPort0156]> { 1018 let Latency = 6; 1019 let NumMicroOps = 2; 1020 let ResourceCycles = [1,1]; 1021} 1022def: InstRW<[BWWriteResGroup66], (instrs POP16r, POP32r, POP64r)>; 1023def: InstRW<[BWWriteResGroup66], (instregex "POP(16|32|64)rmr")>; 1024 1025def BWWriteResGroup68 : SchedWriteRes<[BWPort1,BWPort6,BWPort06,BWPort0156]> { 1026 let Latency = 6; 1027 let NumMicroOps = 4; 1028 let ResourceCycles = [1,1,1,1]; 1029} 1030def: InstRW<[BWWriteResGroup68], (instregex "SLDT(16|32|64)r")>; 1031 1032def BWWriteResGroup69 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> { 1033 let Latency = 6; 1034 let NumMicroOps = 4; 1035 let ResourceCycles = [1,1,1,1]; 1036} 1037def: InstRW<[BWWriteResGroup69], (instregex "SAR(8|16|32|64)m(1|i)", 1038 "SHL(8|16|32|64)m(1|i)", 1039 "SHR(8|16|32|64)m(1|i)")>; 1040 1041def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> { 1042 let Latency = 6; 1043 let NumMicroOps = 4; 1044 let ResourceCycles = [1,1,1,1]; 1045} 1046def: InstRW<[BWWriteResGroup70], (instregex "POP(16|32|64)rmm", 1047 "PUSH(16|32|64)rmm")>; 1048 1049def BWWriteResGroup71 : SchedWriteRes<[BWPort6,BWPort0156]> { 1050 let Latency = 6; 1051 let NumMicroOps = 6; 1052 let ResourceCycles = [1,5]; 1053} 1054def: InstRW<[BWWriteResGroup71], (instrs STD)>; 1055 1056def BWWriteResGroup73 : SchedWriteRes<[BWPort0,BWPort23]> { 1057 let Latency = 7; 1058 let NumMicroOps = 2; 1059 let ResourceCycles = [1,1]; 1060} 1061def: InstRW<[BWWriteResGroup73], (instrs VPSLLVQYrm, 1062 VPSRLVQYrm)>; 1063 1064def BWWriteResGroup74 : SchedWriteRes<[BWPort1,BWPort23]> { 1065 let Latency = 7; 1066 let NumMicroOps = 2; 1067 let ResourceCycles = [1,1]; 1068} 1069def: InstRW<[BWWriteResGroup74], (instregex "FCOM(P?)(32|64)m")>; 1070 1071def BWWriteResGroup77 : SchedWriteRes<[BWPort23,BWPort015]> { 1072 let Latency = 7; 1073 let NumMicroOps = 2; 1074 let ResourceCycles = [1,1]; 1075} 1076def: InstRW<[BWWriteResGroup77], (instrs VPBLENDDYrmi)>; 1077 1078def BWWriteResGroup79 : SchedWriteRes<[BWPort5,BWPort23]> { 1079 let Latency = 7; 1080 let NumMicroOps = 3; 1081 let ResourceCycles = [2,1]; 1082} 1083def: InstRW<[BWWriteResGroup79], (instrs MMX_PACKSSDWirm, 1084 MMX_PACKSSWBirm, 1085 MMX_PACKUSWBirm)>; 1086 1087def BWWriteResGroup80 : SchedWriteRes<[BWPort23,BWPort0156]> { 1088 let Latency = 7; 1089 let NumMicroOps = 3; 1090 let ResourceCycles = [1,2]; 1091} 1092def: InstRW<[BWWriteResGroup80], (instrs LEAVE, LEAVE64, 1093 SCASB, SCASL, SCASQ, SCASW)>; 1094 1095def BWWriteResGroup82 : SchedWriteRes<[BWPort0,BWPort01,BWPort23]> { 1096 let Latency = 7; 1097 let NumMicroOps = 3; 1098 let ResourceCycles = [1,1,1]; 1099} 1100def: InstRW<[BWWriteResGroup82], (instrs FLDCW16m)>; 1101 1102def BWWriteResGroup84 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> { 1103 let Latency = 7; 1104 let NumMicroOps = 3; 1105 let ResourceCycles = [1,1,1]; 1106} 1107def: InstRW<[BWWriteResGroup84], (instrs LRETQ, RETQ)>; 1108 1109def BWWriteResGroup87 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> { 1110 let Latency = 7; 1111 let NumMicroOps = 5; 1112 let ResourceCycles = [1,1,1,2]; 1113} 1114def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m(1|i)", 1115 "ROR(8|16|32|64)m(1|i)")>; 1116 1117def BWWriteResGroup87_1 : SchedWriteRes<[BWPort06]> { 1118 let Latency = 2; 1119 let NumMicroOps = 2; 1120 let ResourceCycles = [2]; 1121} 1122def: InstRW<[BWWriteResGroup87_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1, 1123 ROR8r1, ROR16r1, ROR32r1, ROR64r1)>; 1124 1125def BWWriteResGroup88 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> { 1126 let Latency = 7; 1127 let NumMicroOps = 5; 1128 let ResourceCycles = [1,1,1,2]; 1129} 1130def: InstRW<[BWWriteResGroup88], (instregex "XADD(8|16|32|64)rm")>; 1131 1132def BWWriteResGroup89 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> { 1133 let Latency = 7; 1134 let NumMicroOps = 5; 1135 let ResourceCycles = [1,1,1,1,1]; 1136} 1137def: InstRW<[BWWriteResGroup89], (instregex "CALL(16|32|64)m")>; 1138def: InstRW<[BWWriteResGroup89], (instrs FARCALL64m)>; 1139 1140def BWWriteResGroup90 : SchedWriteRes<[BWPort6,BWPort06,BWPort15,BWPort0156]> { 1141 let Latency = 7; 1142 let NumMicroOps = 7; 1143 let ResourceCycles = [2,2,1,2]; 1144} 1145def: InstRW<[BWWriteResGroup90], (instrs LOOP)>; 1146 1147def BWWriteResGroup91 : SchedWriteRes<[BWPort1,BWPort23]> { 1148 let Latency = 8; 1149 let NumMicroOps = 2; 1150 let ResourceCycles = [1,1]; 1151} 1152def: InstRW<[BWWriteResGroup91], (instrs MMX_CVTPI2PSirm, 1153 CVTDQ2PSrm, 1154 VCVTDQ2PSrm)>; 1155def: InstRW<[BWWriteResGroup91], (instregex "P(DEP|EXT)(32|64)rm")>; 1156 1157def BWWriteResGroup92 : SchedWriteRes<[BWPort5,BWPort23]> { 1158 let Latency = 8; 1159 let NumMicroOps = 2; 1160 let ResourceCycles = [1,1]; 1161} 1162def: InstRW<[BWWriteResGroup92], (instrs VPMOVSXBDYrm, 1163 VPMOVSXBQYrm, 1164 VPMOVSXBWYrm, 1165 VPMOVSXDQYrm, 1166 VPMOVSXWDYrm, 1167 VPMOVSXWQYrm, 1168 VPMOVZXWDYrm)>; 1169 1170def BWWriteResGroup97 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> { 1171 let Latency = 8; 1172 let NumMicroOps = 5; 1173 let ResourceCycles = [1,1,1,2]; 1174} 1175def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)m(1|i)", 1176 "RCR(8|16|32|64)m(1|i)")>; 1177 1178def BWWriteResGroup99 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> { 1179 let Latency = 8; 1180 let NumMicroOps = 6; 1181 let ResourceCycles = [1,1,1,3]; 1182} 1183def: InstRW<[BWWriteResGroup99], (instregex "XCHG(8|16|32|64)rm")>; 1184 1185def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort0156]> { 1186 let Latency = 8; 1187 let NumMicroOps = 6; 1188 let ResourceCycles = [1,1,1,2,1]; 1189} 1190def : SchedAlias<WriteADCRMW, BWWriteResGroup100>; 1191def: InstRW<[BWWriteResGroup100], (instregex "ROL(8|16|32|64)mCL", 1192 "ROR(8|16|32|64)mCL", 1193 "SAR(8|16|32|64)mCL", 1194 "SHL(8|16|32|64)mCL", 1195 "SHR(8|16|32|64)mCL")>; 1196 1197def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> { 1198 let Latency = 9; 1199 let NumMicroOps = 2; 1200 let ResourceCycles = [1,1]; 1201} 1202def: InstRW<[BWWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m", 1203 "ILD_F(16|32|64)m")>; 1204def: InstRW<[BWWriteResGroup101], (instrs VCVTPS2DQYrm, 1205 VCVTTPS2DQYrm)>; 1206 1207def BWWriteResGroup105 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> { 1208 let Latency = 9; 1209 let NumMicroOps = 3; 1210 let ResourceCycles = [1,1,1]; 1211} 1212def: InstRW<[BWWriteResGroup105], (instregex "(V?)CVTSS2SI(64)?rm", 1213 "(V?)CVT(T?)SD2SI64rm", 1214 "(V?)CVT(T?)SD2SIrm", 1215 "VCVTTSS2SI64rm", 1216 "(V?)CVTTSS2SIrm")>; 1217 1218def BWWriteResGroup106 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> { 1219 let Latency = 9; 1220 let NumMicroOps = 3; 1221 let ResourceCycles = [1,1,1]; 1222} 1223def: InstRW<[BWWriteResGroup106], (instrs VCVTPS2PDYrm)>; 1224 1225def BWWriteResGroup107 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> { 1226 let Latency = 9; 1227 let NumMicroOps = 3; 1228 let ResourceCycles = [1,1,1]; 1229} 1230def: InstRW<[BWWriteResGroup107], (instrs CVTPD2PSrm, 1231 CVTPD2DQrm, 1232 CVTTPD2DQrm, 1233 MMX_CVTPI2PDirm)>; 1234def: InstRW<[BWWriteResGroup107], (instregex "MMX_CVT(T?)PD2PIirm", 1235 "(V?)CVTDQ2PDrm", 1236 "(V?)CVTSD2SSrm")>; 1237 1238def BWWriteResGroup108 : SchedWriteRes<[BWPort5,BWPort23,BWPort015]> { 1239 let Latency = 9; 1240 let NumMicroOps = 3; 1241 let ResourceCycles = [1,1,1]; 1242} 1243def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTB(Y?)rm", 1244 "VPBROADCASTW(Y?)rm")>; 1245 1246def BWWriteResGroup112 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> { 1247 let Latency = 9; 1248 let NumMicroOps = 5; 1249 let ResourceCycles = [1,1,3]; 1250} 1251def: InstRW<[BWWriteResGroup112], (instrs RDRAND16r, RDRAND32r, RDRAND64r)>; 1252 1253def BWWriteResGroup113 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> { 1254 let Latency = 9; 1255 let NumMicroOps = 5; 1256 let ResourceCycles = [1,2,1,1]; 1257} 1258def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm", 1259 "LSL(16|32|64)rm")>; 1260 1261def BWWriteResGroup115 : SchedWriteRes<[BWPort0,BWPort23]> { 1262 let Latency = 10; 1263 let NumMicroOps = 2; 1264 let ResourceCycles = [1,1]; 1265} 1266def: InstRW<[BWWriteResGroup115], (instregex "(V?)PCMPGTQrm")>; 1267 1268def BWWriteResGroup117 : SchedWriteRes<[BWPort1,BWPort23]> { 1269 let Latency = 10; 1270 let NumMicroOps = 3; 1271 let ResourceCycles = [2,1]; 1272} 1273def: InstRW<[BWWriteResGroup117], (instregex "FICOM(P?)(16|32)m")>; 1274 1275def BWWriteResGroup120 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> { 1276 let Latency = 10; 1277 let NumMicroOps = 4; 1278 let ResourceCycles = [1,1,1,1]; 1279} 1280def: InstRW<[BWWriteResGroup120], (instregex "CVTTSS2SI64rm")>; 1281 1282def BWWriteResGroup122_1 : SchedWriteRes<[BWPort0,BWFPDivider]> { 1283 let Latency = 11; 1284 let NumMicroOps = 1; 1285 let ResourceCycles = [1,3]; // Really 2.5 cycle throughput 1286} 1287def : SchedAlias<WriteFDiv, BWWriteResGroup122_1>; // TODO - convert to ZnWriteResFpuPair 1288 1289def BWWriteResGroup123 : SchedWriteRes<[BWPort0,BWPort23]> { 1290 let Latency = 11; 1291 let NumMicroOps = 2; 1292 let ResourceCycles = [1,1]; 1293} 1294def: InstRW<[BWWriteResGroup123], (instregex "MUL_F(32|64)m")>; 1295def: InstRW<[BWWriteResGroup123], (instrs VPCMPGTQYrm)>; 1296 1297def BWWriteResGroup128 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> { 1298 let Latency = 11; 1299 let NumMicroOps = 3; 1300 let ResourceCycles = [1,1,1]; 1301} 1302def: InstRW<[BWWriteResGroup128], (instrs VCVTDQ2PDYrm)>; 1303 1304def BWWriteResGroup131 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> { 1305 let Latency = 11; 1306 let NumMicroOps = 7; 1307 let ResourceCycles = [2,2,3]; 1308} 1309def: InstRW<[BWWriteResGroup131], (instregex "RCL(16|32|64)rCL", 1310 "RCR(16|32|64)rCL")>; 1311 1312def BWWriteResGroup132 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> { 1313 let Latency = 11; 1314 let NumMicroOps = 9; 1315 let ResourceCycles = [1,4,1,3]; 1316} 1317def: InstRW<[BWWriteResGroup132], (instrs RCL8rCL)>; 1318 1319def BWWriteResGroup133 : SchedWriteRes<[BWPort06,BWPort0156]> { 1320 let Latency = 11; 1321 let NumMicroOps = 11; 1322 let ResourceCycles = [2,9]; 1323} 1324def: InstRW<[BWWriteResGroup133], (instrs LOOPE)>; 1325def: InstRW<[BWWriteResGroup133], (instrs LOOPNE)>; 1326 1327def BWWriteResGroup135 : SchedWriteRes<[BWPort1,BWPort23]> { 1328 let Latency = 12; 1329 let NumMicroOps = 3; 1330 let ResourceCycles = [2,1]; 1331} 1332def: InstRW<[BWWriteResGroup135], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>; 1333 1334def BWWriteResGroup139_1 : SchedWriteRes<[BWPort0,BWFPDivider]> { 1335 let Latency = 14; 1336 let NumMicroOps = 1; 1337 let ResourceCycles = [1,4]; 1338} 1339def : SchedAlias<WriteFDiv64, BWWriteResGroup139_1>; // TODO - convert to ZnWriteResFpuPair 1340 1341def BWWriteResGroup141 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> { 1342 let Latency = 14; 1343 let NumMicroOps = 3; 1344 let ResourceCycles = [1,1,1]; 1345} 1346def: InstRW<[BWWriteResGroup141], (instregex "MUL_FI(16|32)m")>; 1347 1348def BWWriteResGroup144 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> { 1349 let Latency = 14; 1350 let NumMicroOps = 8; 1351 let ResourceCycles = [2,2,1,3]; 1352} 1353def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>; 1354 1355def BWWriteResGroup145 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> { 1356 let Latency = 14; 1357 let NumMicroOps = 10; 1358 let ResourceCycles = [2,3,1,4]; 1359} 1360def: InstRW<[BWWriteResGroup145], (instrs RCR8rCL)>; 1361 1362def BWWriteResGroup146 : SchedWriteRes<[BWPort0,BWPort1,BWPort6,BWPort0156]> { 1363 let Latency = 14; 1364 let NumMicroOps = 12; 1365 let ResourceCycles = [2,1,4,5]; 1366} 1367def: InstRW<[BWWriteResGroup146], (instrs XCH_F)>; 1368 1369def BWWriteResGroup147 : SchedWriteRes<[BWPort0]> { 1370 let Latency = 15; 1371 let NumMicroOps = 1; 1372 let ResourceCycles = [1]; 1373} 1374def: InstRW<[BWWriteResGroup147], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>; 1375 1376def BWWriteResGroup149 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> { 1377 let Latency = 15; 1378 let NumMicroOps = 10; 1379 let ResourceCycles = [1,1,1,4,1,2]; 1380} 1381def: InstRW<[BWWriteResGroup149], (instregex "RCL(8|16|32|64)mCL")>; 1382 1383def BWWriteResGroup150 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> { 1384 let Latency = 16; 1385 let NumMicroOps = 2; 1386 let ResourceCycles = [1,1,5]; 1387} 1388def : SchedAlias<WriteFDivLd, BWWriteResGroup150>; // TODO - convert to ZnWriteResFpuPair 1389 1390def BWWriteResGroup153 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> { 1391 let Latency = 16; 1392 let NumMicroOps = 14; 1393 let ResourceCycles = [1,1,1,4,2,5]; 1394} 1395def: InstRW<[BWWriteResGroup153], (instrs CMPXCHG8B)>; 1396 1397def BWWriteResGroup154 : SchedWriteRes<[BWPort5,BWPort6]> { 1398 let Latency = 8; 1399 let NumMicroOps = 20; 1400 let ResourceCycles = [1,1]; 1401} 1402def: InstRW<[BWWriteResGroup154], (instrs VZEROALL)>; 1403 1404def BWWriteResGroup159 : SchedWriteRes<[BWPort5,BWPort6,BWPort06,BWPort0156]> { 1405 let Latency = 18; 1406 let NumMicroOps = 8; 1407 let ResourceCycles = [1,1,1,5]; 1408} 1409def: InstRW<[BWWriteResGroup159], (instrs CPUID)>; 1410def: InstRW<[BWWriteResGroup159], (instrs RDTSC)>; 1411 1412def BWWriteResGroup160 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> { 1413 let Latency = 18; 1414 let NumMicroOps = 11; 1415 let ResourceCycles = [2,1,1,3,1,3]; 1416} 1417def: InstRW<[BWWriteResGroup160], (instregex "RCR(8|16|32|64)mCL")>; 1418 1419def BWWriteResGroup161 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> { 1420 let Latency = 19; 1421 let NumMicroOps = 2; 1422 let ResourceCycles = [1,1,8]; 1423} 1424def : SchedAlias<WriteFDiv64Ld, BWWriteResGroup161>; // TODO - convert to ZnWriteResFpuPair 1425 1426def BWWriteResGroup165 : SchedWriteRes<[BWPort0]> { 1427 let Latency = 20; 1428 let NumMicroOps = 1; 1429 let ResourceCycles = [1]; 1430} 1431def: InstRW<[BWWriteResGroup165], (instregex "DIV_(FPrST0|FST0r|FrST0)")>; 1432 1433def BWWriteResGroup167 : SchedWriteRes<[BWPort4,BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> { 1434 let Latency = 20; 1435 let NumMicroOps = 8; 1436 let ResourceCycles = [1,1,1,1,1,1,2]; 1437} 1438def: InstRW<[BWWriteResGroup167], (instrs INSB, INSL, INSW)>; 1439 1440def BWWriteResGroup169 : SchedWriteRes<[BWPort0,BWPort23]> { 1441 let Latency = 21; 1442 let NumMicroOps = 2; 1443 let ResourceCycles = [1,1]; 1444} 1445def: InstRW<[BWWriteResGroup169], (instregex "DIV_F(32|64)m")>; 1446 1447def BWWriteResGroup171 : SchedWriteRes<[BWPort0,BWPort4,BWPort5,BWPort23,BWPort237,BWPort06,BWPort0156]> { 1448 let Latency = 21; 1449 let NumMicroOps = 19; 1450 let ResourceCycles = [2,1,4,1,1,4,6]; 1451} 1452def: InstRW<[BWWriteResGroup171], (instrs CMPXCHG16B)>; 1453 1454def BWWriteResGroup172 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> { 1455 let Latency = 22; 1456 let NumMicroOps = 18; 1457 let ResourceCycles = [1,1,16]; 1458} 1459def: InstRW<[BWWriteResGroup172], (instrs POPF64)>; 1460 1461def BWWriteResGroup176 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> { 1462 let Latency = 23; 1463 let NumMicroOps = 19; 1464 let ResourceCycles = [3,1,15]; 1465} 1466def: InstRW<[BWWriteResGroup176], (instregex "XRSTOR(64)?")>; 1467 1468def BWWriteResGroup177 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> { 1469 let Latency = 24; 1470 let NumMicroOps = 3; 1471 let ResourceCycles = [1,1,1]; 1472} 1473def: InstRW<[BWWriteResGroup177], (instregex "DIV_FI(16|32)m")>; 1474 1475def BWWriteResGroup180 : SchedWriteRes<[BWPort0,BWPort23]> { 1476 let Latency = 26; 1477 let NumMicroOps = 2; 1478 let ResourceCycles = [1,1]; 1479} 1480def: InstRW<[BWWriteResGroup180], (instregex "DIVR_F(32|64)m")>; 1481 1482def BWWriteResGroup182 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> { 1483 let Latency = 29; 1484 let NumMicroOps = 3; 1485 let ResourceCycles = [1,1,1]; 1486} 1487def: InstRW<[BWWriteResGroup182], (instregex "DIVR_FI(16|32)m")>; 1488 1489def BWWriteResGroup183_1 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { 1490 let Latency = 17; 1491 let NumMicroOps = 7; 1492 let ResourceCycles = [1,3,2,1]; 1493} 1494def: InstRW<[BWWriteResGroup183_1], (instrs VGATHERDPDrm, VPGATHERDQrm, 1495 VGATHERQPDrm, VPGATHERQQrm)>; 1496 1497def BWWriteResGroup183_2 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { 1498 let Latency = 18; 1499 let NumMicroOps = 9; 1500 let ResourceCycles = [1,3,4,1]; 1501} 1502def: InstRW<[BWWriteResGroup183_2], (instrs VGATHERDPDYrm, VPGATHERDQYrm, 1503 VGATHERQPDYrm, VPGATHERQQYrm)>; 1504 1505def BWWriteResGroup183_3 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { 1506 let Latency = 19; 1507 let NumMicroOps = 9; 1508 let ResourceCycles = [1,5,2,1]; 1509} 1510def: InstRW<[BWWriteResGroup183_3], (instrs VGATHERQPSrm, VPGATHERQDrm)>; 1511 1512def BWWriteResGroup183_4 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { 1513 let Latency = 19; 1514 let NumMicroOps = 10; 1515 let ResourceCycles = [1,4,4,1]; 1516} 1517def: InstRW<[BWWriteResGroup183_4], (instrs VGATHERDPSrm, VPGATHERDDrm, 1518 VGATHERQPSYrm, VPGATHERQDYrm)>; 1519 1520def BWWriteResGroup183_5 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { 1521 let Latency = 21; 1522 let NumMicroOps = 14; 1523 let ResourceCycles = [1,4,8,1]; 1524} 1525def: InstRW<[BWWriteResGroup183_5], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>; 1526 1527def BWWriteResGroup185 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> { 1528 let Latency = 29; 1529 let NumMicroOps = 27; 1530 let ResourceCycles = [1,5,1,1,19]; 1531} 1532def: InstRW<[BWWriteResGroup185], (instrs XSAVE64)>; 1533 1534def BWWriteResGroup186 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> { 1535 let Latency = 30; 1536 let NumMicroOps = 28; 1537 let ResourceCycles = [1,6,1,1,19]; 1538} 1539def: InstRW<[BWWriteResGroup186], (instrs XSAVE)>; 1540def: InstRW<[BWWriteResGroup186], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>; 1541 1542def BWWriteResGroup191 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort06,BWPort0156]> { 1543 let Latency = 34; 1544 let NumMicroOps = 23; 1545 let ResourceCycles = [1,5,3,4,10]; 1546} 1547def: InstRW<[BWWriteResGroup191], (instregex "IN(8|16|32)ri", 1548 "IN(8|16|32)rr")>; 1549 1550def BWWriteResGroup194 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> { 1551 let Latency = 35; 1552 let NumMicroOps = 23; 1553 let ResourceCycles = [1,5,2,1,4,10]; 1554} 1555def: InstRW<[BWWriteResGroup194], (instregex "OUT(8|16|32)ir", 1556 "OUT(8|16|32)rr")>; 1557 1558def BWWriteResGroup196 : SchedWriteRes<[BWPort5,BWPort0156]> { 1559 let Latency = 42; 1560 let NumMicroOps = 22; 1561 let ResourceCycles = [2,20]; 1562} 1563def: InstRW<[BWWriteResGroup196], (instrs RDTSCP)>; 1564 1565def BWWriteResGroup197 : SchedWriteRes<[BWPort0,BWPort01,BWPort23,BWPort05,BWPort06,BWPort015,BWPort0156]> { 1566 let Latency = 60; 1567 let NumMicroOps = 64; 1568 let ResourceCycles = [2,2,8,1,10,2,39]; 1569} 1570def: InstRW<[BWWriteResGroup197], (instrs FLDENVm)>; 1571 1572def BWWriteResGroup198 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> { 1573 let Latency = 63; 1574 let NumMicroOps = 88; 1575 let ResourceCycles = [4,4,31,1,2,1,45]; 1576} 1577def: InstRW<[BWWriteResGroup198], (instrs FXRSTOR64)>; 1578 1579def BWWriteResGroup199 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> { 1580 let Latency = 63; 1581 let NumMicroOps = 90; 1582 let ResourceCycles = [4,2,33,1,2,1,47]; 1583} 1584def: InstRW<[BWWriteResGroup199], (instrs FXRSTOR)>; 1585 1586def BWWriteResGroup200 : SchedWriteRes<[BWPort5,BWPort01,BWPort0156]> { 1587 let Latency = 75; 1588 let NumMicroOps = 15; 1589 let ResourceCycles = [6,3,6]; 1590} 1591def: InstRW<[BWWriteResGroup200], (instrs FNINIT)>; 1592 1593def BWWriteResGroup202 : SchedWriteRes<[BWPort0,BWPort1,BWPort4,BWPort5,BWPort6,BWPort237,BWPort06,BWPort0156]> { 1594 let Latency = 115; 1595 let NumMicroOps = 100; 1596 let ResourceCycles = [9,9,11,8,1,11,21,30]; 1597} 1598def: InstRW<[BWWriteResGroup202], (instrs FSTENVm)>; 1599 1600def: InstRW<[WriteZero], (instrs CLC)>; 1601 1602 1603// Instruction variants handled by the renamer. These might not need execution 1604// ports in certain conditions. 1605// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs", 1606// section "Haswell and Broadwell Pipeline" > "Register allocation and 1607// renaming". 1608// These can be investigated with llvm-exegesis, e.g. 1609// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1610// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1611 1612def BWWriteZeroLatency : SchedWriteRes<[]> { 1613 let Latency = 0; 1614} 1615 1616def BWWriteZeroIdiom : SchedWriteVariant<[ 1617 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1618 SchedVar<NoSchedPred, [WriteALU]> 1619]>; 1620def : InstRW<[BWWriteZeroIdiom], (instrs SUB32rr, SUB64rr, 1621 XOR32rr, XOR64rr)>; 1622 1623def BWWriteFZeroIdiom : SchedWriteVariant<[ 1624 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1625 SchedVar<NoSchedPred, [WriteFLogic]> 1626]>; 1627def : InstRW<[BWWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr, 1628 VXORPDrr)>; 1629 1630def BWWriteFZeroIdiomY : SchedWriteVariant<[ 1631 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1632 SchedVar<NoSchedPred, [WriteFLogicY]> 1633]>; 1634def : InstRW<[BWWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>; 1635 1636def BWWriteVZeroIdiomLogicX : SchedWriteVariant<[ 1637 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1638 SchedVar<NoSchedPred, [WriteVecLogicX]> 1639]>; 1640def : InstRW<[BWWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>; 1641 1642def BWWriteVZeroIdiomLogicY : SchedWriteVariant<[ 1643 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1644 SchedVar<NoSchedPred, [WriteVecLogicY]> 1645]>; 1646def : InstRW<[BWWriteVZeroIdiomLogicY], (instrs VPXORYrr)>; 1647 1648def BWWriteVZeroIdiomALUX : SchedWriteVariant<[ 1649 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1650 SchedVar<NoSchedPred, [WriteVecALUX]> 1651]>; 1652def : InstRW<[BWWriteVZeroIdiomALUX], (instrs PSUBBrr, VPSUBBrr, 1653 PSUBDrr, VPSUBDrr, 1654 PSUBQrr, VPSUBQrr, 1655 PSUBWrr, VPSUBWrr, 1656 PCMPGTBrr, VPCMPGTBrr, 1657 PCMPGTDrr, VPCMPGTDrr, 1658 PCMPGTWrr, VPCMPGTWrr)>; 1659 1660def BWWriteVZeroIdiomALUY : SchedWriteVariant<[ 1661 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1662 SchedVar<NoSchedPred, [WriteVecALUY]> 1663]>; 1664def : InstRW<[BWWriteVZeroIdiomALUY], (instrs VPSUBBYrr, 1665 VPSUBDYrr, 1666 VPSUBQYrr, 1667 VPSUBWYrr, 1668 VPCMPGTBYrr, 1669 VPCMPGTDYrr, 1670 VPCMPGTWYrr)>; 1671 1672def BWWritePCMPGTQ : SchedWriteRes<[BWPort0]> { 1673 let Latency = 5; 1674 let NumMicroOps = 1; 1675 let ResourceCycles = [1]; 1676} 1677 1678def BWWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[ 1679 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1680 SchedVar<NoSchedPred, [BWWritePCMPGTQ]> 1681]>; 1682def : InstRW<[BWWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr, 1683 VPCMPGTQYrr)>; 1684 1685 1686// CMOVs that use both Z and C flag require an extra uop. 1687def BWWriteCMOVA_CMOVBErr : SchedWriteRes<[BWPort06,BWPort0156]> { 1688 let Latency = 2; 1689 let ResourceCycles = [1,1]; 1690 let NumMicroOps = 2; 1691} 1692 1693def BWWriteCMOVA_CMOVBErm : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> { 1694 let Latency = 7; 1695 let ResourceCycles = [1,1,1]; 1696 let NumMicroOps = 3; 1697} 1698 1699def BWCMOVA_CMOVBErr : SchedWriteVariant<[ 1700 SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [BWWriteCMOVA_CMOVBErr]>, 1701 SchedVar<NoSchedPred, [WriteCMOV]> 1702]>; 1703 1704def BWCMOVA_CMOVBErm : SchedWriteVariant<[ 1705 SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [BWWriteCMOVA_CMOVBErm]>, 1706 SchedVar<NoSchedPred, [WriteCMOV.Folded]> 1707]>; 1708 1709def : InstRW<[BWCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>; 1710def : InstRW<[BWCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>; 1711 1712// SETCCs that use both Z and C flag require an extra uop. 1713def BWWriteSETA_SETBEr : SchedWriteRes<[BWPort06,BWPort0156]> { 1714 let Latency = 2; 1715 let ResourceCycles = [1,1]; 1716 let NumMicroOps = 2; 1717} 1718 1719def BWWriteSETA_SETBEm : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> { 1720 let Latency = 3; 1721 let ResourceCycles = [1,1,1,1]; 1722 let NumMicroOps = 4; 1723} 1724 1725def BWSETA_SETBErr : SchedWriteVariant<[ 1726 SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [BWWriteSETA_SETBEr]>, 1727 SchedVar<NoSchedPred, [WriteSETCC]> 1728]>; 1729 1730def BWSETA_SETBErm : SchedWriteVariant<[ 1731 SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [BWWriteSETA_SETBEm]>, 1732 SchedVar<NoSchedPred, [WriteSETCCStore]> 1733]>; 1734 1735def : InstRW<[BWSETA_SETBErr], (instrs SETCCr)>; 1736def : InstRW<[BWSETA_SETBErm], (instrs SETCCm)>; 1737 1738} // SchedModel 1739