1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -global-isel -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
3
4define amdgpu_cs i32 @test_shl_1(i32 inreg %arg1) {
5; CHECK-LABEL: test_shl_1:
6; CHECK:       ; %bb.0: ; %.entry
7; CHECK-NEXT:    s_lshl_b32 s0, s0, 5
8; CHECK-NEXT:    ; return to shader part epilog
9.entry:
10  %z1 = shl i32 %arg1, 2
11  %z2 = shl i32 %z1, 3
12  ret i32 %z2
13}
14
15define amdgpu_cs i32 @test_shl_2(i32 inreg %arg1) {
16; CHECK-LABEL: test_shl_2:
17; CHECK:       ; %bb.0: ; %.entry
18; CHECK-NEXT:    s_lshl_b32 s0, s0, 10
19; CHECK-NEXT:    ; return to shader part epilog
20.entry:
21  %z1 = shl i32 %arg1, 1
22  %z2 = shl i32 %z1, 2
23  %z3 = shl i32 %z2, 3
24  %z4 = shl i32 %z3, 4
25  ret i32 %z4
26}
27
28define amdgpu_cs i32 @test_shl_i32(i32 inreg %arg1) {
29; CHECK-LABEL: test_shl_i32:
30; CHECK:       ; %bb.0: ; %.entry
31; CHECK-NEXT:    s_mov_b32 s0, 0
32; CHECK-NEXT:    ; return to shader part epilog
33.entry:
34  %z1 = shl i32 %arg1, 10
35  %z2 = shl i32 %z1, 10
36  %z3 = shl i32 %z2, 10
37  %z4 = shl i32 %z3, 10
38  ret i32 %z4
39}
40
41define amdgpu_cs i64 @test_shl_i64(i64 inreg %arg1) {
42; CHECK-LABEL: test_shl_i64:
43; CHECK:       ; %bb.0: ; %.entry
44; CHECK-NEXT:    s_mov_b32 s0, 0
45; CHECK-NEXT:    s_mov_b32 s1, 0
46; CHECK-NEXT:    ; return to shader part epilog
47.entry:
48  %z1 = shl i64 %arg1, 10
49  %z2 = shl i64 %z1, 10
50  %z3 = shl i64 %z2, 10
51  %z4 = shl i64 %z3, 10
52  %z5 = shl i64 %z4, 10
53  %z6 = shl i64 %z5, 10
54  %z7 = shl i64 %z6, 10
55  ret i64 %z7
56}
57
58define amdgpu_cs i32 @test_ashr_1(i32 inreg %arg1) {
59; CHECK-LABEL: test_ashr_1:
60; CHECK:       ; %bb.0: ; %.entry
61; CHECK-NEXT:    s_ashr_i32 s0, s0, 5
62; CHECK-NEXT:    ; return to shader part epilog
63.entry:
64  %z1 = ashr i32 %arg1, 2
65  %z2 = ashr i32 %z1, 3
66  ret i32 %z2
67}
68
69define amdgpu_cs i32 @test_ashr_2(i32 inreg %arg1) {
70; CHECK-LABEL: test_ashr_2:
71; CHECK:       ; %bb.0: ; %.entry
72; CHECK-NEXT:    s_ashr_i32 s0, s0, 10
73; CHECK-NEXT:    ; return to shader part epilog
74.entry:
75  %z1 = ashr i32 %arg1, 1
76  %z2 = ashr i32 %z1, 2
77  %z3 = ashr i32 %z2, 3
78  %z4 = ashr i32 %z3, 4
79  ret i32 %z4
80}
81
82define amdgpu_cs i32 @test_ashr_i32(i32 inreg %arg1) {
83; CHECK-LABEL: test_ashr_i32:
84; CHECK:       ; %bb.0: ; %.entry
85; CHECK-NEXT:    s_ashr_i32 s0, s0, 31
86; CHECK-NEXT:    ; return to shader part epilog
87.entry:
88  %z1 = ashr i32 %arg1, 10
89  %z2 = ashr i32 %z1, 10
90  %z3 = ashr i32 %z2, 10
91  %z4 = ashr i32 %z3, 10
92  ret i32 %z4
93}
94
95define amdgpu_cs i64 @test_ashr_i64(i64 inreg %arg1) {
96; CHECK-LABEL: test_ashr_i64:
97; CHECK:       ; %bb.0: ; %.entry
98; CHECK-NEXT:    s_ashr_i32 s0, s1, 31
99; CHECK-NEXT:    s_mov_b32 s1, s0
100; CHECK-NEXT:    ; return to shader part epilog
101.entry:
102  %z1 = ashr i64 %arg1, 10
103  %z2 = ashr i64 %z1, 10
104  %z3 = ashr i64 %z2, 10
105  %z4 = ashr i64 %z3, 10
106  %z5 = ashr i64 %z4, 10
107  %z6 = ashr i64 %z5, 10
108  %z7 = ashr i64 %z6, 10
109  ret i64 %z7
110}
111
112define amdgpu_cs i32 @test_lshr_1(i32 inreg %arg1) {
113; CHECK-LABEL: test_lshr_1:
114; CHECK:       ; %bb.0: ; %.entry
115; CHECK-NEXT:    s_lshr_b32 s0, s0, 5
116; CHECK-NEXT:    ; return to shader part epilog
117.entry:
118  %z1 = lshr i32 %arg1, 2
119  %z2 = lshr i32 %z1, 3
120  ret i32 %z2
121}
122
123define amdgpu_cs i32 @test_lshr_2(i32 inreg %arg1) {
124; CHECK-LABEL: test_lshr_2:
125; CHECK:       ; %bb.0: ; %.entry
126; CHECK-NEXT:    s_lshr_b32 s0, s0, 10
127; CHECK-NEXT:    ; return to shader part epilog
128.entry:
129  %z1 = lshr i32 %arg1, 1
130  %z2 = lshr i32 %z1, 2
131  %z3 = lshr i32 %z2, 3
132  %z4 = lshr i32 %z3, 4
133  ret i32 %z4
134}
135
136define amdgpu_cs i32 @test_lshr_i32(i32 inreg %arg1) {
137; CHECK-LABEL: test_lshr_i32:
138; CHECK:       ; %bb.0: ; %.entry
139; CHECK-NEXT:    s_mov_b32 s0, 0
140; CHECK-NEXT:    ; return to shader part epilog
141.entry:
142  %z1 = lshr i32 %arg1, 10
143  %z2 = lshr i32 %z1, 10
144  %z3 = lshr i32 %z2, 10
145  %z4 = lshr i32 %z3, 10
146  ret i32 %z4
147}
148
149define amdgpu_cs i64 @test_lshr_i64(i64 inreg %arg1) {
150; CHECK-LABEL: test_lshr_i64:
151; CHECK:       ; %bb.0: ; %.entry
152; CHECK-NEXT:    s_mov_b32 s0, 0
153; CHECK-NEXT:    s_mov_b32 s1, 0
154; CHECK-NEXT:    ; return to shader part epilog
155.entry:
156  %z1 = lshr i64 %arg1, 10
157  %z2 = lshr i64 %z1, 10
158  %z3 = lshr i64 %z2, 10
159  %z4 = lshr i64 %z3, 10
160  %z5 = lshr i64 %z4, 10
161  %z6 = lshr i64 %z5, 10
162  %z7 = lshr i64 %z6, 10
163  ret i64 %z7
164}
165