1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 3; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 4; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV32 5; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV64 6 7define void @splat_ones_v1i1(<1 x i1>* %x) { 8; CHECK-LABEL: splat_ones_v1i1: 9; CHECK: # %bb.0: 10; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu 11; CHECK-NEXT: vmset.m v0 12; CHECK-NEXT: vmv.v.i v25, 0 13; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 14; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu 15; CHECK-NEXT: vmv.v.i v26, 0 16; CHECK-NEXT: vsetivli zero, 1, e8, mf2, tu, mu 17; CHECK-NEXT: vslideup.vi v26, v25, 0 18; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu 19; CHECK-NEXT: vmsne.vi v25, v26, 0 20; CHECK-NEXT: vse1.v v25, (a0) 21; CHECK-NEXT: ret 22 store <1 x i1> <i1 1>, <1 x i1>* %x 23 ret void 24} 25 26define void @splat_zeros_v2i1(<2 x i1>* %x) { 27; CHECK-LABEL: splat_zeros_v2i1: 28; CHECK: # %bb.0: 29; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu 30; CHECK-NEXT: vmclr.m v0 31; CHECK-NEXT: vmv.v.i v25, 0 32; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 33; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu 34; CHECK-NEXT: vmv.v.i v26, 0 35; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu 36; CHECK-NEXT: vslideup.vi v26, v25, 0 37; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu 38; CHECK-NEXT: vmsne.vi v25, v26, 0 39; CHECK-NEXT: vse1.v v25, (a0) 40; CHECK-NEXT: ret 41 store <2 x i1> zeroinitializer, <2 x i1>* %x 42 ret void 43} 44 45define void @splat_v1i1(<1 x i1>* %x, i1 %y) { 46; CHECK-LABEL: splat_v1i1: 47; CHECK: # %bb.0: 48; CHECK-NEXT: andi a1, a1, 1 49; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu 50; CHECK-NEXT: vmv.v.x v25, a1 51; CHECK-NEXT: vmsne.vi v0, v25, 0 52; CHECK-NEXT: vmv.v.i v25, 0 53; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 54; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu 55; CHECK-NEXT: vmv.v.i v26, 0 56; CHECK-NEXT: vsetivli zero, 1, e8, mf2, tu, mu 57; CHECK-NEXT: vslideup.vi v26, v25, 0 58; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu 59; CHECK-NEXT: vmsne.vi v25, v26, 0 60; CHECK-NEXT: vse1.v v25, (a0) 61; CHECK-NEXT: ret 62 %a = insertelement <1 x i1> undef, i1 %y, i32 0 63 %b = shufflevector <1 x i1> %a, <1 x i1> undef, <1 x i32> zeroinitializer 64 store <1 x i1> %b, <1 x i1>* %x 65 ret void 66} 67 68define void @splat_v1i1_icmp(<1 x i1>* %x, i32 signext %y, i32 signext %z) { 69; CHECK-LABEL: splat_v1i1_icmp: 70; CHECK: # %bb.0: 71; CHECK-NEXT: xor a1, a1, a2 72; CHECK-NEXT: seqz a1, a1 73; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu 74; CHECK-NEXT: vmv.v.x v25, a1 75; CHECK-NEXT: vmsne.vi v0, v25, 0 76; CHECK-NEXT: vmv.v.i v25, 0 77; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 78; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu 79; CHECK-NEXT: vmv.v.i v26, 0 80; CHECK-NEXT: vsetivli zero, 1, e8, mf2, tu, mu 81; CHECK-NEXT: vslideup.vi v26, v25, 0 82; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu 83; CHECK-NEXT: vmsne.vi v25, v26, 0 84; CHECK-NEXT: vse1.v v25, (a0) 85; CHECK-NEXT: ret 86 %c = icmp eq i32 %y, %z 87 %a = insertelement <1 x i1> undef, i1 %c, i32 0 88 %b = shufflevector <1 x i1> %a, <1 x i1> undef, <1 x i32> zeroinitializer 89 store <1 x i1> %b, <1 x i1>* %x 90 ret void 91} 92 93define void @splat_ones_v4i1(<4 x i1>* %x) { 94; CHECK-LABEL: splat_ones_v4i1: 95; CHECK: # %bb.0: 96; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu 97; CHECK-NEXT: vmset.m v0 98; CHECK-NEXT: vmv.v.i v25, 0 99; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 100; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu 101; CHECK-NEXT: vmv.v.i v26, 0 102; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu 103; CHECK-NEXT: vslideup.vi v26, v25, 0 104; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu 105; CHECK-NEXT: vmsne.vi v25, v26, 0 106; CHECK-NEXT: vse1.v v25, (a0) 107; CHECK-NEXT: ret 108 store <4 x i1> <i1 1, i1 1, i1 1, i1 1>, <4 x i1>* %x 109 ret void 110} 111 112define void @splat_v4i1(<4 x i1>* %x, i1 %y) { 113; CHECK-LABEL: splat_v4i1: 114; CHECK: # %bb.0: 115; CHECK-NEXT: andi a1, a1, 1 116; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu 117; CHECK-NEXT: vmv.v.x v25, a1 118; CHECK-NEXT: vmsne.vi v0, v25, 0 119; CHECK-NEXT: vmv.v.i v25, 0 120; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 121; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu 122; CHECK-NEXT: vmv.v.i v26, 0 123; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu 124; CHECK-NEXT: vslideup.vi v26, v25, 0 125; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu 126; CHECK-NEXT: vmsne.vi v25, v26, 0 127; CHECK-NEXT: vse1.v v25, (a0) 128; CHECK-NEXT: ret 129 %a = insertelement <4 x i1> undef, i1 %y, i32 0 130 %b = shufflevector <4 x i1> %a, <4 x i1> undef, <4 x i32> zeroinitializer 131 store <4 x i1> %b, <4 x i1>* %x 132 ret void 133} 134 135define void @splat_zeros_v8i1(<8 x i1>* %x) { 136; CHECK-LABEL: splat_zeros_v8i1: 137; CHECK: # %bb.0: 138; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu 139; CHECK-NEXT: vmclr.m v25 140; CHECK-NEXT: vse1.v v25, (a0) 141; CHECK-NEXT: ret 142 store <8 x i1> zeroinitializer, <8 x i1>* %x 143 ret void 144} 145 146define void @splat_v8i1(<8 x i1>* %x, i1 %y) { 147; CHECK-LABEL: splat_v8i1: 148; CHECK: # %bb.0: 149; CHECK-NEXT: andi a1, a1, 1 150; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu 151; CHECK-NEXT: vmv.v.x v25, a1 152; CHECK-NEXT: vmsne.vi v25, v25, 0 153; CHECK-NEXT: vse1.v v25, (a0) 154; CHECK-NEXT: ret 155 %a = insertelement <8 x i1> undef, i1 %y, i32 0 156 %b = shufflevector <8 x i1> %a, <8 x i1> undef, <8 x i32> zeroinitializer 157 store <8 x i1> %b, <8 x i1>* %x 158 ret void 159} 160 161define void @splat_ones_v16i1(<16 x i1>* %x) { 162; CHECK-LABEL: splat_ones_v16i1: 163; CHECK: # %bb.0: 164; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu 165; CHECK-NEXT: vmset.m v25 166; CHECK-NEXT: vse1.v v25, (a0) 167; CHECK-NEXT: ret 168 store <16 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, <16 x i1>* %x 169 ret void 170} 171 172define void @splat_v16i1(<16 x i1>* %x, i1 %y) { 173; CHECK-LABEL: splat_v16i1: 174; CHECK: # %bb.0: 175; CHECK-NEXT: andi a1, a1, 1 176; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu 177; CHECK-NEXT: vmv.v.x v25, a1 178; CHECK-NEXT: vmsne.vi v25, v25, 0 179; CHECK-NEXT: vse1.v v25, (a0) 180; CHECK-NEXT: ret 181 %a = insertelement <16 x i1> undef, i1 %y, i32 0 182 %b = shufflevector <16 x i1> %a, <16 x i1> undef, <16 x i32> zeroinitializer 183 store <16 x i1> %b, <16 x i1>* %x 184 ret void 185} 186 187define void @splat_zeros_v32i1(<32 x i1>* %x) { 188; LMULMAX2-LABEL: splat_zeros_v32i1: 189; LMULMAX2: # %bb.0: 190; LMULMAX2-NEXT: addi a1, zero, 32 191; LMULMAX2-NEXT: vsetvli zero, a1, e8, m2, ta, mu 192; LMULMAX2-NEXT: vmclr.m v25 193; LMULMAX2-NEXT: vse1.v v25, (a0) 194; LMULMAX2-NEXT: ret 195; 196; LMULMAX1-RV32-LABEL: splat_zeros_v32i1: 197; LMULMAX1-RV32: # %bb.0: 198; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu 199; LMULMAX1-RV32-NEXT: vmclr.m v25 200; LMULMAX1-RV32-NEXT: vse1.v v25, (a0) 201; LMULMAX1-RV32-NEXT: addi a0, a0, 2 202; LMULMAX1-RV32-NEXT: vse1.v v25, (a0) 203; LMULMAX1-RV32-NEXT: ret 204; 205; LMULMAX1-RV64-LABEL: splat_zeros_v32i1: 206; LMULMAX1-RV64: # %bb.0: 207; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu 208; LMULMAX1-RV64-NEXT: vmclr.m v25 209; LMULMAX1-RV64-NEXT: vse1.v v25, (a0) 210; LMULMAX1-RV64-NEXT: addi a0, a0, 2 211; LMULMAX1-RV64-NEXT: vse1.v v25, (a0) 212; LMULMAX1-RV64-NEXT: ret 213 store <32 x i1> zeroinitializer, <32 x i1>* %x 214 ret void 215} 216 217define void @splat_v32i1(<32 x i1>* %x, i1 %y) { 218; LMULMAX2-LABEL: splat_v32i1: 219; LMULMAX2: # %bb.0: 220; LMULMAX2-NEXT: andi a1, a1, 1 221; LMULMAX2-NEXT: addi a2, zero, 32 222; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu 223; LMULMAX2-NEXT: vmv.v.x v26, a1 224; LMULMAX2-NEXT: vmsne.vi v25, v26, 0 225; LMULMAX2-NEXT: vse1.v v25, (a0) 226; LMULMAX2-NEXT: ret 227; 228; LMULMAX1-RV32-LABEL: splat_v32i1: 229; LMULMAX1-RV32: # %bb.0: 230; LMULMAX1-RV32-NEXT: andi a1, a1, 1 231; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu 232; LMULMAX1-RV32-NEXT: vmv.v.x v25, a1 233; LMULMAX1-RV32-NEXT: vmsne.vi v25, v25, 0 234; LMULMAX1-RV32-NEXT: addi a1, a0, 2 235; LMULMAX1-RV32-NEXT: vse1.v v25, (a1) 236; LMULMAX1-RV32-NEXT: vse1.v v25, (a0) 237; LMULMAX1-RV32-NEXT: ret 238; 239; LMULMAX1-RV64-LABEL: splat_v32i1: 240; LMULMAX1-RV64: # %bb.0: 241; LMULMAX1-RV64-NEXT: andi a1, a1, 1 242; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu 243; LMULMAX1-RV64-NEXT: vmv.v.x v25, a1 244; LMULMAX1-RV64-NEXT: vmsne.vi v25, v25, 0 245; LMULMAX1-RV64-NEXT: addi a1, a0, 2 246; LMULMAX1-RV64-NEXT: vse1.v v25, (a1) 247; LMULMAX1-RV64-NEXT: vse1.v v25, (a0) 248; LMULMAX1-RV64-NEXT: ret 249 %a = insertelement <32 x i1> undef, i1 %y, i32 0 250 %b = shufflevector <32 x i1> %a, <32 x i1> undef, <32 x i32> zeroinitializer 251 store <32 x i1> %b, <32 x i1>* %x 252 ret void 253} 254 255define void @splat_ones_v64i1(<64 x i1>* %x) { 256; LMULMAX2-LABEL: splat_ones_v64i1: 257; LMULMAX2: # %bb.0: 258; LMULMAX2-NEXT: addi a1, a0, 4 259; LMULMAX2-NEXT: addi a2, zero, 32 260; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu 261; LMULMAX2-NEXT: vmset.m v25 262; LMULMAX2-NEXT: vse1.v v25, (a1) 263; LMULMAX2-NEXT: vse1.v v25, (a0) 264; LMULMAX2-NEXT: ret 265; 266; LMULMAX1-RV32-LABEL: splat_ones_v64i1: 267; LMULMAX1-RV32: # %bb.0: 268; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu 269; LMULMAX1-RV32-NEXT: vmset.m v25 270; LMULMAX1-RV32-NEXT: vse1.v v25, (a0) 271; LMULMAX1-RV32-NEXT: addi a1, a0, 6 272; LMULMAX1-RV32-NEXT: vse1.v v25, (a1) 273; LMULMAX1-RV32-NEXT: addi a1, a0, 4 274; LMULMAX1-RV32-NEXT: vse1.v v25, (a1) 275; LMULMAX1-RV32-NEXT: addi a0, a0, 2 276; LMULMAX1-RV32-NEXT: vse1.v v25, (a0) 277; LMULMAX1-RV32-NEXT: ret 278; 279; LMULMAX1-RV64-LABEL: splat_ones_v64i1: 280; LMULMAX1-RV64: # %bb.0: 281; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu 282; LMULMAX1-RV64-NEXT: vmset.m v25 283; LMULMAX1-RV64-NEXT: vse1.v v25, (a0) 284; LMULMAX1-RV64-NEXT: addi a1, a0, 6 285; LMULMAX1-RV64-NEXT: vse1.v v25, (a1) 286; LMULMAX1-RV64-NEXT: addi a1, a0, 4 287; LMULMAX1-RV64-NEXT: vse1.v v25, (a1) 288; LMULMAX1-RV64-NEXT: addi a0, a0, 2 289; LMULMAX1-RV64-NEXT: vse1.v v25, (a0) 290; LMULMAX1-RV64-NEXT: ret 291 store <64 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, <64 x i1>* %x 292 ret void 293} 294 295define void @splat_v64i1(<64 x i1>* %x, i1 %y) { 296; LMULMAX2-LABEL: splat_v64i1: 297; LMULMAX2: # %bb.0: 298; LMULMAX2-NEXT: andi a1, a1, 1 299; LMULMAX2-NEXT: addi a2, zero, 32 300; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu 301; LMULMAX2-NEXT: vmv.v.x v26, a1 302; LMULMAX2-NEXT: vmsne.vi v25, v26, 0 303; LMULMAX2-NEXT: addi a1, a0, 4 304; LMULMAX2-NEXT: vse1.v v25, (a1) 305; LMULMAX2-NEXT: vse1.v v25, (a0) 306; LMULMAX2-NEXT: ret 307; 308; LMULMAX1-RV32-LABEL: splat_v64i1: 309; LMULMAX1-RV32: # %bb.0: 310; LMULMAX1-RV32-NEXT: andi a1, a1, 1 311; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu 312; LMULMAX1-RV32-NEXT: vmv.v.x v25, a1 313; LMULMAX1-RV32-NEXT: vmsne.vi v25, v25, 0 314; LMULMAX1-RV32-NEXT: addi a1, a0, 6 315; LMULMAX1-RV32-NEXT: vse1.v v25, (a1) 316; LMULMAX1-RV32-NEXT: addi a1, a0, 4 317; LMULMAX1-RV32-NEXT: vse1.v v25, (a1) 318; LMULMAX1-RV32-NEXT: addi a1, a0, 2 319; LMULMAX1-RV32-NEXT: vse1.v v25, (a1) 320; LMULMAX1-RV32-NEXT: vse1.v v25, (a0) 321; LMULMAX1-RV32-NEXT: ret 322; 323; LMULMAX1-RV64-LABEL: splat_v64i1: 324; LMULMAX1-RV64: # %bb.0: 325; LMULMAX1-RV64-NEXT: andi a1, a1, 1 326; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu 327; LMULMAX1-RV64-NEXT: vmv.v.x v25, a1 328; LMULMAX1-RV64-NEXT: vmsne.vi v25, v25, 0 329; LMULMAX1-RV64-NEXT: addi a1, a0, 6 330; LMULMAX1-RV64-NEXT: vse1.v v25, (a1) 331; LMULMAX1-RV64-NEXT: addi a1, a0, 4 332; LMULMAX1-RV64-NEXT: vse1.v v25, (a1) 333; LMULMAX1-RV64-NEXT: addi a1, a0, 2 334; LMULMAX1-RV64-NEXT: vse1.v v25, (a1) 335; LMULMAX1-RV64-NEXT: vse1.v v25, (a0) 336; LMULMAX1-RV64-NEXT: ret 337 %a = insertelement <64 x i1> undef, i1 %y, i32 0 338 %b = shufflevector <64 x i1> %a, <64 x i1> undef, <64 x i32> zeroinitializer 339 store <64 x i1> %b, <64 x i1>* %x 340 ret void 341} 342