1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s --check-prefixes=CHECK,RV32
4; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s --check-prefixes=CHECK,RV64
6
7declare <2 x i8> @llvm.vp.shl.v2i8(<2 x i8>, <2 x i8>, <2 x i1>, i32)
8
9define <2 x i8> @vsll_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zeroext %evl) {
10; CHECK-LABEL: vsll_vv_v2i8:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu
13; CHECK-NEXT:    vsll.vv v8, v8, v9, v0.t
14; CHECK-NEXT:    ret
15  %v = call <2 x i8> @llvm.vp.shl.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl)
16  ret <2 x i8> %v
17}
18
19define <2 x i8> @vsll_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %evl) {
20; CHECK-LABEL: vsll_vv_v2i8_unmasked:
21; CHECK:       # %bb.0:
22; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu
23; CHECK-NEXT:    vsll.vv v8, v8, v9
24; CHECK-NEXT:    ret
25  %head = insertelement <2 x i1> undef, i1 true, i32 0
26  %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer
27  %v = call <2 x i8> @llvm.vp.shl.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl)
28  ret <2 x i8> %v
29}
30
31define <2 x i8> @vsll_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl) {
32; CHECK-LABEL: vsll_vx_v2i8:
33; CHECK:       # %bb.0:
34; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, mu
35; CHECK-NEXT:    vsll.vx v8, v8, a0, v0.t
36; CHECK-NEXT:    ret
37  %elt.head = insertelement <2 x i8> undef, i8 %b, i32 0
38  %vb = shufflevector <2 x i8> %elt.head, <2 x i8> undef, <2 x i32> zeroinitializer
39  %v = call <2 x i8> @llvm.vp.shl.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl)
40  ret <2 x i8> %v
41}
42
43define <2 x i8> @vsll_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) {
44; CHECK-LABEL: vsll_vx_v2i8_unmasked:
45; CHECK:       # %bb.0:
46; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, mu
47; CHECK-NEXT:    vsll.vx v8, v8, a0
48; CHECK-NEXT:    ret
49  %elt.head = insertelement <2 x i8> undef, i8 %b, i32 0
50  %vb = shufflevector <2 x i8> %elt.head, <2 x i8> undef, <2 x i32> zeroinitializer
51  %head = insertelement <2 x i1> undef, i1 true, i32 0
52  %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer
53  %v = call <2 x i8> @llvm.vp.shl.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl)
54  ret <2 x i8> %v
55}
56
57define <2 x i8> @vsll_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {
58; CHECK-LABEL: vsll_vi_v2i8:
59; CHECK:       # %bb.0:
60; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu
61; CHECK-NEXT:    vsll.vi v8, v8, 3, v0.t
62; CHECK-NEXT:    ret
63  %elt.head = insertelement <2 x i8> undef, i8 3, i32 0
64  %vb = shufflevector <2 x i8> %elt.head, <2 x i8> undef, <2 x i32> zeroinitializer
65  %v = call <2 x i8> @llvm.vp.shl.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl)
66  ret <2 x i8> %v
67}
68
69define <2 x i8> @vsll_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {
70; CHECK-LABEL: vsll_vi_v2i8_unmasked:
71; CHECK:       # %bb.0:
72; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu
73; CHECK-NEXT:    vsll.vi v8, v8, 3
74; CHECK-NEXT:    ret
75  %elt.head = insertelement <2 x i8> undef, i8 3, i32 0
76  %vb = shufflevector <2 x i8> %elt.head, <2 x i8> undef, <2 x i32> zeroinitializer
77  %head = insertelement <2 x i1> undef, i1 true, i32 0
78  %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer
79  %v = call <2 x i8> @llvm.vp.shl.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl)
80  ret <2 x i8> %v
81}
82
83declare <4 x i8> @llvm.vp.shl.v4i8(<4 x i8>, <4 x i8>, <4 x i1>, i32)
84
85define <4 x i8> @vsll_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zeroext %evl) {
86; CHECK-LABEL: vsll_vv_v4i8:
87; CHECK:       # %bb.0:
88; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, mu
89; CHECK-NEXT:    vsll.vv v8, v8, v9, v0.t
90; CHECK-NEXT:    ret
91  %v = call <4 x i8> @llvm.vp.shl.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl)
92  ret <4 x i8> %v
93}
94
95define <4 x i8> @vsll_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %evl) {
96; CHECK-LABEL: vsll_vv_v4i8_unmasked:
97; CHECK:       # %bb.0:
98; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, mu
99; CHECK-NEXT:    vsll.vv v8, v8, v9
100; CHECK-NEXT:    ret
101  %head = insertelement <4 x i1> undef, i1 true, i32 0
102  %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer
103  %v = call <4 x i8> @llvm.vp.shl.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl)
104  ret <4 x i8> %v
105}
106
107define <4 x i8> @vsll_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {
108; CHECK-LABEL: vsll_vx_v4i8:
109; CHECK:       # %bb.0:
110; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, mu
111; CHECK-NEXT:    vsll.vx v8, v8, a0, v0.t
112; CHECK-NEXT:    ret
113  %elt.head = insertelement <4 x i8> undef, i8 %b, i32 0
114  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> undef, <4 x i32> zeroinitializer
115  %v = call <4 x i8> @llvm.vp.shl.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl)
116  ret <4 x i8> %v
117}
118
119define <4 x i8> @vsll_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) {
120; CHECK-LABEL: vsll_vx_v4i8_unmasked:
121; CHECK:       # %bb.0:
122; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, mu
123; CHECK-NEXT:    vsll.vx v8, v8, a0
124; CHECK-NEXT:    ret
125  %elt.head = insertelement <4 x i8> undef, i8 %b, i32 0
126  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> undef, <4 x i32> zeroinitializer
127  %head = insertelement <4 x i1> undef, i1 true, i32 0
128  %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer
129  %v = call <4 x i8> @llvm.vp.shl.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl)
130  ret <4 x i8> %v
131}
132
133define <4 x i8> @vsll_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
134; CHECK-LABEL: vsll_vi_v4i8:
135; CHECK:       # %bb.0:
136; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, mu
137; CHECK-NEXT:    vsll.vi v8, v8, 3, v0.t
138; CHECK-NEXT:    ret
139  %elt.head = insertelement <4 x i8> undef, i8 3, i32 0
140  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> undef, <4 x i32> zeroinitializer
141  %v = call <4 x i8> @llvm.vp.shl.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl)
142  ret <4 x i8> %v
143}
144
145define <4 x i8> @vsll_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
146; CHECK-LABEL: vsll_vi_v4i8_unmasked:
147; CHECK:       # %bb.0:
148; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, mu
149; CHECK-NEXT:    vsll.vi v8, v8, 3
150; CHECK-NEXT:    ret
151  %elt.head = insertelement <4 x i8> undef, i8 3, i32 0
152  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> undef, <4 x i32> zeroinitializer
153  %head = insertelement <4 x i1> undef, i1 true, i32 0
154  %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer
155  %v = call <4 x i8> @llvm.vp.shl.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl)
156  ret <4 x i8> %v
157}
158
159declare <8 x i8> @llvm.vp.shl.v8i8(<8 x i8>, <8 x i8>, <8 x i1>, i32)
160
161define <8 x i8> @vsll_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zeroext %evl) {
162; CHECK-LABEL: vsll_vv_v8i8:
163; CHECK:       # %bb.0:
164; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, mu
165; CHECK-NEXT:    vsll.vv v8, v8, v9, v0.t
166; CHECK-NEXT:    ret
167  %v = call <8 x i8> @llvm.vp.shl.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl)
168  ret <8 x i8> %v
169}
170
171define <8 x i8> @vsll_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %evl) {
172; CHECK-LABEL: vsll_vv_v8i8_unmasked:
173; CHECK:       # %bb.0:
174; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, mu
175; CHECK-NEXT:    vsll.vv v8, v8, v9
176; CHECK-NEXT:    ret
177  %head = insertelement <8 x i1> undef, i1 true, i32 0
178  %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer
179  %v = call <8 x i8> @llvm.vp.shl.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl)
180  ret <8 x i8> %v
181}
182
183define <8 x i8> @vsll_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %evl) {
184; CHECK-LABEL: vsll_vx_v8i8:
185; CHECK:       # %bb.0:
186; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, mu
187; CHECK-NEXT:    vsll.vx v8, v8, a0, v0.t
188; CHECK-NEXT:    ret
189  %elt.head = insertelement <8 x i8> undef, i8 %b, i32 0
190  %vb = shufflevector <8 x i8> %elt.head, <8 x i8> undef, <8 x i32> zeroinitializer
191  %v = call <8 x i8> @llvm.vp.shl.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl)
192  ret <8 x i8> %v
193}
194
195define <8 x i8> @vsll_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) {
196; CHECK-LABEL: vsll_vx_v8i8_unmasked:
197; CHECK:       # %bb.0:
198; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, mu
199; CHECK-NEXT:    vsll.vx v8, v8, a0
200; CHECK-NEXT:    ret
201  %elt.head = insertelement <8 x i8> undef, i8 %b, i32 0
202  %vb = shufflevector <8 x i8> %elt.head, <8 x i8> undef, <8 x i32> zeroinitializer
203  %head = insertelement <8 x i1> undef, i1 true, i32 0
204  %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer
205  %v = call <8 x i8> @llvm.vp.shl.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl)
206  ret <8 x i8> %v
207}
208
209define <8 x i8> @vsll_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
210; CHECK-LABEL: vsll_vi_v8i8:
211; CHECK:       # %bb.0:
212; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, mu
213; CHECK-NEXT:    vsll.vi v8, v8, 3, v0.t
214; CHECK-NEXT:    ret
215  %elt.head = insertelement <8 x i8> undef, i8 3, i32 0
216  %vb = shufflevector <8 x i8> %elt.head, <8 x i8> undef, <8 x i32> zeroinitializer
217  %v = call <8 x i8> @llvm.vp.shl.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl)
218  ret <8 x i8> %v
219}
220
221define <8 x i8> @vsll_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {
222; CHECK-LABEL: vsll_vi_v8i8_unmasked:
223; CHECK:       # %bb.0:
224; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, mu
225; CHECK-NEXT:    vsll.vi v8, v8, 3
226; CHECK-NEXT:    ret
227  %elt.head = insertelement <8 x i8> undef, i8 3, i32 0
228  %vb = shufflevector <8 x i8> %elt.head, <8 x i8> undef, <8 x i32> zeroinitializer
229  %head = insertelement <8 x i1> undef, i1 true, i32 0
230  %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer
231  %v = call <8 x i8> @llvm.vp.shl.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl)
232  ret <8 x i8> %v
233}
234
235declare <16 x i8> @llvm.vp.shl.v16i8(<16 x i8>, <16 x i8>, <16 x i1>, i32)
236
237define <16 x i8> @vsll_vv_v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 zeroext %evl) {
238; CHECK-LABEL: vsll_vv_v16i8:
239; CHECK:       # %bb.0:
240; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, mu
241; CHECK-NEXT:    vsll.vv v8, v8, v9, v0.t
242; CHECK-NEXT:    ret
243  %v = call <16 x i8> @llvm.vp.shl.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl)
244  ret <16 x i8> %v
245}
246
247define <16 x i8> @vsll_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroext %evl) {
248; CHECK-LABEL: vsll_vv_v16i8_unmasked:
249; CHECK:       # %bb.0:
250; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, mu
251; CHECK-NEXT:    vsll.vv v8, v8, v9
252; CHECK-NEXT:    ret
253  %head = insertelement <16 x i1> undef, i1 true, i32 0
254  %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer
255  %v = call <16 x i8> @llvm.vp.shl.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl)
256  ret <16 x i8> %v
257}
258
259define <16 x i8> @vsll_vx_v16i8(<16 x i8> %va, i8 %b, <16 x i1> %m, i32 zeroext %evl) {
260; CHECK-LABEL: vsll_vx_v16i8:
261; CHECK:       # %bb.0:
262; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, mu
263; CHECK-NEXT:    vsll.vx v8, v8, a0, v0.t
264; CHECK-NEXT:    ret
265  %elt.head = insertelement <16 x i8> undef, i8 %b, i32 0
266  %vb = shufflevector <16 x i8> %elt.head, <16 x i8> undef, <16 x i32> zeroinitializer
267  %v = call <16 x i8> @llvm.vp.shl.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl)
268  ret <16 x i8> %v
269}
270
271define <16 x i8> @vsll_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) {
272; CHECK-LABEL: vsll_vx_v16i8_unmasked:
273; CHECK:       # %bb.0:
274; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, mu
275; CHECK-NEXT:    vsll.vx v8, v8, a0
276; CHECK-NEXT:    ret
277  %elt.head = insertelement <16 x i8> undef, i8 %b, i32 0
278  %vb = shufflevector <16 x i8> %elt.head, <16 x i8> undef, <16 x i32> zeroinitializer
279  %head = insertelement <16 x i1> undef, i1 true, i32 0
280  %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer
281  %v = call <16 x i8> @llvm.vp.shl.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl)
282  ret <16 x i8> %v
283}
284
285define <16 x i8> @vsll_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {
286; CHECK-LABEL: vsll_vi_v16i8:
287; CHECK:       # %bb.0:
288; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, mu
289; CHECK-NEXT:    vsll.vi v8, v8, 3, v0.t
290; CHECK-NEXT:    ret
291  %elt.head = insertelement <16 x i8> undef, i8 3, i32 0
292  %vb = shufflevector <16 x i8> %elt.head, <16 x i8> undef, <16 x i32> zeroinitializer
293  %v = call <16 x i8> @llvm.vp.shl.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl)
294  ret <16 x i8> %v
295}
296
297define <16 x i8> @vsll_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {
298; CHECK-LABEL: vsll_vi_v16i8_unmasked:
299; CHECK:       # %bb.0:
300; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, mu
301; CHECK-NEXT:    vsll.vi v8, v8, 3
302; CHECK-NEXT:    ret
303  %elt.head = insertelement <16 x i8> undef, i8 3, i32 0
304  %vb = shufflevector <16 x i8> %elt.head, <16 x i8> undef, <16 x i32> zeroinitializer
305  %head = insertelement <16 x i1> undef, i1 true, i32 0
306  %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer
307  %v = call <16 x i8> @llvm.vp.shl.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl)
308  ret <16 x i8> %v
309}
310
311declare <2 x i16> @llvm.vp.shl.v2i16(<2 x i16>, <2 x i16>, <2 x i1>, i32)
312
313define <2 x i16> @vsll_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 zeroext %evl) {
314; CHECK-LABEL: vsll_vv_v2i16:
315; CHECK:       # %bb.0:
316; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, mu
317; CHECK-NEXT:    vsll.vv v8, v8, v9, v0.t
318; CHECK-NEXT:    ret
319  %v = call <2 x i16> @llvm.vp.shl.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl)
320  ret <2 x i16> %v
321}
322
323define <2 x i16> @vsll_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroext %evl) {
324; CHECK-LABEL: vsll_vv_v2i16_unmasked:
325; CHECK:       # %bb.0:
326; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, mu
327; CHECK-NEXT:    vsll.vv v8, v8, v9
328; CHECK-NEXT:    ret
329  %head = insertelement <2 x i1> undef, i1 true, i32 0
330  %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer
331  %v = call <2 x i16> @llvm.vp.shl.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl)
332  ret <2 x i16> %v
333}
334
335define <2 x i16> @vsll_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext %evl) {
336; CHECK-LABEL: vsll_vx_v2i16:
337; CHECK:       # %bb.0:
338; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu
339; CHECK-NEXT:    vsll.vx v8, v8, a0, v0.t
340; CHECK-NEXT:    ret
341  %elt.head = insertelement <2 x i16> undef, i16 %b, i32 0
342  %vb = shufflevector <2 x i16> %elt.head, <2 x i16> undef, <2 x i32> zeroinitializer
343  %v = call <2 x i16> @llvm.vp.shl.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl)
344  ret <2 x i16> %v
345}
346
347define <2 x i16> @vsll_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl) {
348; CHECK-LABEL: vsll_vx_v2i16_unmasked:
349; CHECK:       # %bb.0:
350; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu
351; CHECK-NEXT:    vsll.vx v8, v8, a0
352; CHECK-NEXT:    ret
353  %elt.head = insertelement <2 x i16> undef, i16 %b, i32 0
354  %vb = shufflevector <2 x i16> %elt.head, <2 x i16> undef, <2 x i32> zeroinitializer
355  %head = insertelement <2 x i1> undef, i1 true, i32 0
356  %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer
357  %v = call <2 x i16> @llvm.vp.shl.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl)
358  ret <2 x i16> %v
359}
360
361define <2 x i16> @vsll_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {
362; CHECK-LABEL: vsll_vi_v2i16:
363; CHECK:       # %bb.0:
364; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, mu
365; CHECK-NEXT:    vsll.vi v8, v8, 3, v0.t
366; CHECK-NEXT:    ret
367  %elt.head = insertelement <2 x i16> undef, i16 3, i32 0
368  %vb = shufflevector <2 x i16> %elt.head, <2 x i16> undef, <2 x i32> zeroinitializer
369  %v = call <2 x i16> @llvm.vp.shl.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl)
370  ret <2 x i16> %v
371}
372
373define <2 x i16> @vsll_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {
374; CHECK-LABEL: vsll_vi_v2i16_unmasked:
375; CHECK:       # %bb.0:
376; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, mu
377; CHECK-NEXT:    vsll.vi v8, v8, 3
378; CHECK-NEXT:    ret
379  %elt.head = insertelement <2 x i16> undef, i16 3, i32 0
380  %vb = shufflevector <2 x i16> %elt.head, <2 x i16> undef, <2 x i32> zeroinitializer
381  %head = insertelement <2 x i1> undef, i1 true, i32 0
382  %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer
383  %v = call <2 x i16> @llvm.vp.shl.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl)
384  ret <2 x i16> %v
385}
386
387declare <4 x i16> @llvm.vp.shl.v4i16(<4 x i16>, <4 x i16>, <4 x i1>, i32)
388
389define <4 x i16> @vsll_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 zeroext %evl) {
390; CHECK-LABEL: vsll_vv_v4i16:
391; CHECK:       # %bb.0:
392; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu
393; CHECK-NEXT:    vsll.vv v8, v8, v9, v0.t
394; CHECK-NEXT:    ret
395  %v = call <4 x i16> @llvm.vp.shl.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl)
396  ret <4 x i16> %v
397}
398
399define <4 x i16> @vsll_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroext %evl) {
400; CHECK-LABEL: vsll_vv_v4i16_unmasked:
401; CHECK:       # %bb.0:
402; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu
403; CHECK-NEXT:    vsll.vv v8, v8, v9
404; CHECK-NEXT:    ret
405  %head = insertelement <4 x i1> undef, i1 true, i32 0
406  %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer
407  %v = call <4 x i16> @llvm.vp.shl.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl)
408  ret <4 x i16> %v
409}
410
411define <4 x i16> @vsll_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext %evl) {
412; CHECK-LABEL: vsll_vx_v4i16:
413; CHECK:       # %bb.0:
414; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu
415; CHECK-NEXT:    vsll.vx v8, v8, a0, v0.t
416; CHECK-NEXT:    ret
417  %elt.head = insertelement <4 x i16> undef, i16 %b, i32 0
418  %vb = shufflevector <4 x i16> %elt.head, <4 x i16> undef, <4 x i32> zeroinitializer
419  %v = call <4 x i16> @llvm.vp.shl.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl)
420  ret <4 x i16> %v
421}
422
423define <4 x i16> @vsll_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl) {
424; CHECK-LABEL: vsll_vx_v4i16_unmasked:
425; CHECK:       # %bb.0:
426; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu
427; CHECK-NEXT:    vsll.vx v8, v8, a0
428; CHECK-NEXT:    ret
429  %elt.head = insertelement <4 x i16> undef, i16 %b, i32 0
430  %vb = shufflevector <4 x i16> %elt.head, <4 x i16> undef, <4 x i32> zeroinitializer
431  %head = insertelement <4 x i1> undef, i1 true, i32 0
432  %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer
433  %v = call <4 x i16> @llvm.vp.shl.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl)
434  ret <4 x i16> %v
435}
436
437define <4 x i16> @vsll_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
438; CHECK-LABEL: vsll_vi_v4i16:
439; CHECK:       # %bb.0:
440; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu
441; CHECK-NEXT:    vsll.vi v8, v8, 3, v0.t
442; CHECK-NEXT:    ret
443  %elt.head = insertelement <4 x i16> undef, i16 3, i32 0
444  %vb = shufflevector <4 x i16> %elt.head, <4 x i16> undef, <4 x i32> zeroinitializer
445  %v = call <4 x i16> @llvm.vp.shl.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl)
446  ret <4 x i16> %v
447}
448
449define <4 x i16> @vsll_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
450; CHECK-LABEL: vsll_vi_v4i16_unmasked:
451; CHECK:       # %bb.0:
452; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu
453; CHECK-NEXT:    vsll.vi v8, v8, 3
454; CHECK-NEXT:    ret
455  %elt.head = insertelement <4 x i16> undef, i16 3, i32 0
456  %vb = shufflevector <4 x i16> %elt.head, <4 x i16> undef, <4 x i32> zeroinitializer
457  %head = insertelement <4 x i1> undef, i1 true, i32 0
458  %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer
459  %v = call <4 x i16> @llvm.vp.shl.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl)
460  ret <4 x i16> %v
461}
462
463declare <8 x i16> @llvm.vp.shl.v8i16(<8 x i16>, <8 x i16>, <8 x i1>, i32)
464
465define <8 x i16> @vsll_vv_v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 zeroext %evl) {
466; CHECK-LABEL: vsll_vv_v8i16:
467; CHECK:       # %bb.0:
468; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu
469; CHECK-NEXT:    vsll.vv v8, v8, v9, v0.t
470; CHECK-NEXT:    ret
471  %v = call <8 x i16> @llvm.vp.shl.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl)
472  ret <8 x i16> %v
473}
474
475define <8 x i16> @vsll_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroext %evl) {
476; CHECK-LABEL: vsll_vv_v8i16_unmasked:
477; CHECK:       # %bb.0:
478; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu
479; CHECK-NEXT:    vsll.vv v8, v8, v9
480; CHECK-NEXT:    ret
481  %head = insertelement <8 x i1> undef, i1 true, i32 0
482  %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer
483  %v = call <8 x i16> @llvm.vp.shl.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl)
484  ret <8 x i16> %v
485}
486
487define <8 x i16> @vsll_vx_v8i16(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroext %evl) {
488; CHECK-LABEL: vsll_vx_v8i16:
489; CHECK:       # %bb.0:
490; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu
491; CHECK-NEXT:    vsll.vx v8, v8, a0, v0.t
492; CHECK-NEXT:    ret
493  %elt.head = insertelement <8 x i16> undef, i16 %b, i32 0
494  %vb = shufflevector <8 x i16> %elt.head, <8 x i16> undef, <8 x i32> zeroinitializer
495  %v = call <8 x i16> @llvm.vp.shl.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl)
496  ret <8 x i16> %v
497}
498
499define <8 x i16> @vsll_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl) {
500; CHECK-LABEL: vsll_vx_v8i16_unmasked:
501; CHECK:       # %bb.0:
502; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu
503; CHECK-NEXT:    vsll.vx v8, v8, a0
504; CHECK-NEXT:    ret
505  %elt.head = insertelement <8 x i16> undef, i16 %b, i32 0
506  %vb = shufflevector <8 x i16> %elt.head, <8 x i16> undef, <8 x i32> zeroinitializer
507  %head = insertelement <8 x i1> undef, i1 true, i32 0
508  %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer
509  %v = call <8 x i16> @llvm.vp.shl.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl)
510  ret <8 x i16> %v
511}
512
513define <8 x i16> @vsll_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {
514; CHECK-LABEL: vsll_vi_v8i16:
515; CHECK:       # %bb.0:
516; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu
517; CHECK-NEXT:    vsll.vi v8, v8, 3, v0.t
518; CHECK-NEXT:    ret
519  %elt.head = insertelement <8 x i16> undef, i16 3, i32 0
520  %vb = shufflevector <8 x i16> %elt.head, <8 x i16> undef, <8 x i32> zeroinitializer
521  %v = call <8 x i16> @llvm.vp.shl.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl)
522  ret <8 x i16> %v
523}
524
525define <8 x i16> @vsll_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {
526; CHECK-LABEL: vsll_vi_v8i16_unmasked:
527; CHECK:       # %bb.0:
528; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu
529; CHECK-NEXT:    vsll.vi v8, v8, 3
530; CHECK-NEXT:    ret
531  %elt.head = insertelement <8 x i16> undef, i16 3, i32 0
532  %vb = shufflevector <8 x i16> %elt.head, <8 x i16> undef, <8 x i32> zeroinitializer
533  %head = insertelement <8 x i1> undef, i1 true, i32 0
534  %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer
535  %v = call <8 x i16> @llvm.vp.shl.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl)
536  ret <8 x i16> %v
537}
538
539declare <16 x i16> @llvm.vp.shl.v16i16(<16 x i16>, <16 x i16>, <16 x i1>, i32)
540
541define <16 x i16> @vsll_vv_v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 zeroext %evl) {
542; CHECK-LABEL: vsll_vv_v16i16:
543; CHECK:       # %bb.0:
544; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, mu
545; CHECK-NEXT:    vsll.vv v8, v8, v10, v0.t
546; CHECK-NEXT:    ret
547  %v = call <16 x i16> @llvm.vp.shl.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl)
548  ret <16 x i16> %v
549}
550
551define <16 x i16> @vsll_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 zeroext %evl) {
552; CHECK-LABEL: vsll_vv_v16i16_unmasked:
553; CHECK:       # %bb.0:
554; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, mu
555; CHECK-NEXT:    vsll.vv v8, v8, v10
556; CHECK-NEXT:    ret
557  %head = insertelement <16 x i1> undef, i1 true, i32 0
558  %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer
559  %v = call <16 x i16> @llvm.vp.shl.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl)
560  ret <16 x i16> %v
561}
562
563define <16 x i16> @vsll_vx_v16i16(<16 x i16> %va, i16 %b, <16 x i1> %m, i32 zeroext %evl) {
564; CHECK-LABEL: vsll_vx_v16i16:
565; CHECK:       # %bb.0:
566; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu
567; CHECK-NEXT:    vsll.vx v8, v8, a0, v0.t
568; CHECK-NEXT:    ret
569  %elt.head = insertelement <16 x i16> undef, i16 %b, i32 0
570  %vb = shufflevector <16 x i16> %elt.head, <16 x i16> undef, <16 x i32> zeroinitializer
571  %v = call <16 x i16> @llvm.vp.shl.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl)
572  ret <16 x i16> %v
573}
574
575define <16 x i16> @vsll_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext %evl) {
576; CHECK-LABEL: vsll_vx_v16i16_unmasked:
577; CHECK:       # %bb.0:
578; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu
579; CHECK-NEXT:    vsll.vx v8, v8, a0
580; CHECK-NEXT:    ret
581  %elt.head = insertelement <16 x i16> undef, i16 %b, i32 0
582  %vb = shufflevector <16 x i16> %elt.head, <16 x i16> undef, <16 x i32> zeroinitializer
583  %head = insertelement <16 x i1> undef, i1 true, i32 0
584  %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer
585  %v = call <16 x i16> @llvm.vp.shl.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl)
586  ret <16 x i16> %v
587}
588
589define <16 x i16> @vsll_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {
590; CHECK-LABEL: vsll_vi_v16i16:
591; CHECK:       # %bb.0:
592; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, mu
593; CHECK-NEXT:    vsll.vi v8, v8, 3, v0.t
594; CHECK-NEXT:    ret
595  %elt.head = insertelement <16 x i16> undef, i16 3, i32 0
596  %vb = shufflevector <16 x i16> %elt.head, <16 x i16> undef, <16 x i32> zeroinitializer
597  %v = call <16 x i16> @llvm.vp.shl.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl)
598  ret <16 x i16> %v
599}
600
601define <16 x i16> @vsll_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
602; CHECK-LABEL: vsll_vi_v16i16_unmasked:
603; CHECK:       # %bb.0:
604; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, mu
605; CHECK-NEXT:    vsll.vi v8, v8, 3
606; CHECK-NEXT:    ret
607  %elt.head = insertelement <16 x i16> undef, i16 3, i32 0
608  %vb = shufflevector <16 x i16> %elt.head, <16 x i16> undef, <16 x i32> zeroinitializer
609  %head = insertelement <16 x i1> undef, i1 true, i32 0
610  %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer
611  %v = call <16 x i16> @llvm.vp.shl.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl)
612  ret <16 x i16> %v
613}
614
615declare <2 x i32> @llvm.vp.shl.v2i32(<2 x i32>, <2 x i32>, <2 x i1>, i32)
616
617define <2 x i32> @vsll_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 zeroext %evl) {
618; CHECK-LABEL: vsll_vv_v2i32:
619; CHECK:       # %bb.0:
620; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, mu
621; CHECK-NEXT:    vsll.vv v8, v8, v9, v0.t
622; CHECK-NEXT:    ret
623  %v = call <2 x i32> @llvm.vp.shl.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl)
624  ret <2 x i32> %v
625}
626
627define <2 x i32> @vsll_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroext %evl) {
628; CHECK-LABEL: vsll_vv_v2i32_unmasked:
629; CHECK:       # %bb.0:
630; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, mu
631; CHECK-NEXT:    vsll.vv v8, v8, v9
632; CHECK-NEXT:    ret
633  %head = insertelement <2 x i1> undef, i1 true, i32 0
634  %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer
635  %v = call <2 x i32> @llvm.vp.shl.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl)
636  ret <2 x i32> %v
637}
638
639define <2 x i32> @vsll_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext %evl) {
640; CHECK-LABEL: vsll_vx_v2i32:
641; CHECK:       # %bb.0:
642; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu
643; CHECK-NEXT:    vsll.vx v8, v8, a0, v0.t
644; CHECK-NEXT:    ret
645  %elt.head = insertelement <2 x i32> undef, i32 %b, i32 0
646  %vb = shufflevector <2 x i32> %elt.head, <2 x i32> undef, <2 x i32> zeroinitializer
647  %v = call <2 x i32> @llvm.vp.shl.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl)
648  ret <2 x i32> %v
649}
650
651define <2 x i32> @vsll_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl) {
652; CHECK-LABEL: vsll_vx_v2i32_unmasked:
653; CHECK:       # %bb.0:
654; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu
655; CHECK-NEXT:    vsll.vx v8, v8, a0
656; CHECK-NEXT:    ret
657  %elt.head = insertelement <2 x i32> undef, i32 %b, i32 0
658  %vb = shufflevector <2 x i32> %elt.head, <2 x i32> undef, <2 x i32> zeroinitializer
659  %head = insertelement <2 x i1> undef, i1 true, i32 0
660  %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer
661  %v = call <2 x i32> @llvm.vp.shl.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl)
662  ret <2 x i32> %v
663}
664
665define <2 x i32> @vsll_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {
666; CHECK-LABEL: vsll_vi_v2i32:
667; CHECK:       # %bb.0:
668; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, mu
669; CHECK-NEXT:    vsll.vi v8, v8, 3, v0.t
670; CHECK-NEXT:    ret
671  %elt.head = insertelement <2 x i32> undef, i32 3, i32 0
672  %vb = shufflevector <2 x i32> %elt.head, <2 x i32> undef, <2 x i32> zeroinitializer
673  %v = call <2 x i32> @llvm.vp.shl.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl)
674  ret <2 x i32> %v
675}
676
677define <2 x i32> @vsll_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {
678; CHECK-LABEL: vsll_vi_v2i32_unmasked:
679; CHECK:       # %bb.0:
680; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, mu
681; CHECK-NEXT:    vsll.vi v8, v8, 3
682; CHECK-NEXT:    ret
683  %elt.head = insertelement <2 x i32> undef, i32 3, i32 0
684  %vb = shufflevector <2 x i32> %elt.head, <2 x i32> undef, <2 x i32> zeroinitializer
685  %head = insertelement <2 x i1> undef, i1 true, i32 0
686  %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer
687  %v = call <2 x i32> @llvm.vp.shl.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl)
688  ret <2 x i32> %v
689}
690
691declare <4 x i32> @llvm.vp.shl.v4i32(<4 x i32>, <4 x i32>, <4 x i1>, i32)
692
693define <4 x i32> @vsll_vv_v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 zeroext %evl) {
694; CHECK-LABEL: vsll_vv_v4i32:
695; CHECK:       # %bb.0:
696; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, mu
697; CHECK-NEXT:    vsll.vv v8, v8, v9, v0.t
698; CHECK-NEXT:    ret
699  %v = call <4 x i32> @llvm.vp.shl.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl)
700  ret <4 x i32> %v
701}
702
703define <4 x i32> @vsll_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroext %evl) {
704; CHECK-LABEL: vsll_vv_v4i32_unmasked:
705; CHECK:       # %bb.0:
706; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, mu
707; CHECK-NEXT:    vsll.vv v8, v8, v9
708; CHECK-NEXT:    ret
709  %head = insertelement <4 x i1> undef, i1 true, i32 0
710  %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer
711  %v = call <4 x i32> @llvm.vp.shl.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl)
712  ret <4 x i32> %v
713}
714
715define <4 x i32> @vsll_vx_v4i32(<4 x i32> %va, i32 %b, <4 x i1> %m, i32 zeroext %evl) {
716; CHECK-LABEL: vsll_vx_v4i32:
717; CHECK:       # %bb.0:
718; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu
719; CHECK-NEXT:    vsll.vx v8, v8, a0, v0.t
720; CHECK-NEXT:    ret
721  %elt.head = insertelement <4 x i32> undef, i32 %b, i32 0
722  %vb = shufflevector <4 x i32> %elt.head, <4 x i32> undef, <4 x i32> zeroinitializer
723  %v = call <4 x i32> @llvm.vp.shl.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl)
724  ret <4 x i32> %v
725}
726
727define <4 x i32> @vsll_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl) {
728; CHECK-LABEL: vsll_vx_v4i32_unmasked:
729; CHECK:       # %bb.0:
730; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu
731; CHECK-NEXT:    vsll.vx v8, v8, a0
732; CHECK-NEXT:    ret
733  %elt.head = insertelement <4 x i32> undef, i32 %b, i32 0
734  %vb = shufflevector <4 x i32> %elt.head, <4 x i32> undef, <4 x i32> zeroinitializer
735  %head = insertelement <4 x i1> undef, i1 true, i32 0
736  %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer
737  %v = call <4 x i32> @llvm.vp.shl.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl)
738  ret <4 x i32> %v
739}
740
741define <4 x i32> @vsll_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
742; CHECK-LABEL: vsll_vi_v4i32:
743; CHECK:       # %bb.0:
744; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, mu
745; CHECK-NEXT:    vsll.vi v8, v8, 3, v0.t
746; CHECK-NEXT:    ret
747  %elt.head = insertelement <4 x i32> undef, i32 3, i32 0
748  %vb = shufflevector <4 x i32> %elt.head, <4 x i32> undef, <4 x i32> zeroinitializer
749  %v = call <4 x i32> @llvm.vp.shl.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl)
750  ret <4 x i32> %v
751}
752
753define <4 x i32> @vsll_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
754; CHECK-LABEL: vsll_vi_v4i32_unmasked:
755; CHECK:       # %bb.0:
756; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, mu
757; CHECK-NEXT:    vsll.vi v8, v8, 3
758; CHECK-NEXT:    ret
759  %elt.head = insertelement <4 x i32> undef, i32 3, i32 0
760  %vb = shufflevector <4 x i32> %elt.head, <4 x i32> undef, <4 x i32> zeroinitializer
761  %head = insertelement <4 x i1> undef, i1 true, i32 0
762  %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer
763  %v = call <4 x i32> @llvm.vp.shl.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl)
764  ret <4 x i32> %v
765}
766
767declare <8 x i32> @llvm.vp.shl.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
768
769define <8 x i32> @vsll_vv_v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 zeroext %evl) {
770; CHECK-LABEL: vsll_vv_v8i32:
771; CHECK:       # %bb.0:
772; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, mu
773; CHECK-NEXT:    vsll.vv v8, v8, v10, v0.t
774; CHECK-NEXT:    ret
775  %v = call <8 x i32> @llvm.vp.shl.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl)
776  ret <8 x i32> %v
777}
778
779define <8 x i32> @vsll_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroext %evl) {
780; CHECK-LABEL: vsll_vv_v8i32_unmasked:
781; CHECK:       # %bb.0:
782; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, mu
783; CHECK-NEXT:    vsll.vv v8, v8, v10
784; CHECK-NEXT:    ret
785  %head = insertelement <8 x i1> undef, i1 true, i32 0
786  %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer
787  %v = call <8 x i32> @llvm.vp.shl.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl)
788  ret <8 x i32> %v
789}
790
791define <8 x i32> @vsll_vx_v8i32(<8 x i32> %va, i32 %b, <8 x i1> %m, i32 zeroext %evl) {
792; CHECK-LABEL: vsll_vx_v8i32:
793; CHECK:       # %bb.0:
794; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, mu
795; CHECK-NEXT:    vsll.vx v8, v8, a0, v0.t
796; CHECK-NEXT:    ret
797  %elt.head = insertelement <8 x i32> undef, i32 %b, i32 0
798  %vb = shufflevector <8 x i32> %elt.head, <8 x i32> undef, <8 x i32> zeroinitializer
799  %v = call <8 x i32> @llvm.vp.shl.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl)
800  ret <8 x i32> %v
801}
802
803define <8 x i32> @vsll_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl) {
804; CHECK-LABEL: vsll_vx_v8i32_unmasked:
805; CHECK:       # %bb.0:
806; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, mu
807; CHECK-NEXT:    vsll.vx v8, v8, a0
808; CHECK-NEXT:    ret
809  %elt.head = insertelement <8 x i32> undef, i32 %b, i32 0
810  %vb = shufflevector <8 x i32> %elt.head, <8 x i32> undef, <8 x i32> zeroinitializer
811  %head = insertelement <8 x i1> undef, i1 true, i32 0
812  %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer
813  %v = call <8 x i32> @llvm.vp.shl.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl)
814  ret <8 x i32> %v
815}
816
817define <8 x i32> @vsll_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
818; CHECK-LABEL: vsll_vi_v8i32:
819; CHECK:       # %bb.0:
820; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, mu
821; CHECK-NEXT:    vsll.vi v8, v8, 3, v0.t
822; CHECK-NEXT:    ret
823  %elt.head = insertelement <8 x i32> undef, i32 3, i32 0
824  %vb = shufflevector <8 x i32> %elt.head, <8 x i32> undef, <8 x i32> zeroinitializer
825  %v = call <8 x i32> @llvm.vp.shl.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl)
826  ret <8 x i32> %v
827}
828
829define <8 x i32> @vsll_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
830; CHECK-LABEL: vsll_vi_v8i32_unmasked:
831; CHECK:       # %bb.0:
832; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, mu
833; CHECK-NEXT:    vsll.vi v8, v8, 3
834; CHECK-NEXT:    ret
835  %elt.head = insertelement <8 x i32> undef, i32 3, i32 0
836  %vb = shufflevector <8 x i32> %elt.head, <8 x i32> undef, <8 x i32> zeroinitializer
837  %head = insertelement <8 x i1> undef, i1 true, i32 0
838  %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer
839  %v = call <8 x i32> @llvm.vp.shl.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl)
840  ret <8 x i32> %v
841}
842
843declare <16 x i32> @llvm.vp.shl.v16i32(<16 x i32>, <16 x i32>, <16 x i1>, i32)
844
845define <16 x i32> @vsll_vv_v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 zeroext %evl) {
846; CHECK-LABEL: vsll_vv_v16i32:
847; CHECK:       # %bb.0:
848; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, mu
849; CHECK-NEXT:    vsll.vv v8, v8, v12, v0.t
850; CHECK-NEXT:    ret
851  %v = call <16 x i32> @llvm.vp.shl.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl)
852  ret <16 x i32> %v
853}
854
855define <16 x i32> @vsll_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 zeroext %evl) {
856; CHECK-LABEL: vsll_vv_v16i32_unmasked:
857; CHECK:       # %bb.0:
858; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, mu
859; CHECK-NEXT:    vsll.vv v8, v8, v12
860; CHECK-NEXT:    ret
861  %head = insertelement <16 x i1> undef, i1 true, i32 0
862  %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer
863  %v = call <16 x i32> @llvm.vp.shl.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl)
864  ret <16 x i32> %v
865}
866
867define <16 x i32> @vsll_vx_v16i32(<16 x i32> %va, i32 %b, <16 x i1> %m, i32 zeroext %evl) {
868; CHECK-LABEL: vsll_vx_v16i32:
869; CHECK:       # %bb.0:
870; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, mu
871; CHECK-NEXT:    vsll.vx v8, v8, a0, v0.t
872; CHECK-NEXT:    ret
873  %elt.head = insertelement <16 x i32> undef, i32 %b, i32 0
874  %vb = shufflevector <16 x i32> %elt.head, <16 x i32> undef, <16 x i32> zeroinitializer
875  %v = call <16 x i32> @llvm.vp.shl.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl)
876  ret <16 x i32> %v
877}
878
879define <16 x i32> @vsll_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext %evl) {
880; CHECK-LABEL: vsll_vx_v16i32_unmasked:
881; CHECK:       # %bb.0:
882; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, mu
883; CHECK-NEXT:    vsll.vx v8, v8, a0
884; CHECK-NEXT:    ret
885  %elt.head = insertelement <16 x i32> undef, i32 %b, i32 0
886  %vb = shufflevector <16 x i32> %elt.head, <16 x i32> undef, <16 x i32> zeroinitializer
887  %head = insertelement <16 x i1> undef, i1 true, i32 0
888  %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer
889  %v = call <16 x i32> @llvm.vp.shl.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl)
890  ret <16 x i32> %v
891}
892
893define <16 x i32> @vsll_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {
894; CHECK-LABEL: vsll_vi_v16i32:
895; CHECK:       # %bb.0:
896; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, mu
897; CHECK-NEXT:    vsll.vi v8, v8, 3, v0.t
898; CHECK-NEXT:    ret
899  %elt.head = insertelement <16 x i32> undef, i32 3, i32 0
900  %vb = shufflevector <16 x i32> %elt.head, <16 x i32> undef, <16 x i32> zeroinitializer
901  %v = call <16 x i32> @llvm.vp.shl.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl)
902  ret <16 x i32> %v
903}
904
905define <16 x i32> @vsll_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
906; CHECK-LABEL: vsll_vi_v16i32_unmasked:
907; CHECK:       # %bb.0:
908; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, mu
909; CHECK-NEXT:    vsll.vi v8, v8, 3
910; CHECK-NEXT:    ret
911  %elt.head = insertelement <16 x i32> undef, i32 3, i32 0
912  %vb = shufflevector <16 x i32> %elt.head, <16 x i32> undef, <16 x i32> zeroinitializer
913  %head = insertelement <16 x i1> undef, i1 true, i32 0
914  %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer
915  %v = call <16 x i32> @llvm.vp.shl.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl)
916  ret <16 x i32> %v
917}
918
919declare <2 x i64> @llvm.vp.shl.v2i64(<2 x i64>, <2 x i64>, <2 x i1>, i32)
920
921define <2 x i64> @vsll_vv_v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 zeroext %evl) {
922; CHECK-LABEL: vsll_vv_v2i64:
923; CHECK:       # %bb.0:
924; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, mu
925; CHECK-NEXT:    vsll.vv v8, v8, v9, v0.t
926; CHECK-NEXT:    ret
927  %v = call <2 x i64> @llvm.vp.shl.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl)
928  ret <2 x i64> %v
929}
930
931define <2 x i64> @vsll_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroext %evl) {
932; CHECK-LABEL: vsll_vv_v2i64_unmasked:
933; CHECK:       # %bb.0:
934; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, mu
935; CHECK-NEXT:    vsll.vv v8, v8, v9
936; CHECK-NEXT:    ret
937  %head = insertelement <2 x i1> undef, i1 true, i32 0
938  %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer
939  %v = call <2 x i64> @llvm.vp.shl.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl)
940  ret <2 x i64> %v
941}
942
943define <2 x i64> @vsll_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {
944; RV32-LABEL: vsll_vx_v2i64:
945; RV32:       # %bb.0:
946; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, mu
947; RV32-NEXT:    vsll.vx v8, v8, a0, v0.t
948; RV32-NEXT:    ret
949;
950; RV64-LABEL: vsll_vx_v2i64:
951; RV64:       # %bb.0:
952; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, mu
953; RV64-NEXT:    vsll.vx v8, v8, a0, v0.t
954; RV64-NEXT:    ret
955  %elt.head = insertelement <2 x i64> undef, i64 %b, i32 0
956  %vb = shufflevector <2 x i64> %elt.head, <2 x i64> undef, <2 x i32> zeroinitializer
957  %v = call <2 x i64> @llvm.vp.shl.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)
958  ret <2 x i64> %v
959}
960
961define <2 x i64> @vsll_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {
962; RV32-LABEL: vsll_vx_v2i64_unmasked:
963; RV32:       # %bb.0:
964; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, mu
965; RV32-NEXT:    vsll.vx v8, v8, a0
966; RV32-NEXT:    ret
967;
968; RV64-LABEL: vsll_vx_v2i64_unmasked:
969; RV64:       # %bb.0:
970; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, mu
971; RV64-NEXT:    vsll.vx v8, v8, a0
972; RV64-NEXT:    ret
973  %elt.head = insertelement <2 x i64> undef, i64 %b, i32 0
974  %vb = shufflevector <2 x i64> %elt.head, <2 x i64> undef, <2 x i32> zeroinitializer
975  %head = insertelement <2 x i1> undef, i1 true, i32 0
976  %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer
977  %v = call <2 x i64> @llvm.vp.shl.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)
978  ret <2 x i64> %v
979}
980
981define <2 x i64> @vsll_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
982; CHECK-LABEL: vsll_vi_v2i64:
983; CHECK:       # %bb.0:
984; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, mu
985; CHECK-NEXT:    vsll.vi v8, v8, 3, v0.t
986; CHECK-NEXT:    ret
987  %elt.head = insertelement <2 x i64> undef, i64 3, i32 0
988  %vb = shufflevector <2 x i64> %elt.head, <2 x i64> undef, <2 x i32> zeroinitializer
989  %v = call <2 x i64> @llvm.vp.shl.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)
990  ret <2 x i64> %v
991}
992
993define <2 x i64> @vsll_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
994; CHECK-LABEL: vsll_vi_v2i64_unmasked:
995; CHECK:       # %bb.0:
996; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, mu
997; CHECK-NEXT:    vsll.vi v8, v8, 3
998; CHECK-NEXT:    ret
999  %elt.head = insertelement <2 x i64> undef, i64 3, i32 0
1000  %vb = shufflevector <2 x i64> %elt.head, <2 x i64> undef, <2 x i32> zeroinitializer
1001  %head = insertelement <2 x i1> undef, i1 true, i32 0
1002  %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer
1003  %v = call <2 x i64> @llvm.vp.shl.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)
1004  ret <2 x i64> %v
1005}
1006
1007declare <4 x i64> @llvm.vp.shl.v4i64(<4 x i64>, <4 x i64>, <4 x i1>, i32)
1008
1009define <4 x i64> @vsll_vv_v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 zeroext %evl) {
1010; CHECK-LABEL: vsll_vv_v4i64:
1011; CHECK:       # %bb.0:
1012; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, mu
1013; CHECK-NEXT:    vsll.vv v8, v8, v10, v0.t
1014; CHECK-NEXT:    ret
1015  %v = call <4 x i64> @llvm.vp.shl.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl)
1016  ret <4 x i64> %v
1017}
1018
1019define <4 x i64> @vsll_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroext %evl) {
1020; CHECK-LABEL: vsll_vv_v4i64_unmasked:
1021; CHECK:       # %bb.0:
1022; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, mu
1023; CHECK-NEXT:    vsll.vv v8, v8, v10
1024; CHECK-NEXT:    ret
1025  %head = insertelement <4 x i1> undef, i1 true, i32 0
1026  %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer
1027  %v = call <4 x i64> @llvm.vp.shl.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl)
1028  ret <4 x i64> %v
1029}
1030
1031define <4 x i64> @vsll_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {
1032; RV32-LABEL: vsll_vx_v4i64:
1033; RV32:       # %bb.0:
1034; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, mu
1035; RV32-NEXT:    vsll.vx v8, v8, a0, v0.t
1036; RV32-NEXT:    ret
1037;
1038; RV64-LABEL: vsll_vx_v4i64:
1039; RV64:       # %bb.0:
1040; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, mu
1041; RV64-NEXT:    vsll.vx v8, v8, a0, v0.t
1042; RV64-NEXT:    ret
1043  %elt.head = insertelement <4 x i64> undef, i64 %b, i32 0
1044  %vb = shufflevector <4 x i64> %elt.head, <4 x i64> undef, <4 x i32> zeroinitializer
1045  %v = call <4 x i64> @llvm.vp.shl.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)
1046  ret <4 x i64> %v
1047}
1048
1049define <4 x i64> @vsll_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {
1050; RV32-LABEL: vsll_vx_v4i64_unmasked:
1051; RV32:       # %bb.0:
1052; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, mu
1053; RV32-NEXT:    vsll.vx v8, v8, a0
1054; RV32-NEXT:    ret
1055;
1056; RV64-LABEL: vsll_vx_v4i64_unmasked:
1057; RV64:       # %bb.0:
1058; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, mu
1059; RV64-NEXT:    vsll.vx v8, v8, a0
1060; RV64-NEXT:    ret
1061  %elt.head = insertelement <4 x i64> undef, i64 %b, i32 0
1062  %vb = shufflevector <4 x i64> %elt.head, <4 x i64> undef, <4 x i32> zeroinitializer
1063  %head = insertelement <4 x i1> undef, i1 true, i32 0
1064  %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer
1065  %v = call <4 x i64> @llvm.vp.shl.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)
1066  ret <4 x i64> %v
1067}
1068
1069define <4 x i64> @vsll_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
1070; CHECK-LABEL: vsll_vi_v4i64:
1071; CHECK:       # %bb.0:
1072; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, mu
1073; CHECK-NEXT:    vsll.vi v8, v8, 3, v0.t
1074; CHECK-NEXT:    ret
1075  %elt.head = insertelement <4 x i64> undef, i64 3, i32 0
1076  %vb = shufflevector <4 x i64> %elt.head, <4 x i64> undef, <4 x i32> zeroinitializer
1077  %v = call <4 x i64> @llvm.vp.shl.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)
1078  ret <4 x i64> %v
1079}
1080
1081define <4 x i64> @vsll_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
1082; CHECK-LABEL: vsll_vi_v4i64_unmasked:
1083; CHECK:       # %bb.0:
1084; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, mu
1085; CHECK-NEXT:    vsll.vi v8, v8, 3
1086; CHECK-NEXT:    ret
1087  %elt.head = insertelement <4 x i64> undef, i64 3, i32 0
1088  %vb = shufflevector <4 x i64> %elt.head, <4 x i64> undef, <4 x i32> zeroinitializer
1089  %head = insertelement <4 x i1> undef, i1 true, i32 0
1090  %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer
1091  %v = call <4 x i64> @llvm.vp.shl.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)
1092  ret <4 x i64> %v
1093}
1094
1095declare <8 x i64> @llvm.vp.shl.v8i64(<8 x i64>, <8 x i64>, <8 x i1>, i32)
1096
1097define <8 x i64> @vsll_vv_v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 zeroext %evl) {
1098; CHECK-LABEL: vsll_vv_v8i64:
1099; CHECK:       # %bb.0:
1100; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, mu
1101; CHECK-NEXT:    vsll.vv v8, v8, v12, v0.t
1102; CHECK-NEXT:    ret
1103  %v = call <8 x i64> @llvm.vp.shl.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl)
1104  ret <8 x i64> %v
1105}
1106
1107define <8 x i64> @vsll_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroext %evl) {
1108; CHECK-LABEL: vsll_vv_v8i64_unmasked:
1109; CHECK:       # %bb.0:
1110; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, mu
1111; CHECK-NEXT:    vsll.vv v8, v8, v12
1112; CHECK-NEXT:    ret
1113  %head = insertelement <8 x i1> undef, i1 true, i32 0
1114  %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer
1115  %v = call <8 x i64> @llvm.vp.shl.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl)
1116  ret <8 x i64> %v
1117}
1118
1119define <8 x i64> @vsll_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
1120; RV32-LABEL: vsll_vx_v8i64:
1121; RV32:       # %bb.0:
1122; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, mu
1123; RV32-NEXT:    vsll.vx v8, v8, a0, v0.t
1124; RV32-NEXT:    ret
1125;
1126; RV64-LABEL: vsll_vx_v8i64:
1127; RV64:       # %bb.0:
1128; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, mu
1129; RV64-NEXT:    vsll.vx v8, v8, a0, v0.t
1130; RV64-NEXT:    ret
1131  %elt.head = insertelement <8 x i64> undef, i64 %b, i32 0
1132  %vb = shufflevector <8 x i64> %elt.head, <8 x i64> undef, <8 x i32> zeroinitializer
1133  %v = call <8 x i64> @llvm.vp.shl.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)
1134  ret <8 x i64> %v
1135}
1136
1137define <8 x i64> @vsll_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {
1138; RV32-LABEL: vsll_vx_v8i64_unmasked:
1139; RV32:       # %bb.0:
1140; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, mu
1141; RV32-NEXT:    vsll.vx v8, v8, a0
1142; RV32-NEXT:    ret
1143;
1144; RV64-LABEL: vsll_vx_v8i64_unmasked:
1145; RV64:       # %bb.0:
1146; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, mu
1147; RV64-NEXT:    vsll.vx v8, v8, a0
1148; RV64-NEXT:    ret
1149  %elt.head = insertelement <8 x i64> undef, i64 %b, i32 0
1150  %vb = shufflevector <8 x i64> %elt.head, <8 x i64> undef, <8 x i32> zeroinitializer
1151  %head = insertelement <8 x i1> undef, i1 true, i32 0
1152  %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer
1153  %v = call <8 x i64> @llvm.vp.shl.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)
1154  ret <8 x i64> %v
1155}
1156
1157define <8 x i64> @vsll_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
1158; CHECK-LABEL: vsll_vi_v8i64:
1159; CHECK:       # %bb.0:
1160; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, mu
1161; CHECK-NEXT:    vsll.vi v8, v8, 3, v0.t
1162; CHECK-NEXT:    ret
1163  %elt.head = insertelement <8 x i64> undef, i64 3, i32 0
1164  %vb = shufflevector <8 x i64> %elt.head, <8 x i64> undef, <8 x i32> zeroinitializer
1165  %v = call <8 x i64> @llvm.vp.shl.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)
1166  ret <8 x i64> %v
1167}
1168
1169define <8 x i64> @vsll_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
1170; CHECK-LABEL: vsll_vi_v8i64_unmasked:
1171; CHECK:       # %bb.0:
1172; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, mu
1173; CHECK-NEXT:    vsll.vi v8, v8, 3
1174; CHECK-NEXT:    ret
1175  %elt.head = insertelement <8 x i64> undef, i64 3, i32 0
1176  %vb = shufflevector <8 x i64> %elt.head, <8 x i64> undef, <8 x i32> zeroinitializer
1177  %head = insertelement <8 x i1> undef, i1 true, i32 0
1178  %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer
1179  %v = call <8 x i64> @llvm.vp.shl.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)
1180  ret <8 x i64> %v
1181}
1182
1183declare <16 x i64> @llvm.vp.shl.v16i64(<16 x i64>, <16 x i64>, <16 x i1>, i32)
1184
1185define <16 x i64> @vsll_vv_v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 zeroext %evl) {
1186; CHECK-LABEL: vsll_vv_v16i64:
1187; CHECK:       # %bb.0:
1188; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, mu
1189; CHECK-NEXT:    vsll.vv v8, v8, v16, v0.t
1190; CHECK-NEXT:    ret
1191  %v = call <16 x i64> @llvm.vp.shl.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl)
1192  ret <16 x i64> %v
1193}
1194
1195define <16 x i64> @vsll_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 zeroext %evl) {
1196; CHECK-LABEL: vsll_vv_v16i64_unmasked:
1197; CHECK:       # %bb.0:
1198; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, mu
1199; CHECK-NEXT:    vsll.vv v8, v8, v16
1200; CHECK-NEXT:    ret
1201  %head = insertelement <16 x i1> undef, i1 true, i32 0
1202  %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer
1203  %v = call <16 x i64> @llvm.vp.shl.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl)
1204  ret <16 x i64> %v
1205}
1206
1207define <16 x i64> @vsll_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {
1208; RV32-LABEL: vsll_vx_v16i64:
1209; RV32:       # %bb.0:
1210; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
1211; RV32-NEXT:    vsll.vx v8, v8, a0, v0.t
1212; RV32-NEXT:    ret
1213;
1214; RV64-LABEL: vsll_vx_v16i64:
1215; RV64:       # %bb.0:
1216; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, mu
1217; RV64-NEXT:    vsll.vx v8, v8, a0, v0.t
1218; RV64-NEXT:    ret
1219  %elt.head = insertelement <16 x i64> undef, i64 %b, i32 0
1220  %vb = shufflevector <16 x i64> %elt.head, <16 x i64> undef, <16 x i32> zeroinitializer
1221  %v = call <16 x i64> @llvm.vp.shl.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)
1222  ret <16 x i64> %v
1223}
1224
1225define <16 x i64> @vsll_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {
1226; RV32-LABEL: vsll_vx_v16i64_unmasked:
1227; RV32:       # %bb.0:
1228; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
1229; RV32-NEXT:    vsll.vx v8, v8, a0
1230; RV32-NEXT:    ret
1231;
1232; RV64-LABEL: vsll_vx_v16i64_unmasked:
1233; RV64:       # %bb.0:
1234; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, mu
1235; RV64-NEXT:    vsll.vx v8, v8, a0
1236; RV64-NEXT:    ret
1237  %elt.head = insertelement <16 x i64> undef, i64 %b, i32 0
1238  %vb = shufflevector <16 x i64> %elt.head, <16 x i64> undef, <16 x i32> zeroinitializer
1239  %head = insertelement <16 x i1> undef, i1 true, i32 0
1240  %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer
1241  %v = call <16 x i64> @llvm.vp.shl.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)
1242  ret <16 x i64> %v
1243}
1244
1245define <16 x i64> @vsll_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {
1246; CHECK-LABEL: vsll_vi_v16i64:
1247; CHECK:       # %bb.0:
1248; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, mu
1249; CHECK-NEXT:    vsll.vi v8, v8, 3, v0.t
1250; CHECK-NEXT:    ret
1251  %elt.head = insertelement <16 x i64> undef, i64 3, i32 0
1252  %vb = shufflevector <16 x i64> %elt.head, <16 x i64> undef, <16 x i32> zeroinitializer
1253  %v = call <16 x i64> @llvm.vp.shl.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)
1254  ret <16 x i64> %v
1255}
1256
1257define <16 x i64> @vsll_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
1258; CHECK-LABEL: vsll_vi_v16i64_unmasked:
1259; CHECK:       # %bb.0:
1260; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, mu
1261; CHECK-NEXT:    vsll.vi v8, v8, 3
1262; CHECK-NEXT:    ret
1263  %elt.head = insertelement <16 x i64> undef, i64 3, i32 0
1264  %vb = shufflevector <16 x i64> %elt.head, <16 x i64> undef, <16 x i32> zeroinitializer
1265  %head = insertelement <16 x i1> undef, i1 true, i32 0
1266  %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer
1267  %v = call <16 x i64> @llvm.vp.shl.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)
1268  ret <16 x i64> %v
1269}
1270