1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -mattr=+m -O0 < %s \
3; RUN:    | FileCheck --check-prefix=SPILL-O0 %s
4; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -mattr=+m -O2 < %s \
5; RUN:    | FileCheck --check-prefix=SPILL-O2 %s
6
7define <vscale x 1 x i32> @spill_zvlsseg_nxv1i32(i32* %base, i64 %vl) nounwind {
8; SPILL-O0-LABEL: spill_zvlsseg_nxv1i32:
9; SPILL-O0:       # %bb.0: # %entry
10; SPILL-O0-NEXT:    addi sp, sp, -16
11; SPILL-O0-NEXT:    csrr a2, vlenb
12; SPILL-O0-NEXT:    sub sp, sp, a2
13; SPILL-O0-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu
14; SPILL-O0-NEXT:    vlseg2e32.v v0, (a0)
15; SPILL-O0-NEXT:    vmv1r.v v25, v1
16; SPILL-O0-NEXT:    addi a0, sp, 16
17; SPILL-O0-NEXT:    vs1r.v v25, (a0) # Unknown-size Folded Spill
18; SPILL-O0-NEXT:    #APP
19; SPILL-O0-NEXT:    #NO_APP
20; SPILL-O0-NEXT:    addi a0, sp, 16
21; SPILL-O0-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
22; SPILL-O0-NEXT:    csrr a0, vlenb
23; SPILL-O0-NEXT:    add sp, sp, a0
24; SPILL-O0-NEXT:    addi sp, sp, 16
25; SPILL-O0-NEXT:    ret
26;
27; SPILL-O2-LABEL: spill_zvlsseg_nxv1i32:
28; SPILL-O2:       # %bb.0: # %entry
29; SPILL-O2-NEXT:    addi sp, sp, -16
30; SPILL-O2-NEXT:    csrr a2, vlenb
31; SPILL-O2-NEXT:    slli a2, a2, 1
32; SPILL-O2-NEXT:    sub sp, sp, a2
33; SPILL-O2-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu
34; SPILL-O2-NEXT:    vlseg2e32.v v0, (a0)
35; SPILL-O2-NEXT:    addi a0, sp, 16
36; SPILL-O2-NEXT:    csrr a1, vlenb
37; SPILL-O2-NEXT:    vs1r.v v0, (a0) # Unknown-size Folded Spill
38; SPILL-O2-NEXT:    add a0, a0, a1
39; SPILL-O2-NEXT:    vs1r.v v1, (a0) # Unknown-size Folded Spill
40; SPILL-O2-NEXT:    #APP
41; SPILL-O2-NEXT:    #NO_APP
42; SPILL-O2-NEXT:    addi a0, sp, 16
43; SPILL-O2-NEXT:    csrr a1, vlenb
44; SPILL-O2-NEXT:    vl1r.v v7, (a0) # Unknown-size Folded Reload
45; SPILL-O2-NEXT:    add a0, a0, a1
46; SPILL-O2-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
47; SPILL-O2-NEXT:    # kill: def $v8 killed $v8 killed $v7_v8
48; SPILL-O2-NEXT:    csrr a0, vlenb
49; SPILL-O2-NEXT:    slli a0, a0, 1
50; SPILL-O2-NEXT:    add sp, sp, a0
51; SPILL-O2-NEXT:    addi sp, sp, 16
52; SPILL-O2-NEXT:    ret
53entry:
54  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.nxv1i32(i32* %base, i64 %vl)
55  call void asm sideeffect "",
56  "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
57  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
58  ret <vscale x 1 x i32> %1
59}
60
61define <vscale x 2 x i32> @spill_zvlsseg_nxv2i32(i32* %base, i64 %vl) nounwind {
62; SPILL-O0-LABEL: spill_zvlsseg_nxv2i32:
63; SPILL-O0:       # %bb.0: # %entry
64; SPILL-O0-NEXT:    addi sp, sp, -16
65; SPILL-O0-NEXT:    csrr a2, vlenb
66; SPILL-O0-NEXT:    sub sp, sp, a2
67; SPILL-O0-NEXT:    vsetvli zero, a1, e32, m1, ta, mu
68; SPILL-O0-NEXT:    vlseg2e32.v v0, (a0)
69; SPILL-O0-NEXT:    vmv1r.v v25, v1
70; SPILL-O0-NEXT:    addi a0, sp, 16
71; SPILL-O0-NEXT:    vs1r.v v25, (a0) # Unknown-size Folded Spill
72; SPILL-O0-NEXT:    #APP
73; SPILL-O0-NEXT:    #NO_APP
74; SPILL-O0-NEXT:    addi a0, sp, 16
75; SPILL-O0-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
76; SPILL-O0-NEXT:    csrr a0, vlenb
77; SPILL-O0-NEXT:    add sp, sp, a0
78; SPILL-O0-NEXT:    addi sp, sp, 16
79; SPILL-O0-NEXT:    ret
80;
81; SPILL-O2-LABEL: spill_zvlsseg_nxv2i32:
82; SPILL-O2:       # %bb.0: # %entry
83; SPILL-O2-NEXT:    addi sp, sp, -16
84; SPILL-O2-NEXT:    csrr a2, vlenb
85; SPILL-O2-NEXT:    slli a2, a2, 1
86; SPILL-O2-NEXT:    sub sp, sp, a2
87; SPILL-O2-NEXT:    vsetvli zero, a1, e32, m1, ta, mu
88; SPILL-O2-NEXT:    vlseg2e32.v v0, (a0)
89; SPILL-O2-NEXT:    addi a0, sp, 16
90; SPILL-O2-NEXT:    csrr a1, vlenb
91; SPILL-O2-NEXT:    vs1r.v v0, (a0) # Unknown-size Folded Spill
92; SPILL-O2-NEXT:    add a0, a0, a1
93; SPILL-O2-NEXT:    vs1r.v v1, (a0) # Unknown-size Folded Spill
94; SPILL-O2-NEXT:    #APP
95; SPILL-O2-NEXT:    #NO_APP
96; SPILL-O2-NEXT:    addi a0, sp, 16
97; SPILL-O2-NEXT:    csrr a1, vlenb
98; SPILL-O2-NEXT:    vl1r.v v7, (a0) # Unknown-size Folded Reload
99; SPILL-O2-NEXT:    add a0, a0, a1
100; SPILL-O2-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
101; SPILL-O2-NEXT:    # kill: def $v8 killed $v8 killed $v7_v8
102; SPILL-O2-NEXT:    csrr a0, vlenb
103; SPILL-O2-NEXT:    slli a0, a0, 1
104; SPILL-O2-NEXT:    add sp, sp, a0
105; SPILL-O2-NEXT:    addi sp, sp, 16
106; SPILL-O2-NEXT:    ret
107entry:
108  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg2.nxv2i32(i32* %base, i64 %vl)
109  call void asm sideeffect "",
110  "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
111  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
112  ret <vscale x 2 x i32> %1
113}
114
115define <vscale x 4 x i32> @spill_zvlsseg_nxv4i32(i32* %base, i64 %vl) nounwind {
116; SPILL-O0-LABEL: spill_zvlsseg_nxv4i32:
117; SPILL-O0:       # %bb.0: # %entry
118; SPILL-O0-NEXT:    addi sp, sp, -16
119; SPILL-O0-NEXT:    csrr a2, vlenb
120; SPILL-O0-NEXT:    slli a2, a2, 1
121; SPILL-O0-NEXT:    sub sp, sp, a2
122; SPILL-O0-NEXT:    vsetvli zero, a1, e32, m2, ta, mu
123; SPILL-O0-NEXT:    vlseg2e32.v v0, (a0)
124; SPILL-O0-NEXT:    vmv2r.v v26, v2
125; SPILL-O0-NEXT:    addi a0, sp, 16
126; SPILL-O0-NEXT:    vs2r.v v26, (a0) # Unknown-size Folded Spill
127; SPILL-O0-NEXT:    #APP
128; SPILL-O0-NEXT:    #NO_APP
129; SPILL-O0-NEXT:    addi a0, sp, 16
130; SPILL-O0-NEXT:    vl2re8.v v8, (a0) # Unknown-size Folded Reload
131; SPILL-O0-NEXT:    csrr a0, vlenb
132; SPILL-O0-NEXT:    slli a0, a0, 1
133; SPILL-O0-NEXT:    add sp, sp, a0
134; SPILL-O0-NEXT:    addi sp, sp, 16
135; SPILL-O0-NEXT:    ret
136;
137; SPILL-O2-LABEL: spill_zvlsseg_nxv4i32:
138; SPILL-O2:       # %bb.0: # %entry
139; SPILL-O2-NEXT:    addi sp, sp, -16
140; SPILL-O2-NEXT:    csrr a2, vlenb
141; SPILL-O2-NEXT:    slli a2, a2, 2
142; SPILL-O2-NEXT:    sub sp, sp, a2
143; SPILL-O2-NEXT:    vsetvli zero, a1, e32, m2, ta, mu
144; SPILL-O2-NEXT:    vlseg2e32.v v0, (a0)
145; SPILL-O2-NEXT:    addi a0, sp, 16
146; SPILL-O2-NEXT:    csrr a1, vlenb
147; SPILL-O2-NEXT:    slli a1, a1, 1
148; SPILL-O2-NEXT:    vs2r.v v0, (a0) # Unknown-size Folded Spill
149; SPILL-O2-NEXT:    add a0, a0, a1
150; SPILL-O2-NEXT:    vs2r.v v2, (a0) # Unknown-size Folded Spill
151; SPILL-O2-NEXT:    #APP
152; SPILL-O2-NEXT:    #NO_APP
153; SPILL-O2-NEXT:    addi a0, sp, 16
154; SPILL-O2-NEXT:    csrr a1, vlenb
155; SPILL-O2-NEXT:    slli a1, a1, 1
156; SPILL-O2-NEXT:    vl2r.v v6, (a0) # Unknown-size Folded Reload
157; SPILL-O2-NEXT:    add a0, a0, a1
158; SPILL-O2-NEXT:    vl2r.v v8, (a0) # Unknown-size Folded Reload
159; SPILL-O2-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
160; SPILL-O2-NEXT:    csrr a0, vlenb
161; SPILL-O2-NEXT:    slli a0, a0, 2
162; SPILL-O2-NEXT:    add sp, sp, a0
163; SPILL-O2-NEXT:    addi sp, sp, 16
164; SPILL-O2-NEXT:    ret
165entry:
166  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg2.nxv4i32(i32* %base, i64 %vl)
167  call void asm sideeffect "",
168  "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
169  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
170  ret <vscale x 4 x i32> %1
171}
172
173define <vscale x 8 x i32> @spill_zvlsseg_nxv8i32(i32* %base, i64 %vl) nounwind {
174; SPILL-O0-LABEL: spill_zvlsseg_nxv8i32:
175; SPILL-O0:       # %bb.0: # %entry
176; SPILL-O0-NEXT:    addi sp, sp, -16
177; SPILL-O0-NEXT:    csrr a2, vlenb
178; SPILL-O0-NEXT:    slli a2, a2, 2
179; SPILL-O0-NEXT:    sub sp, sp, a2
180; SPILL-O0-NEXT:    vsetvli zero, a1, e32, m4, ta, mu
181; SPILL-O0-NEXT:    vlseg2e32.v v0, (a0)
182; SPILL-O0-NEXT:    vmv4r.v v28, v4
183; SPILL-O0-NEXT:    addi a0, sp, 16
184; SPILL-O0-NEXT:    vs4r.v v28, (a0) # Unknown-size Folded Spill
185; SPILL-O0-NEXT:    #APP
186; SPILL-O0-NEXT:    #NO_APP
187; SPILL-O0-NEXT:    addi a0, sp, 16
188; SPILL-O0-NEXT:    vl4re8.v v8, (a0) # Unknown-size Folded Reload
189; SPILL-O0-NEXT:    csrr a0, vlenb
190; SPILL-O0-NEXT:    slli a0, a0, 2
191; SPILL-O0-NEXT:    add sp, sp, a0
192; SPILL-O0-NEXT:    addi sp, sp, 16
193; SPILL-O0-NEXT:    ret
194;
195; SPILL-O2-LABEL: spill_zvlsseg_nxv8i32:
196; SPILL-O2:       # %bb.0: # %entry
197; SPILL-O2-NEXT:    addi sp, sp, -16
198; SPILL-O2-NEXT:    csrr a2, vlenb
199; SPILL-O2-NEXT:    slli a2, a2, 3
200; SPILL-O2-NEXT:    sub sp, sp, a2
201; SPILL-O2-NEXT:    vsetvli zero, a1, e32, m4, ta, mu
202; SPILL-O2-NEXT:    vlseg2e32.v v0, (a0)
203; SPILL-O2-NEXT:    addi a0, sp, 16
204; SPILL-O2-NEXT:    csrr a1, vlenb
205; SPILL-O2-NEXT:    slli a1, a1, 2
206; SPILL-O2-NEXT:    vs4r.v v0, (a0) # Unknown-size Folded Spill
207; SPILL-O2-NEXT:    add a0, a0, a1
208; SPILL-O2-NEXT:    vs4r.v v4, (a0) # Unknown-size Folded Spill
209; SPILL-O2-NEXT:    #APP
210; SPILL-O2-NEXT:    #NO_APP
211; SPILL-O2-NEXT:    addi a0, sp, 16
212; SPILL-O2-NEXT:    csrr a1, vlenb
213; SPILL-O2-NEXT:    slli a1, a1, 2
214; SPILL-O2-NEXT:    vl4r.v v4, (a0) # Unknown-size Folded Reload
215; SPILL-O2-NEXT:    add a0, a0, a1
216; SPILL-O2-NEXT:    vl4r.v v8, (a0) # Unknown-size Folded Reload
217; SPILL-O2-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
218; SPILL-O2-NEXT:    csrr a0, vlenb
219; SPILL-O2-NEXT:    slli a0, a0, 3
220; SPILL-O2-NEXT:    add sp, sp, a0
221; SPILL-O2-NEXT:    addi sp, sp, 16
222; SPILL-O2-NEXT:    ret
223entry:
224  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlseg2.nxv8i32(i32* %base, i64 %vl)
225  call void asm sideeffect "",
226  "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
227  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 1
228  ret <vscale x 8 x i32> %1
229}
230
231define <vscale x 4 x i32> @spill_zvlsseg3_nxv4i32(i32* %base, i64 %vl) nounwind {
232; SPILL-O0-LABEL: spill_zvlsseg3_nxv4i32:
233; SPILL-O0:       # %bb.0: # %entry
234; SPILL-O0-NEXT:    addi sp, sp, -16
235; SPILL-O0-NEXT:    csrr a2, vlenb
236; SPILL-O0-NEXT:    slli a2, a2, 1
237; SPILL-O0-NEXT:    sub sp, sp, a2
238; SPILL-O0-NEXT:    vsetvli zero, a1, e32, m2, ta, mu
239; SPILL-O0-NEXT:    vlseg3e32.v v0, (a0)
240; SPILL-O0-NEXT:    vmv2r.v v26, v2
241; SPILL-O0-NEXT:    addi a0, sp, 16
242; SPILL-O0-NEXT:    vs2r.v v26, (a0) # Unknown-size Folded Spill
243; SPILL-O0-NEXT:    #APP
244; SPILL-O0-NEXT:    #NO_APP
245; SPILL-O0-NEXT:    addi a0, sp, 16
246; SPILL-O0-NEXT:    vl2re8.v v8, (a0) # Unknown-size Folded Reload
247; SPILL-O0-NEXT:    csrr a0, vlenb
248; SPILL-O0-NEXT:    slli a0, a0, 1
249; SPILL-O0-NEXT:    add sp, sp, a0
250; SPILL-O0-NEXT:    addi sp, sp, 16
251; SPILL-O0-NEXT:    ret
252;
253; SPILL-O2-LABEL: spill_zvlsseg3_nxv4i32:
254; SPILL-O2:       # %bb.0: # %entry
255; SPILL-O2-NEXT:    addi sp, sp, -16
256; SPILL-O2-NEXT:    csrr a2, vlenb
257; SPILL-O2-NEXT:    addi a3, zero, 6
258; SPILL-O2-NEXT:    mul a2, a2, a3
259; SPILL-O2-NEXT:    sub sp, sp, a2
260; SPILL-O2-NEXT:    vsetvli zero, a1, e32, m2, ta, mu
261; SPILL-O2-NEXT:    vlseg3e32.v v0, (a0)
262; SPILL-O2-NEXT:    addi a0, sp, 16
263; SPILL-O2-NEXT:    csrr a1, vlenb
264; SPILL-O2-NEXT:    slli a1, a1, 1
265; SPILL-O2-NEXT:    vs2r.v v0, (a0) # Unknown-size Folded Spill
266; SPILL-O2-NEXT:    add a0, a0, a1
267; SPILL-O2-NEXT:    vs2r.v v2, (a0) # Unknown-size Folded Spill
268; SPILL-O2-NEXT:    add a0, a0, a1
269; SPILL-O2-NEXT:    vs2r.v v4, (a0) # Unknown-size Folded Spill
270; SPILL-O2-NEXT:    #APP
271; SPILL-O2-NEXT:    #NO_APP
272; SPILL-O2-NEXT:    addi a0, sp, 16
273; SPILL-O2-NEXT:    csrr a1, vlenb
274; SPILL-O2-NEXT:    slli a1, a1, 1
275; SPILL-O2-NEXT:    vl2r.v v6, (a0) # Unknown-size Folded Reload
276; SPILL-O2-NEXT:    add a0, a0, a1
277; SPILL-O2-NEXT:    vl2r.v v8, (a0) # Unknown-size Folded Reload
278; SPILL-O2-NEXT:    add a0, a0, a1
279; SPILL-O2-NEXT:    vl2r.v v10, (a0) # Unknown-size Folded Reload
280; SPILL-O2-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
281; SPILL-O2-NEXT:    csrr a0, vlenb
282; SPILL-O2-NEXT:    addi a1, zero, 6
283; SPILL-O2-NEXT:    mul a0, a0, a1
284; SPILL-O2-NEXT:    add sp, sp, a0
285; SPILL-O2-NEXT:    addi sp, sp, 16
286; SPILL-O2-NEXT:    ret
287entry:
288  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg3.nxv4i32(i32* %base, i64 %vl)
289  call void asm sideeffect "",
290  "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
291  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
292  ret <vscale x 4 x i32> %1
293}
294
295declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.nxv1i32(i32* , i64)
296declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg2.nxv2i32(i32* , i64)
297declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg2.nxv4i32(i32* , i64)
298declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlseg2.nxv8i32(i32* , i64)
299declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg3.nxv4i32(i32* , i64)
300