1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
3; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
4
5define <vscale x 1 x i1> @vselect_nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, <vscale x 1 x i1> %cc) {
6; CHECK-LABEL: vselect_nxv1i1:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
9; CHECK-NEXT:    vmandnot.mm v25, v8, v9
10; CHECK-NEXT:    vmand.mm v26, v0, v9
11; CHECK-NEXT:    vmor.mm v0, v26, v25
12; CHECK-NEXT:    ret
13  %v = select <vscale x 1 x i1> %cc, <vscale x 1 x i1> %a, <vscale x 1 x i1> %b
14  ret <vscale x 1 x i1> %v
15}
16
17define <vscale x 2 x i1> @vselect_nxv2i1(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b, <vscale x 2 x i1> %cc) {
18; CHECK-LABEL: vselect_nxv2i1:
19; CHECK:       # %bb.0:
20; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
21; CHECK-NEXT:    vmandnot.mm v25, v8, v9
22; CHECK-NEXT:    vmand.mm v26, v0, v9
23; CHECK-NEXT:    vmor.mm v0, v26, v25
24; CHECK-NEXT:    ret
25  %v = select <vscale x 2 x i1> %cc, <vscale x 2 x i1> %a, <vscale x 2 x i1> %b
26  ret <vscale x 2 x i1> %v
27}
28
29define <vscale x 4 x i1> @vselect_nxv4i1(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b, <vscale x 4 x i1> %cc) {
30; CHECK-LABEL: vselect_nxv4i1:
31; CHECK:       # %bb.0:
32; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
33; CHECK-NEXT:    vmandnot.mm v25, v8, v9
34; CHECK-NEXT:    vmand.mm v26, v0, v9
35; CHECK-NEXT:    vmor.mm v0, v26, v25
36; CHECK-NEXT:    ret
37  %v = select <vscale x 4 x i1> %cc, <vscale x 4 x i1> %a, <vscale x 4 x i1> %b
38  ret <vscale x 4 x i1> %v
39}
40
41define <vscale x 8 x i1> @vselect_nxv8i1(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b, <vscale x 8 x i1> %cc) {
42; CHECK-LABEL: vselect_nxv8i1:
43; CHECK:       # %bb.0:
44; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
45; CHECK-NEXT:    vmandnot.mm v25, v8, v9
46; CHECK-NEXT:    vmand.mm v26, v0, v9
47; CHECK-NEXT:    vmor.mm v0, v26, v25
48; CHECK-NEXT:    ret
49  %v = select <vscale x 8 x i1> %cc, <vscale x 8 x i1> %a, <vscale x 8 x i1> %b
50  ret <vscale x 8 x i1> %v
51}
52
53define <vscale x 16 x i1> @vselect_nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, <vscale x 16 x i1> %cc) {
54; CHECK-LABEL: vselect_nxv16i1:
55; CHECK:       # %bb.0:
56; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
57; CHECK-NEXT:    vmandnot.mm v25, v8, v9
58; CHECK-NEXT:    vmand.mm v26, v0, v9
59; CHECK-NEXT:    vmor.mm v0, v26, v25
60; CHECK-NEXT:    ret
61  %v = select <vscale x 16 x i1> %cc, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b
62  ret <vscale x 16 x i1> %v
63}
64
65define <vscale x 32 x i1> @vselect_nxv32i1(<vscale x 32 x i1> %a, <vscale x 32 x i1> %b, <vscale x 32 x i1> %cc) {
66; CHECK-LABEL: vselect_nxv32i1:
67; CHECK:       # %bb.0:
68; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, mu
69; CHECK-NEXT:    vmandnot.mm v25, v8, v9
70; CHECK-NEXT:    vmand.mm v26, v0, v9
71; CHECK-NEXT:    vmor.mm v0, v26, v25
72; CHECK-NEXT:    ret
73  %v = select <vscale x 32 x i1> %cc, <vscale x 32 x i1> %a, <vscale x 32 x i1> %b
74  ret <vscale x 32 x i1> %v
75}
76
77define <vscale x 64 x i1> @vselect_nxv64i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b, <vscale x 64 x i1> %cc) {
78; CHECK-LABEL: vselect_nxv64i1:
79; CHECK:       # %bb.0:
80; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, mu
81; CHECK-NEXT:    vmandnot.mm v25, v8, v9
82; CHECK-NEXT:    vmand.mm v26, v0, v9
83; CHECK-NEXT:    vmor.mm v0, v26, v25
84; CHECK-NEXT:    ret
85  %v = select <vscale x 64 x i1> %cc, <vscale x 64 x i1> %a, <vscale x 64 x i1> %b
86  ret <vscale x 64 x i1> %v
87}
88