1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
3
4define <vscale x 1 x i8> @vxor_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
5; CHECK-LABEL: vxor_vv_nxv1i8:
6; CHECK:       # %bb.0:
7; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
8; CHECK-NEXT:    vxor.vv v8, v8, v9
9; CHECK-NEXT:    ret
10  %vc = xor <vscale x 1 x i8> %va, %vb
11  ret <vscale x 1 x i8> %vc
12}
13
14define <vscale x 1 x i8> @vxor_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
15; CHECK-LABEL: vxor_vx_nxv1i8:
16; CHECK:       # %bb.0:
17; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
18; CHECK-NEXT:    vxor.vx v8, v8, a0
19; CHECK-NEXT:    ret
20  %head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
21  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
22  %vc = xor <vscale x 1 x i8> %va, %splat
23  ret <vscale x 1 x i8> %vc
24}
25
26define <vscale x 1 x i8> @vxor_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
27; CHECK-LABEL: vxor_vi_nxv1i8_0:
28; CHECK:       # %bb.0:
29; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
30; CHECK-NEXT:    vxor.vi v8, v8, -1
31; CHECK-NEXT:    ret
32  %head = insertelement <vscale x 1 x i8> undef, i8 -1, i32 0
33  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
34  %vc = xor <vscale x 1 x i8> %va, %splat
35  ret <vscale x 1 x i8> %vc
36}
37
38define <vscale x 1 x i8> @vxor_vi_nxv1i8_1(<vscale x 1 x i8> %va) {
39; CHECK-LABEL: vxor_vi_nxv1i8_1:
40; CHECK:       # %bb.0:
41; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
42; CHECK-NEXT:    vxor.vi v8, v8, 8
43; CHECK-NEXT:    ret
44  %head = insertelement <vscale x 1 x i8> undef, i8 8, i32 0
45  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
46  %vc = xor <vscale x 1 x i8> %va, %splat
47  ret <vscale x 1 x i8> %vc
48}
49
50define <vscale x 1 x i8> @vxor_vi_nxv1i8_2(<vscale x 1 x i8> %va) {
51; CHECK-LABEL: vxor_vi_nxv1i8_2:
52; CHECK:       # %bb.0:
53; CHECK-NEXT:    addi a0, zero, 16
54; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
55; CHECK-NEXT:    vxor.vx v8, v8, a0
56; CHECK-NEXT:    ret
57  %head = insertelement <vscale x 1 x i8> undef, i8 16, i32 0
58  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
59  %vc = xor <vscale x 1 x i8> %va, %splat
60  ret <vscale x 1 x i8> %vc
61}
62
63define <vscale x 2 x i8> @vxor_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
64; CHECK-LABEL: vxor_vv_nxv2i8:
65; CHECK:       # %bb.0:
66; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
67; CHECK-NEXT:    vxor.vv v8, v8, v9
68; CHECK-NEXT:    ret
69  %vc = xor <vscale x 2 x i8> %va, %vb
70  ret <vscale x 2 x i8> %vc
71}
72
73define <vscale x 2 x i8> @vxor_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
74; CHECK-LABEL: vxor_vx_nxv2i8:
75; CHECK:       # %bb.0:
76; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
77; CHECK-NEXT:    vxor.vx v8, v8, a0
78; CHECK-NEXT:    ret
79  %head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
80  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
81  %vc = xor <vscale x 2 x i8> %va, %splat
82  ret <vscale x 2 x i8> %vc
83}
84
85define <vscale x 2 x i8> @vxor_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
86; CHECK-LABEL: vxor_vi_nxv2i8_0:
87; CHECK:       # %bb.0:
88; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
89; CHECK-NEXT:    vxor.vi v8, v8, -1
90; CHECK-NEXT:    ret
91  %head = insertelement <vscale x 2 x i8> undef, i8 -1, i32 0
92  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
93  %vc = xor <vscale x 2 x i8> %va, %splat
94  ret <vscale x 2 x i8> %vc
95}
96
97define <vscale x 2 x i8> @vxor_vi_nxv2i8_1(<vscale x 2 x i8> %va) {
98; CHECK-LABEL: vxor_vi_nxv2i8_1:
99; CHECK:       # %bb.0:
100; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
101; CHECK-NEXT:    vxor.vi v8, v8, 8
102; CHECK-NEXT:    ret
103  %head = insertelement <vscale x 2 x i8> undef, i8 8, i32 0
104  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
105  %vc = xor <vscale x 2 x i8> %va, %splat
106  ret <vscale x 2 x i8> %vc
107}
108
109define <vscale x 2 x i8> @vxor_vi_nxv2i8_2(<vscale x 2 x i8> %va) {
110; CHECK-LABEL: vxor_vi_nxv2i8_2:
111; CHECK:       # %bb.0:
112; CHECK-NEXT:    addi a0, zero, 16
113; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
114; CHECK-NEXT:    vxor.vx v8, v8, a0
115; CHECK-NEXT:    ret
116  %head = insertelement <vscale x 2 x i8> undef, i8 16, i32 0
117  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
118  %vc = xor <vscale x 2 x i8> %va, %splat
119  ret <vscale x 2 x i8> %vc
120}
121
122define <vscale x 4 x i8> @vxor_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
123; CHECK-LABEL: vxor_vv_nxv4i8:
124; CHECK:       # %bb.0:
125; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
126; CHECK-NEXT:    vxor.vv v8, v8, v9
127; CHECK-NEXT:    ret
128  %vc = xor <vscale x 4 x i8> %va, %vb
129  ret <vscale x 4 x i8> %vc
130}
131
132define <vscale x 4 x i8> @vxor_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
133; CHECK-LABEL: vxor_vx_nxv4i8:
134; CHECK:       # %bb.0:
135; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
136; CHECK-NEXT:    vxor.vx v8, v8, a0
137; CHECK-NEXT:    ret
138  %head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
139  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
140  %vc = xor <vscale x 4 x i8> %va, %splat
141  ret <vscale x 4 x i8> %vc
142}
143
144define <vscale x 4 x i8> @vxor_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
145; CHECK-LABEL: vxor_vi_nxv4i8_0:
146; CHECK:       # %bb.0:
147; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
148; CHECK-NEXT:    vxor.vi v8, v8, -1
149; CHECK-NEXT:    ret
150  %head = insertelement <vscale x 4 x i8> undef, i8 -1, i32 0
151  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
152  %vc = xor <vscale x 4 x i8> %va, %splat
153  ret <vscale x 4 x i8> %vc
154}
155
156define <vscale x 4 x i8> @vxor_vi_nxv4i8_1(<vscale x 4 x i8> %va) {
157; CHECK-LABEL: vxor_vi_nxv4i8_1:
158; CHECK:       # %bb.0:
159; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
160; CHECK-NEXT:    vxor.vi v8, v8, 8
161; CHECK-NEXT:    ret
162  %head = insertelement <vscale x 4 x i8> undef, i8 8, i32 0
163  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
164  %vc = xor <vscale x 4 x i8> %va, %splat
165  ret <vscale x 4 x i8> %vc
166}
167
168define <vscale x 4 x i8> @vxor_vi_nxv4i8_2(<vscale x 4 x i8> %va) {
169; CHECK-LABEL: vxor_vi_nxv4i8_2:
170; CHECK:       # %bb.0:
171; CHECK-NEXT:    addi a0, zero, 16
172; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
173; CHECK-NEXT:    vxor.vx v8, v8, a0
174; CHECK-NEXT:    ret
175  %head = insertelement <vscale x 4 x i8> undef, i8 16, i32 0
176  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
177  %vc = xor <vscale x 4 x i8> %va, %splat
178  ret <vscale x 4 x i8> %vc
179}
180
181define <vscale x 8 x i8> @vxor_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
182; CHECK-LABEL: vxor_vv_nxv8i8:
183; CHECK:       # %bb.0:
184; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
185; CHECK-NEXT:    vxor.vv v8, v8, v9
186; CHECK-NEXT:    ret
187  %vc = xor <vscale x 8 x i8> %va, %vb
188  ret <vscale x 8 x i8> %vc
189}
190
191define <vscale x 8 x i8> @vxor_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
192; CHECK-LABEL: vxor_vx_nxv8i8:
193; CHECK:       # %bb.0:
194; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
195; CHECK-NEXT:    vxor.vx v8, v8, a0
196; CHECK-NEXT:    ret
197  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
198  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
199  %vc = xor <vscale x 8 x i8> %va, %splat
200  ret <vscale x 8 x i8> %vc
201}
202
203define <vscale x 8 x i8> @vxor_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
204; CHECK-LABEL: vxor_vi_nxv8i8_0:
205; CHECK:       # %bb.0:
206; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
207; CHECK-NEXT:    vxor.vi v8, v8, -1
208; CHECK-NEXT:    ret
209  %head = insertelement <vscale x 8 x i8> undef, i8 -1, i32 0
210  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
211  %vc = xor <vscale x 8 x i8> %va, %splat
212  ret <vscale x 8 x i8> %vc
213}
214
215define <vscale x 8 x i8> @vxor_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
216; CHECK-LABEL: vxor_vi_nxv8i8_1:
217; CHECK:       # %bb.0:
218; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
219; CHECK-NEXT:    vxor.vi v8, v8, 8
220; CHECK-NEXT:    ret
221  %head = insertelement <vscale x 8 x i8> undef, i8 8, i32 0
222  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
223  %vc = xor <vscale x 8 x i8> %va, %splat
224  ret <vscale x 8 x i8> %vc
225}
226
227define <vscale x 8 x i8> @vxor_vi_nxv8i8_2(<vscale x 8 x i8> %va) {
228; CHECK-LABEL: vxor_vi_nxv8i8_2:
229; CHECK:       # %bb.0:
230; CHECK-NEXT:    addi a0, zero, 16
231; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
232; CHECK-NEXT:    vxor.vx v8, v8, a0
233; CHECK-NEXT:    ret
234  %head = insertelement <vscale x 8 x i8> undef, i8 16, i32 0
235  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
236  %vc = xor <vscale x 8 x i8> %va, %splat
237  ret <vscale x 8 x i8> %vc
238}
239
240define <vscale x 16 x i8> @vxor_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
241; CHECK-LABEL: vxor_vv_nxv16i8:
242; CHECK:       # %bb.0:
243; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
244; CHECK-NEXT:    vxor.vv v8, v8, v10
245; CHECK-NEXT:    ret
246  %vc = xor <vscale x 16 x i8> %va, %vb
247  ret <vscale x 16 x i8> %vc
248}
249
250define <vscale x 16 x i8> @vxor_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
251; CHECK-LABEL: vxor_vx_nxv16i8:
252; CHECK:       # %bb.0:
253; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
254; CHECK-NEXT:    vxor.vx v8, v8, a0
255; CHECK-NEXT:    ret
256  %head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
257  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
258  %vc = xor <vscale x 16 x i8> %va, %splat
259  ret <vscale x 16 x i8> %vc
260}
261
262define <vscale x 16 x i8> @vxor_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
263; CHECK-LABEL: vxor_vi_nxv16i8_0:
264; CHECK:       # %bb.0:
265; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
266; CHECK-NEXT:    vxor.vi v8, v8, -1
267; CHECK-NEXT:    ret
268  %head = insertelement <vscale x 16 x i8> undef, i8 -1, i32 0
269  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
270  %vc = xor <vscale x 16 x i8> %va, %splat
271  ret <vscale x 16 x i8> %vc
272}
273
274define <vscale x 16 x i8> @vxor_vi_nxv16i8_1(<vscale x 16 x i8> %va) {
275; CHECK-LABEL: vxor_vi_nxv16i8_1:
276; CHECK:       # %bb.0:
277; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
278; CHECK-NEXT:    vxor.vi v8, v8, 8
279; CHECK-NEXT:    ret
280  %head = insertelement <vscale x 16 x i8> undef, i8 8, i32 0
281  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
282  %vc = xor <vscale x 16 x i8> %va, %splat
283  ret <vscale x 16 x i8> %vc
284}
285
286define <vscale x 16 x i8> @vxor_vi_nxv16i8_2(<vscale x 16 x i8> %va) {
287; CHECK-LABEL: vxor_vi_nxv16i8_2:
288; CHECK:       # %bb.0:
289; CHECK-NEXT:    addi a0, zero, 16
290; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
291; CHECK-NEXT:    vxor.vx v8, v8, a0
292; CHECK-NEXT:    ret
293  %head = insertelement <vscale x 16 x i8> undef, i8 16, i32 0
294  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
295  %vc = xor <vscale x 16 x i8> %va, %splat
296  ret <vscale x 16 x i8> %vc
297}
298
299define <vscale x 32 x i8> @vxor_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
300; CHECK-LABEL: vxor_vv_nxv32i8:
301; CHECK:       # %bb.0:
302; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, mu
303; CHECK-NEXT:    vxor.vv v8, v8, v12
304; CHECK-NEXT:    ret
305  %vc = xor <vscale x 32 x i8> %va, %vb
306  ret <vscale x 32 x i8> %vc
307}
308
309define <vscale x 32 x i8> @vxor_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
310; CHECK-LABEL: vxor_vx_nxv32i8:
311; CHECK:       # %bb.0:
312; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
313; CHECK-NEXT:    vxor.vx v8, v8, a0
314; CHECK-NEXT:    ret
315  %head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
316  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
317  %vc = xor <vscale x 32 x i8> %va, %splat
318  ret <vscale x 32 x i8> %vc
319}
320
321define <vscale x 32 x i8> @vxor_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
322; CHECK-LABEL: vxor_vi_nxv32i8_0:
323; CHECK:       # %bb.0:
324; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, mu
325; CHECK-NEXT:    vxor.vi v8, v8, -1
326; CHECK-NEXT:    ret
327  %head = insertelement <vscale x 32 x i8> undef, i8 -1, i32 0
328  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
329  %vc = xor <vscale x 32 x i8> %va, %splat
330  ret <vscale x 32 x i8> %vc
331}
332
333define <vscale x 32 x i8> @vxor_vi_nxv32i8_1(<vscale x 32 x i8> %va) {
334; CHECK-LABEL: vxor_vi_nxv32i8_1:
335; CHECK:       # %bb.0:
336; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, mu
337; CHECK-NEXT:    vxor.vi v8, v8, 8
338; CHECK-NEXT:    ret
339  %head = insertelement <vscale x 32 x i8> undef, i8 8, i32 0
340  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
341  %vc = xor <vscale x 32 x i8> %va, %splat
342  ret <vscale x 32 x i8> %vc
343}
344
345define <vscale x 32 x i8> @vxor_vi_nxv32i8_2(<vscale x 32 x i8> %va) {
346; CHECK-LABEL: vxor_vi_nxv32i8_2:
347; CHECK:       # %bb.0:
348; CHECK-NEXT:    addi a0, zero, 16
349; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
350; CHECK-NEXT:    vxor.vx v8, v8, a0
351; CHECK-NEXT:    ret
352  %head = insertelement <vscale x 32 x i8> undef, i8 16, i32 0
353  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
354  %vc = xor <vscale x 32 x i8> %va, %splat
355  ret <vscale x 32 x i8> %vc
356}
357
358define <vscale x 64 x i8> @vxor_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
359; CHECK-LABEL: vxor_vv_nxv64i8:
360; CHECK:       # %bb.0:
361; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, mu
362; CHECK-NEXT:    vxor.vv v8, v8, v16
363; CHECK-NEXT:    ret
364  %vc = xor <vscale x 64 x i8> %va, %vb
365  ret <vscale x 64 x i8> %vc
366}
367
368define <vscale x 64 x i8> @vxor_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
369; CHECK-LABEL: vxor_vx_nxv64i8:
370; CHECK:       # %bb.0:
371; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, mu
372; CHECK-NEXT:    vxor.vx v8, v8, a0
373; CHECK-NEXT:    ret
374  %head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
375  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
376  %vc = xor <vscale x 64 x i8> %va, %splat
377  ret <vscale x 64 x i8> %vc
378}
379
380define <vscale x 64 x i8> @vxor_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
381; CHECK-LABEL: vxor_vi_nxv64i8_0:
382; CHECK:       # %bb.0:
383; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, mu
384; CHECK-NEXT:    vxor.vi v8, v8, -1
385; CHECK-NEXT:    ret
386  %head = insertelement <vscale x 64 x i8> undef, i8 -1, i32 0
387  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
388  %vc = xor <vscale x 64 x i8> %va, %splat
389  ret <vscale x 64 x i8> %vc
390}
391
392define <vscale x 64 x i8> @vxor_vi_nxv64i8_1(<vscale x 64 x i8> %va) {
393; CHECK-LABEL: vxor_vi_nxv64i8_1:
394; CHECK:       # %bb.0:
395; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, mu
396; CHECK-NEXT:    vxor.vi v8, v8, 8
397; CHECK-NEXT:    ret
398  %head = insertelement <vscale x 64 x i8> undef, i8 8, i32 0
399  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
400  %vc = xor <vscale x 64 x i8> %va, %splat
401  ret <vscale x 64 x i8> %vc
402}
403
404define <vscale x 64 x i8> @vxor_vi_nxv64i8_2(<vscale x 64 x i8> %va) {
405; CHECK-LABEL: vxor_vi_nxv64i8_2:
406; CHECK:       # %bb.0:
407; CHECK-NEXT:    addi a0, zero, 16
408; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, mu
409; CHECK-NEXT:    vxor.vx v8, v8, a0
410; CHECK-NEXT:    ret
411  %head = insertelement <vscale x 64 x i8> undef, i8 16, i32 0
412  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
413  %vc = xor <vscale x 64 x i8> %va, %splat
414  ret <vscale x 64 x i8> %vc
415}
416
417define <vscale x 1 x i16> @vxor_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
418; CHECK-LABEL: vxor_vv_nxv1i16:
419; CHECK:       # %bb.0:
420; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
421; CHECK-NEXT:    vxor.vv v8, v8, v9
422; CHECK-NEXT:    ret
423  %vc = xor <vscale x 1 x i16> %va, %vb
424  ret <vscale x 1 x i16> %vc
425}
426
427define <vscale x 1 x i16> @vxor_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
428; CHECK-LABEL: vxor_vx_nxv1i16:
429; CHECK:       # %bb.0:
430; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
431; CHECK-NEXT:    vxor.vx v8, v8, a0
432; CHECK-NEXT:    ret
433  %head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
434  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
435  %vc = xor <vscale x 1 x i16> %va, %splat
436  ret <vscale x 1 x i16> %vc
437}
438
439define <vscale x 1 x i16> @vxor_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
440; CHECK-LABEL: vxor_vi_nxv1i16_0:
441; CHECK:       # %bb.0:
442; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
443; CHECK-NEXT:    vxor.vi v8, v8, -1
444; CHECK-NEXT:    ret
445  %head = insertelement <vscale x 1 x i16> undef, i16 -1, i32 0
446  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
447  %vc = xor <vscale x 1 x i16> %va, %splat
448  ret <vscale x 1 x i16> %vc
449}
450
451define <vscale x 1 x i16> @vxor_vi_nxv1i16_1(<vscale x 1 x i16> %va) {
452; CHECK-LABEL: vxor_vi_nxv1i16_1:
453; CHECK:       # %bb.0:
454; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
455; CHECK-NEXT:    vxor.vi v8, v8, 8
456; CHECK-NEXT:    ret
457  %head = insertelement <vscale x 1 x i16> undef, i16 8, i32 0
458  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
459  %vc = xor <vscale x 1 x i16> %va, %splat
460  ret <vscale x 1 x i16> %vc
461}
462
463define <vscale x 1 x i16> @vxor_vi_nxv1i16_2(<vscale x 1 x i16> %va) {
464; CHECK-LABEL: vxor_vi_nxv1i16_2:
465; CHECK:       # %bb.0:
466; CHECK-NEXT:    addi a0, zero, 16
467; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
468; CHECK-NEXT:    vxor.vx v8, v8, a0
469; CHECK-NEXT:    ret
470  %head = insertelement <vscale x 1 x i16> undef, i16 16, i32 0
471  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
472  %vc = xor <vscale x 1 x i16> %va, %splat
473  ret <vscale x 1 x i16> %vc
474}
475
476define <vscale x 2 x i16> @vxor_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
477; CHECK-LABEL: vxor_vv_nxv2i16:
478; CHECK:       # %bb.0:
479; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
480; CHECK-NEXT:    vxor.vv v8, v8, v9
481; CHECK-NEXT:    ret
482  %vc = xor <vscale x 2 x i16> %va, %vb
483  ret <vscale x 2 x i16> %vc
484}
485
486define <vscale x 2 x i16> @vxor_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
487; CHECK-LABEL: vxor_vx_nxv2i16:
488; CHECK:       # %bb.0:
489; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
490; CHECK-NEXT:    vxor.vx v8, v8, a0
491; CHECK-NEXT:    ret
492  %head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
493  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
494  %vc = xor <vscale x 2 x i16> %va, %splat
495  ret <vscale x 2 x i16> %vc
496}
497
498define <vscale x 2 x i16> @vxor_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
499; CHECK-LABEL: vxor_vi_nxv2i16_0:
500; CHECK:       # %bb.0:
501; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
502; CHECK-NEXT:    vxor.vi v8, v8, -1
503; CHECK-NEXT:    ret
504  %head = insertelement <vscale x 2 x i16> undef, i16 -1, i32 0
505  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
506  %vc = xor <vscale x 2 x i16> %va, %splat
507  ret <vscale x 2 x i16> %vc
508}
509
510define <vscale x 2 x i16> @vxor_vi_nxv2i16_1(<vscale x 2 x i16> %va) {
511; CHECK-LABEL: vxor_vi_nxv2i16_1:
512; CHECK:       # %bb.0:
513; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
514; CHECK-NEXT:    vxor.vi v8, v8, 8
515; CHECK-NEXT:    ret
516  %head = insertelement <vscale x 2 x i16> undef, i16 8, i32 0
517  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
518  %vc = xor <vscale x 2 x i16> %va, %splat
519  ret <vscale x 2 x i16> %vc
520}
521
522define <vscale x 2 x i16> @vxor_vi_nxv2i16_2(<vscale x 2 x i16> %va) {
523; CHECK-LABEL: vxor_vi_nxv2i16_2:
524; CHECK:       # %bb.0:
525; CHECK-NEXT:    addi a0, zero, 16
526; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
527; CHECK-NEXT:    vxor.vx v8, v8, a0
528; CHECK-NEXT:    ret
529  %head = insertelement <vscale x 2 x i16> undef, i16 16, i32 0
530  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
531  %vc = xor <vscale x 2 x i16> %va, %splat
532  ret <vscale x 2 x i16> %vc
533}
534
535define <vscale x 4 x i16> @vxor_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
536; CHECK-LABEL: vxor_vv_nxv4i16:
537; CHECK:       # %bb.0:
538; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
539; CHECK-NEXT:    vxor.vv v8, v8, v9
540; CHECK-NEXT:    ret
541  %vc = xor <vscale x 4 x i16> %va, %vb
542  ret <vscale x 4 x i16> %vc
543}
544
545define <vscale x 4 x i16> @vxor_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
546; CHECK-LABEL: vxor_vx_nxv4i16:
547; CHECK:       # %bb.0:
548; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
549; CHECK-NEXT:    vxor.vx v8, v8, a0
550; CHECK-NEXT:    ret
551  %head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
552  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
553  %vc = xor <vscale x 4 x i16> %va, %splat
554  ret <vscale x 4 x i16> %vc
555}
556
557define <vscale x 4 x i16> @vxor_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
558; CHECK-LABEL: vxor_vi_nxv4i16_0:
559; CHECK:       # %bb.0:
560; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
561; CHECK-NEXT:    vxor.vi v8, v8, -1
562; CHECK-NEXT:    ret
563  %head = insertelement <vscale x 4 x i16> undef, i16 -1, i32 0
564  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
565  %vc = xor <vscale x 4 x i16> %va, %splat
566  ret <vscale x 4 x i16> %vc
567}
568
569define <vscale x 4 x i16> @vxor_vi_nxv4i16_1(<vscale x 4 x i16> %va) {
570; CHECK-LABEL: vxor_vi_nxv4i16_1:
571; CHECK:       # %bb.0:
572; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
573; CHECK-NEXT:    vxor.vi v8, v8, 8
574; CHECK-NEXT:    ret
575  %head = insertelement <vscale x 4 x i16> undef, i16 8, i32 0
576  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
577  %vc = xor <vscale x 4 x i16> %va, %splat
578  ret <vscale x 4 x i16> %vc
579}
580
581define <vscale x 4 x i16> @vxor_vi_nxv4i16_2(<vscale x 4 x i16> %va) {
582; CHECK-LABEL: vxor_vi_nxv4i16_2:
583; CHECK:       # %bb.0:
584; CHECK-NEXT:    addi a0, zero, 16
585; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
586; CHECK-NEXT:    vxor.vx v8, v8, a0
587; CHECK-NEXT:    ret
588  %head = insertelement <vscale x 4 x i16> undef, i16 16, i32 0
589  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
590  %vc = xor <vscale x 4 x i16> %va, %splat
591  ret <vscale x 4 x i16> %vc
592}
593
594define <vscale x 8 x i16> @vxor_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
595; CHECK-LABEL: vxor_vv_nxv8i16:
596; CHECK:       # %bb.0:
597; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
598; CHECK-NEXT:    vxor.vv v8, v8, v10
599; CHECK-NEXT:    ret
600  %vc = xor <vscale x 8 x i16> %va, %vb
601  ret <vscale x 8 x i16> %vc
602}
603
604define <vscale x 8 x i16> @vxor_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
605; CHECK-LABEL: vxor_vx_nxv8i16:
606; CHECK:       # %bb.0:
607; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
608; CHECK-NEXT:    vxor.vx v8, v8, a0
609; CHECK-NEXT:    ret
610  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
611  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
612  %vc = xor <vscale x 8 x i16> %va, %splat
613  ret <vscale x 8 x i16> %vc
614}
615
616define <vscale x 8 x i16> @vxor_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
617; CHECK-LABEL: vxor_vi_nxv8i16_0:
618; CHECK:       # %bb.0:
619; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
620; CHECK-NEXT:    vxor.vi v8, v8, -1
621; CHECK-NEXT:    ret
622  %head = insertelement <vscale x 8 x i16> undef, i16 -1, i32 0
623  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
624  %vc = xor <vscale x 8 x i16> %va, %splat
625  ret <vscale x 8 x i16> %vc
626}
627
628define <vscale x 8 x i16> @vxor_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
629; CHECK-LABEL: vxor_vi_nxv8i16_1:
630; CHECK:       # %bb.0:
631; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
632; CHECK-NEXT:    vxor.vi v8, v8, 8
633; CHECK-NEXT:    ret
634  %head = insertelement <vscale x 8 x i16> undef, i16 8, i32 0
635  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
636  %vc = xor <vscale x 8 x i16> %va, %splat
637  ret <vscale x 8 x i16> %vc
638}
639
640define <vscale x 8 x i16> @vxor_vi_nxv8i16_2(<vscale x 8 x i16> %va) {
641; CHECK-LABEL: vxor_vi_nxv8i16_2:
642; CHECK:       # %bb.0:
643; CHECK-NEXT:    addi a0, zero, 16
644; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
645; CHECK-NEXT:    vxor.vx v8, v8, a0
646; CHECK-NEXT:    ret
647  %head = insertelement <vscale x 8 x i16> undef, i16 16, i32 0
648  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
649  %vc = xor <vscale x 8 x i16> %va, %splat
650  ret <vscale x 8 x i16> %vc
651}
652
653define <vscale x 16 x i16> @vxor_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
654; CHECK-LABEL: vxor_vv_nxv16i16:
655; CHECK:       # %bb.0:
656; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
657; CHECK-NEXT:    vxor.vv v8, v8, v12
658; CHECK-NEXT:    ret
659  %vc = xor <vscale x 16 x i16> %va, %vb
660  ret <vscale x 16 x i16> %vc
661}
662
663define <vscale x 16 x i16> @vxor_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
664; CHECK-LABEL: vxor_vx_nxv16i16:
665; CHECK:       # %bb.0:
666; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
667; CHECK-NEXT:    vxor.vx v8, v8, a0
668; CHECK-NEXT:    ret
669  %head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
670  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
671  %vc = xor <vscale x 16 x i16> %va, %splat
672  ret <vscale x 16 x i16> %vc
673}
674
675define <vscale x 16 x i16> @vxor_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
676; CHECK-LABEL: vxor_vi_nxv16i16_0:
677; CHECK:       # %bb.0:
678; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
679; CHECK-NEXT:    vxor.vi v8, v8, -1
680; CHECK-NEXT:    ret
681  %head = insertelement <vscale x 16 x i16> undef, i16 -1, i32 0
682  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
683  %vc = xor <vscale x 16 x i16> %va, %splat
684  ret <vscale x 16 x i16> %vc
685}
686
687define <vscale x 16 x i16> @vxor_vi_nxv16i16_1(<vscale x 16 x i16> %va) {
688; CHECK-LABEL: vxor_vi_nxv16i16_1:
689; CHECK:       # %bb.0:
690; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
691; CHECK-NEXT:    vxor.vi v8, v8, 8
692; CHECK-NEXT:    ret
693  %head = insertelement <vscale x 16 x i16> undef, i16 8, i32 0
694  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
695  %vc = xor <vscale x 16 x i16> %va, %splat
696  ret <vscale x 16 x i16> %vc
697}
698
699define <vscale x 16 x i16> @vxor_vi_nxv16i16_2(<vscale x 16 x i16> %va) {
700; CHECK-LABEL: vxor_vi_nxv16i16_2:
701; CHECK:       # %bb.0:
702; CHECK-NEXT:    addi a0, zero, 16
703; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
704; CHECK-NEXT:    vxor.vx v8, v8, a0
705; CHECK-NEXT:    ret
706  %head = insertelement <vscale x 16 x i16> undef, i16 16, i32 0
707  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
708  %vc = xor <vscale x 16 x i16> %va, %splat
709  ret <vscale x 16 x i16> %vc
710}
711
712define <vscale x 32 x i16> @vxor_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
713; CHECK-LABEL: vxor_vv_nxv32i16:
714; CHECK:       # %bb.0:
715; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
716; CHECK-NEXT:    vxor.vv v8, v8, v16
717; CHECK-NEXT:    ret
718  %vc = xor <vscale x 32 x i16> %va, %vb
719  ret <vscale x 32 x i16> %vc
720}
721
722define <vscale x 32 x i16> @vxor_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
723; CHECK-LABEL: vxor_vx_nxv32i16:
724; CHECK:       # %bb.0:
725; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
726; CHECK-NEXT:    vxor.vx v8, v8, a0
727; CHECK-NEXT:    ret
728  %head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
729  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
730  %vc = xor <vscale x 32 x i16> %va, %splat
731  ret <vscale x 32 x i16> %vc
732}
733
734define <vscale x 32 x i16> @vxor_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
735; CHECK-LABEL: vxor_vi_nxv32i16_0:
736; CHECK:       # %bb.0:
737; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
738; CHECK-NEXT:    vxor.vi v8, v8, -1
739; CHECK-NEXT:    ret
740  %head = insertelement <vscale x 32 x i16> undef, i16 -1, i32 0
741  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
742  %vc = xor <vscale x 32 x i16> %va, %splat
743  ret <vscale x 32 x i16> %vc
744}
745
746define <vscale x 32 x i16> @vxor_vi_nxv32i16_1(<vscale x 32 x i16> %va) {
747; CHECK-LABEL: vxor_vi_nxv32i16_1:
748; CHECK:       # %bb.0:
749; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
750; CHECK-NEXT:    vxor.vi v8, v8, 8
751; CHECK-NEXT:    ret
752  %head = insertelement <vscale x 32 x i16> undef, i16 8, i32 0
753  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
754  %vc = xor <vscale x 32 x i16> %va, %splat
755  ret <vscale x 32 x i16> %vc
756}
757
758define <vscale x 32 x i16> @vxor_vi_nxv32i16_2(<vscale x 32 x i16> %va) {
759; CHECK-LABEL: vxor_vi_nxv32i16_2:
760; CHECK:       # %bb.0:
761; CHECK-NEXT:    addi a0, zero, 16
762; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
763; CHECK-NEXT:    vxor.vx v8, v8, a0
764; CHECK-NEXT:    ret
765  %head = insertelement <vscale x 32 x i16> undef, i16 16, i32 0
766  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
767  %vc = xor <vscale x 32 x i16> %va, %splat
768  ret <vscale x 32 x i16> %vc
769}
770
771define <vscale x 1 x i32> @vxor_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
772; CHECK-LABEL: vxor_vv_nxv1i32:
773; CHECK:       # %bb.0:
774; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
775; CHECK-NEXT:    vxor.vv v8, v8, v9
776; CHECK-NEXT:    ret
777  %vc = xor <vscale x 1 x i32> %va, %vb
778  ret <vscale x 1 x i32> %vc
779}
780
781define <vscale x 1 x i32> @vxor_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {
782; CHECK-LABEL: vxor_vx_nxv1i32:
783; CHECK:       # %bb.0:
784; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
785; CHECK-NEXT:    vxor.vx v8, v8, a0
786; CHECK-NEXT:    ret
787  %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
788  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
789  %vc = xor <vscale x 1 x i32> %va, %splat
790  ret <vscale x 1 x i32> %vc
791}
792
793define <vscale x 1 x i32> @vxor_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
794; CHECK-LABEL: vxor_vi_nxv1i32_0:
795; CHECK:       # %bb.0:
796; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
797; CHECK-NEXT:    vxor.vi v8, v8, -1
798; CHECK-NEXT:    ret
799  %head = insertelement <vscale x 1 x i32> undef, i32 -1, i32 0
800  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
801  %vc = xor <vscale x 1 x i32> %va, %splat
802  ret <vscale x 1 x i32> %vc
803}
804
805define <vscale x 1 x i32> @vxor_vi_nxv1i32_1(<vscale x 1 x i32> %va) {
806; CHECK-LABEL: vxor_vi_nxv1i32_1:
807; CHECK:       # %bb.0:
808; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
809; CHECK-NEXT:    vxor.vi v8, v8, 8
810; CHECK-NEXT:    ret
811  %head = insertelement <vscale x 1 x i32> undef, i32 8, i32 0
812  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
813  %vc = xor <vscale x 1 x i32> %va, %splat
814  ret <vscale x 1 x i32> %vc
815}
816
817define <vscale x 1 x i32> @vxor_vi_nxv1i32_2(<vscale x 1 x i32> %va) {
818; CHECK-LABEL: vxor_vi_nxv1i32_2:
819; CHECK:       # %bb.0:
820; CHECK-NEXT:    addi a0, zero, 16
821; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
822; CHECK-NEXT:    vxor.vx v8, v8, a0
823; CHECK-NEXT:    ret
824  %head = insertelement <vscale x 1 x i32> undef, i32 16, i32 0
825  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
826  %vc = xor <vscale x 1 x i32> %va, %splat
827  ret <vscale x 1 x i32> %vc
828}
829
830define <vscale x 2 x i32> @vxor_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
831; CHECK-LABEL: vxor_vv_nxv2i32:
832; CHECK:       # %bb.0:
833; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
834; CHECK-NEXT:    vxor.vv v8, v8, v9
835; CHECK-NEXT:    ret
836  %vc = xor <vscale x 2 x i32> %va, %vb
837  ret <vscale x 2 x i32> %vc
838}
839
840define <vscale x 2 x i32> @vxor_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
841; CHECK-LABEL: vxor_vx_nxv2i32:
842; CHECK:       # %bb.0:
843; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
844; CHECK-NEXT:    vxor.vx v8, v8, a0
845; CHECK-NEXT:    ret
846  %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
847  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
848  %vc = xor <vscale x 2 x i32> %va, %splat
849  ret <vscale x 2 x i32> %vc
850}
851
852define <vscale x 2 x i32> @vxor_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
853; CHECK-LABEL: vxor_vi_nxv2i32_0:
854; CHECK:       # %bb.0:
855; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
856; CHECK-NEXT:    vxor.vi v8, v8, -1
857; CHECK-NEXT:    ret
858  %head = insertelement <vscale x 2 x i32> undef, i32 -1, i32 0
859  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
860  %vc = xor <vscale x 2 x i32> %va, %splat
861  ret <vscale x 2 x i32> %vc
862}
863
864define <vscale x 2 x i32> @vxor_vi_nxv2i32_1(<vscale x 2 x i32> %va) {
865; CHECK-LABEL: vxor_vi_nxv2i32_1:
866; CHECK:       # %bb.0:
867; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
868; CHECK-NEXT:    vxor.vi v8, v8, 8
869; CHECK-NEXT:    ret
870  %head = insertelement <vscale x 2 x i32> undef, i32 8, i32 0
871  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
872  %vc = xor <vscale x 2 x i32> %va, %splat
873  ret <vscale x 2 x i32> %vc
874}
875
876define <vscale x 2 x i32> @vxor_vi_nxv2i32_2(<vscale x 2 x i32> %va) {
877; CHECK-LABEL: vxor_vi_nxv2i32_2:
878; CHECK:       # %bb.0:
879; CHECK-NEXT:    addi a0, zero, 16
880; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
881; CHECK-NEXT:    vxor.vx v8, v8, a0
882; CHECK-NEXT:    ret
883  %head = insertelement <vscale x 2 x i32> undef, i32 16, i32 0
884  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
885  %vc = xor <vscale x 2 x i32> %va, %splat
886  ret <vscale x 2 x i32> %vc
887}
888
889define <vscale x 4 x i32> @vxor_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
890; CHECK-LABEL: vxor_vv_nxv4i32:
891; CHECK:       # %bb.0:
892; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
893; CHECK-NEXT:    vxor.vv v8, v8, v10
894; CHECK-NEXT:    ret
895  %vc = xor <vscale x 4 x i32> %va, %vb
896  ret <vscale x 4 x i32> %vc
897}
898
899define <vscale x 4 x i32> @vxor_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
900; CHECK-LABEL: vxor_vx_nxv4i32:
901; CHECK:       # %bb.0:
902; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
903; CHECK-NEXT:    vxor.vx v8, v8, a0
904; CHECK-NEXT:    ret
905  %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
906  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
907  %vc = xor <vscale x 4 x i32> %va, %splat
908  ret <vscale x 4 x i32> %vc
909}
910
911define <vscale x 4 x i32> @vxor_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
912; CHECK-LABEL: vxor_vi_nxv4i32_0:
913; CHECK:       # %bb.0:
914; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
915; CHECK-NEXT:    vxor.vi v8, v8, -1
916; CHECK-NEXT:    ret
917  %head = insertelement <vscale x 4 x i32> undef, i32 -1, i32 0
918  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
919  %vc = xor <vscale x 4 x i32> %va, %splat
920  ret <vscale x 4 x i32> %vc
921}
922
923define <vscale x 4 x i32> @vxor_vi_nxv4i32_1(<vscale x 4 x i32> %va) {
924; CHECK-LABEL: vxor_vi_nxv4i32_1:
925; CHECK:       # %bb.0:
926; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
927; CHECK-NEXT:    vxor.vi v8, v8, 8
928; CHECK-NEXT:    ret
929  %head = insertelement <vscale x 4 x i32> undef, i32 8, i32 0
930  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
931  %vc = xor <vscale x 4 x i32> %va, %splat
932  ret <vscale x 4 x i32> %vc
933}
934
935define <vscale x 4 x i32> @vxor_vi_nxv4i32_2(<vscale x 4 x i32> %va) {
936; CHECK-LABEL: vxor_vi_nxv4i32_2:
937; CHECK:       # %bb.0:
938; CHECK-NEXT:    addi a0, zero, 16
939; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
940; CHECK-NEXT:    vxor.vx v8, v8, a0
941; CHECK-NEXT:    ret
942  %head = insertelement <vscale x 4 x i32> undef, i32 16, i32 0
943  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
944  %vc = xor <vscale x 4 x i32> %va, %splat
945  ret <vscale x 4 x i32> %vc
946}
947
948define <vscale x 8 x i32> @vxor_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
949; CHECK-LABEL: vxor_vv_nxv8i32:
950; CHECK:       # %bb.0:
951; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
952; CHECK-NEXT:    vxor.vv v8, v8, v12
953; CHECK-NEXT:    ret
954  %vc = xor <vscale x 8 x i32> %va, %vb
955  ret <vscale x 8 x i32> %vc
956}
957
958define <vscale x 8 x i32> @vxor_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
959; CHECK-LABEL: vxor_vx_nxv8i32:
960; CHECK:       # %bb.0:
961; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
962; CHECK-NEXT:    vxor.vx v8, v8, a0
963; CHECK-NEXT:    ret
964  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
965  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
966  %vc = xor <vscale x 8 x i32> %va, %splat
967  ret <vscale x 8 x i32> %vc
968}
969
970define <vscale x 8 x i32> @vxor_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
971; CHECK-LABEL: vxor_vi_nxv8i32_0:
972; CHECK:       # %bb.0:
973; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
974; CHECK-NEXT:    vxor.vi v8, v8, -1
975; CHECK-NEXT:    ret
976  %head = insertelement <vscale x 8 x i32> undef, i32 -1, i32 0
977  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
978  %vc = xor <vscale x 8 x i32> %va, %splat
979  ret <vscale x 8 x i32> %vc
980}
981
982define <vscale x 8 x i32> @vxor_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
983; CHECK-LABEL: vxor_vi_nxv8i32_1:
984; CHECK:       # %bb.0:
985; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
986; CHECK-NEXT:    vxor.vi v8, v8, 8
987; CHECK-NEXT:    ret
988  %head = insertelement <vscale x 8 x i32> undef, i32 8, i32 0
989  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
990  %vc = xor <vscale x 8 x i32> %va, %splat
991  ret <vscale x 8 x i32> %vc
992}
993
994define <vscale x 8 x i32> @vxor_vi_nxv8i32_2(<vscale x 8 x i32> %va) {
995; CHECK-LABEL: vxor_vi_nxv8i32_2:
996; CHECK:       # %bb.0:
997; CHECK-NEXT:    addi a0, zero, 16
998; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
999; CHECK-NEXT:    vxor.vx v8, v8, a0
1000; CHECK-NEXT:    ret
1001  %head = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
1002  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
1003  %vc = xor <vscale x 8 x i32> %va, %splat
1004  ret <vscale x 8 x i32> %vc
1005}
1006
1007define <vscale x 16 x i32> @vxor_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
1008; CHECK-LABEL: vxor_vv_nxv16i32:
1009; CHECK:       # %bb.0:
1010; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
1011; CHECK-NEXT:    vxor.vv v8, v8, v16
1012; CHECK-NEXT:    ret
1013  %vc = xor <vscale x 16 x i32> %va, %vb
1014  ret <vscale x 16 x i32> %vc
1015}
1016
1017define <vscale x 16 x i32> @vxor_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
1018; CHECK-LABEL: vxor_vx_nxv16i32:
1019; CHECK:       # %bb.0:
1020; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
1021; CHECK-NEXT:    vxor.vx v8, v8, a0
1022; CHECK-NEXT:    ret
1023  %head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
1024  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
1025  %vc = xor <vscale x 16 x i32> %va, %splat
1026  ret <vscale x 16 x i32> %vc
1027}
1028
1029define <vscale x 16 x i32> @vxor_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
1030; CHECK-LABEL: vxor_vi_nxv16i32_0:
1031; CHECK:       # %bb.0:
1032; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
1033; CHECK-NEXT:    vxor.vi v8, v8, -1
1034; CHECK-NEXT:    ret
1035  %head = insertelement <vscale x 16 x i32> undef, i32 -1, i32 0
1036  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
1037  %vc = xor <vscale x 16 x i32> %va, %splat
1038  ret <vscale x 16 x i32> %vc
1039}
1040
1041define <vscale x 16 x i32> @vxor_vi_nxv16i32_1(<vscale x 16 x i32> %va) {
1042; CHECK-LABEL: vxor_vi_nxv16i32_1:
1043; CHECK:       # %bb.0:
1044; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
1045; CHECK-NEXT:    vxor.vi v8, v8, 8
1046; CHECK-NEXT:    ret
1047  %head = insertelement <vscale x 16 x i32> undef, i32 8, i32 0
1048  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
1049  %vc = xor <vscale x 16 x i32> %va, %splat
1050  ret <vscale x 16 x i32> %vc
1051}
1052
1053define <vscale x 16 x i32> @vxor_vi_nxv16i32_2(<vscale x 16 x i32> %va) {
1054; CHECK-LABEL: vxor_vi_nxv16i32_2:
1055; CHECK:       # %bb.0:
1056; CHECK-NEXT:    addi a0, zero, 16
1057; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
1058; CHECK-NEXT:    vxor.vx v8, v8, a0
1059; CHECK-NEXT:    ret
1060  %head = insertelement <vscale x 16 x i32> undef, i32 16, i32 0
1061  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
1062  %vc = xor <vscale x 16 x i32> %va, %splat
1063  ret <vscale x 16 x i32> %vc
1064}
1065
1066define <vscale x 1 x i64> @vxor_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
1067; CHECK-LABEL: vxor_vv_nxv1i64:
1068; CHECK:       # %bb.0:
1069; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
1070; CHECK-NEXT:    vxor.vv v8, v8, v9
1071; CHECK-NEXT:    ret
1072  %vc = xor <vscale x 1 x i64> %va, %vb
1073  ret <vscale x 1 x i64> %vc
1074}
1075
1076define <vscale x 1 x i64> @vxor_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
1077; CHECK-LABEL: vxor_vx_nxv1i64:
1078; CHECK:       # %bb.0:
1079; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
1080; CHECK-NEXT:    vxor.vx v8, v8, a0
1081; CHECK-NEXT:    ret
1082  %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
1083  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
1084  %vc = xor <vscale x 1 x i64> %va, %splat
1085  ret <vscale x 1 x i64> %vc
1086}
1087
1088define <vscale x 1 x i64> @vxor_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
1089; CHECK-LABEL: vxor_vi_nxv1i64_0:
1090; CHECK:       # %bb.0:
1091; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
1092; CHECK-NEXT:    vxor.vi v8, v8, -1
1093; CHECK-NEXT:    ret
1094  %head = insertelement <vscale x 1 x i64> undef, i64 -1, i32 0
1095  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
1096  %vc = xor <vscale x 1 x i64> %va, %splat
1097  ret <vscale x 1 x i64> %vc
1098}
1099
1100define <vscale x 1 x i64> @vxor_vi_nxv1i64_1(<vscale x 1 x i64> %va) {
1101; CHECK-LABEL: vxor_vi_nxv1i64_1:
1102; CHECK:       # %bb.0:
1103; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
1104; CHECK-NEXT:    vxor.vi v8, v8, 8
1105; CHECK-NEXT:    ret
1106  %head = insertelement <vscale x 1 x i64> undef, i64 8, i32 0
1107  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
1108  %vc = xor <vscale x 1 x i64> %va, %splat
1109  ret <vscale x 1 x i64> %vc
1110}
1111
1112define <vscale x 1 x i64> @vxor_vi_nxv1i64_2(<vscale x 1 x i64> %va) {
1113; CHECK-LABEL: vxor_vi_nxv1i64_2:
1114; CHECK:       # %bb.0:
1115; CHECK-NEXT:    addi a0, zero, 16
1116; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
1117; CHECK-NEXT:    vxor.vx v8, v8, a0
1118; CHECK-NEXT:    ret
1119  %head = insertelement <vscale x 1 x i64> undef, i64 16, i32 0
1120  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
1121  %vc = xor <vscale x 1 x i64> %va, %splat
1122  ret <vscale x 1 x i64> %vc
1123}
1124
1125define <vscale x 2 x i64> @vxor_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
1126; CHECK-LABEL: vxor_vv_nxv2i64:
1127; CHECK:       # %bb.0:
1128; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
1129; CHECK-NEXT:    vxor.vv v8, v8, v10
1130; CHECK-NEXT:    ret
1131  %vc = xor <vscale x 2 x i64> %va, %vb
1132  ret <vscale x 2 x i64> %vc
1133}
1134
1135define <vscale x 2 x i64> @vxor_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
1136; CHECK-LABEL: vxor_vx_nxv2i64:
1137; CHECK:       # %bb.0:
1138; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
1139; CHECK-NEXT:    vxor.vx v8, v8, a0
1140; CHECK-NEXT:    ret
1141  %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
1142  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
1143  %vc = xor <vscale x 2 x i64> %va, %splat
1144  ret <vscale x 2 x i64> %vc
1145}
1146
1147define <vscale x 2 x i64> @vxor_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
1148; CHECK-LABEL: vxor_vi_nxv2i64_0:
1149; CHECK:       # %bb.0:
1150; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
1151; CHECK-NEXT:    vxor.vi v8, v8, -1
1152; CHECK-NEXT:    ret
1153  %head = insertelement <vscale x 2 x i64> undef, i64 -1, i32 0
1154  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
1155  %vc = xor <vscale x 2 x i64> %va, %splat
1156  ret <vscale x 2 x i64> %vc
1157}
1158
1159define <vscale x 2 x i64> @vxor_vi_nxv2i64_1(<vscale x 2 x i64> %va) {
1160; CHECK-LABEL: vxor_vi_nxv2i64_1:
1161; CHECK:       # %bb.0:
1162; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
1163; CHECK-NEXT:    vxor.vi v8, v8, 8
1164; CHECK-NEXT:    ret
1165  %head = insertelement <vscale x 2 x i64> undef, i64 8, i32 0
1166  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
1167  %vc = xor <vscale x 2 x i64> %va, %splat
1168  ret <vscale x 2 x i64> %vc
1169}
1170
1171define <vscale x 2 x i64> @vxor_vi_nxv2i64_2(<vscale x 2 x i64> %va) {
1172; CHECK-LABEL: vxor_vi_nxv2i64_2:
1173; CHECK:       # %bb.0:
1174; CHECK-NEXT:    addi a0, zero, 16
1175; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
1176; CHECK-NEXT:    vxor.vx v8, v8, a0
1177; CHECK-NEXT:    ret
1178  %head = insertelement <vscale x 2 x i64> undef, i64 16, i32 0
1179  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
1180  %vc = xor <vscale x 2 x i64> %va, %splat
1181  ret <vscale x 2 x i64> %vc
1182}
1183
1184define <vscale x 4 x i64> @vxor_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
1185; CHECK-LABEL: vxor_vv_nxv4i64:
1186; CHECK:       # %bb.0:
1187; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
1188; CHECK-NEXT:    vxor.vv v8, v8, v12
1189; CHECK-NEXT:    ret
1190  %vc = xor <vscale x 4 x i64> %va, %vb
1191  ret <vscale x 4 x i64> %vc
1192}
1193
1194define <vscale x 4 x i64> @vxor_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
1195; CHECK-LABEL: vxor_vx_nxv4i64:
1196; CHECK:       # %bb.0:
1197; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
1198; CHECK-NEXT:    vxor.vx v8, v8, a0
1199; CHECK-NEXT:    ret
1200  %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
1201  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
1202  %vc = xor <vscale x 4 x i64> %va, %splat
1203  ret <vscale x 4 x i64> %vc
1204}
1205
1206define <vscale x 4 x i64> @vxor_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
1207; CHECK-LABEL: vxor_vi_nxv4i64_0:
1208; CHECK:       # %bb.0:
1209; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
1210; CHECK-NEXT:    vxor.vi v8, v8, -1
1211; CHECK-NEXT:    ret
1212  %head = insertelement <vscale x 4 x i64> undef, i64 -1, i32 0
1213  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
1214  %vc = xor <vscale x 4 x i64> %va, %splat
1215  ret <vscale x 4 x i64> %vc
1216}
1217
1218define <vscale x 4 x i64> @vxor_vi_nxv4i64_1(<vscale x 4 x i64> %va) {
1219; CHECK-LABEL: vxor_vi_nxv4i64_1:
1220; CHECK:       # %bb.0:
1221; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
1222; CHECK-NEXT:    vxor.vi v8, v8, 8
1223; CHECK-NEXT:    ret
1224  %head = insertelement <vscale x 4 x i64> undef, i64 8, i32 0
1225  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
1226  %vc = xor <vscale x 4 x i64> %va, %splat
1227  ret <vscale x 4 x i64> %vc
1228}
1229
1230define <vscale x 4 x i64> @vxor_vi_nxv4i64_2(<vscale x 4 x i64> %va) {
1231; CHECK-LABEL: vxor_vi_nxv4i64_2:
1232; CHECK:       # %bb.0:
1233; CHECK-NEXT:    addi a0, zero, 16
1234; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
1235; CHECK-NEXT:    vxor.vx v8, v8, a0
1236; CHECK-NEXT:    ret
1237  %head = insertelement <vscale x 4 x i64> undef, i64 16, i32 0
1238  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
1239  %vc = xor <vscale x 4 x i64> %va, %splat
1240  ret <vscale x 4 x i64> %vc
1241}
1242
1243define <vscale x 8 x i64> @vxor_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
1244; CHECK-LABEL: vxor_vv_nxv8i64:
1245; CHECK:       # %bb.0:
1246; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
1247; CHECK-NEXT:    vxor.vv v8, v8, v16
1248; CHECK-NEXT:    ret
1249  %vc = xor <vscale x 8 x i64> %va, %vb
1250  ret <vscale x 8 x i64> %vc
1251}
1252
1253define <vscale x 8 x i64> @vxor_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
1254; CHECK-LABEL: vxor_vx_nxv8i64:
1255; CHECK:       # %bb.0:
1256; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
1257; CHECK-NEXT:    vxor.vx v8, v8, a0
1258; CHECK-NEXT:    ret
1259  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
1260  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
1261  %vc = xor <vscale x 8 x i64> %va, %splat
1262  ret <vscale x 8 x i64> %vc
1263}
1264
1265define <vscale x 8 x i64> @vxor_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
1266; CHECK-LABEL: vxor_vi_nxv8i64_0:
1267; CHECK:       # %bb.0:
1268; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
1269; CHECK-NEXT:    vxor.vi v8, v8, -1
1270; CHECK-NEXT:    ret
1271  %head = insertelement <vscale x 8 x i64> undef, i64 -1, i32 0
1272  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
1273  %vc = xor <vscale x 8 x i64> %va, %splat
1274  ret <vscale x 8 x i64> %vc
1275}
1276
1277define <vscale x 8 x i64> @vxor_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
1278; CHECK-LABEL: vxor_vi_nxv8i64_1:
1279; CHECK:       # %bb.0:
1280; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
1281; CHECK-NEXT:    vxor.vi v8, v8, 8
1282; CHECK-NEXT:    ret
1283  %head = insertelement <vscale x 8 x i64> undef, i64 8, i32 0
1284  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
1285  %vc = xor <vscale x 8 x i64> %va, %splat
1286  ret <vscale x 8 x i64> %vc
1287}
1288
1289define <vscale x 8 x i64> @vxor_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
1290; CHECK-LABEL: vxor_vi_nxv8i64_2:
1291; CHECK:       # %bb.0:
1292; CHECK-NEXT:    addi a0, zero, 16
1293; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
1294; CHECK-NEXT:    vxor.vx v8, v8, a0
1295; CHECK-NEXT:    ret
1296  %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0
1297  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
1298  %vc = xor <vscale x 8 x i64> %va, %splat
1299  ret <vscale x 8 x i64> %vc
1300}
1301
1302