1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2 // REQUIRES: riscv-registered-target
3 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
4 // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
5
6 #include <riscv_vector.h>
7
8 //
9 // CHECK-RV64-LABEL: @test_vfredmax_vs_f32mf2_f32m1(
10 // CHECK-RV64-NEXT: entry:
11 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[DST:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 [[VL:%.*]])
12 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
13 //
test_vfredmax_vs_f32mf2_f32m1(vfloat32m1_t dst,vfloat32mf2_t vector,vfloat32m1_t scalar,size_t vl)14 vfloat32m1_t test_vfredmax_vs_f32mf2_f32m1(vfloat32m1_t dst,
15 vfloat32mf2_t vector,
16 vfloat32m1_t scalar, size_t vl) {
17 return vfredmax_vs_f32mf2_f32m1(dst, vector, scalar, vl);
18 }
19
20 //
21 // CHECK-RV64-LABEL: @test_vfredmax_vs_f32m1_f32m1(
22 // CHECK-RV64-NEXT: entry:
23 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[DST:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 [[VL:%.*]])
24 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
25 //
test_vfredmax_vs_f32m1_f32m1(vfloat32m1_t dst,vfloat32m1_t vector,vfloat32m1_t scalar,size_t vl)26 vfloat32m1_t test_vfredmax_vs_f32m1_f32m1(vfloat32m1_t dst, vfloat32m1_t vector,
27 vfloat32m1_t scalar, size_t vl) {
28 return vfredmax_vs_f32m1_f32m1(dst, vector, scalar, vl);
29 }
30
31 //
32 // CHECK-RV64-LABEL: @test_vfredmax_vs_f32m2_f32m1(
33 // CHECK-RV64-NEXT: entry:
34 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[DST:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 [[VL:%.*]])
35 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
36 //
test_vfredmax_vs_f32m2_f32m1(vfloat32m1_t dst,vfloat32m2_t vector,vfloat32m1_t scalar,size_t vl)37 vfloat32m1_t test_vfredmax_vs_f32m2_f32m1(vfloat32m1_t dst, vfloat32m2_t vector,
38 vfloat32m1_t scalar, size_t vl) {
39 return vfredmax_vs_f32m2_f32m1(dst, vector, scalar, vl);
40 }
41
42 //
43 // CHECK-RV64-LABEL: @test_vfredmax_vs_f32m4_f32m1(
44 // CHECK-RV64-NEXT: entry:
45 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv8f32.i64(<vscale x 2 x float> [[DST:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 [[VL:%.*]])
46 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
47 //
test_vfredmax_vs_f32m4_f32m1(vfloat32m1_t dst,vfloat32m4_t vector,vfloat32m1_t scalar,size_t vl)48 vfloat32m1_t test_vfredmax_vs_f32m4_f32m1(vfloat32m1_t dst, vfloat32m4_t vector,
49 vfloat32m1_t scalar, size_t vl) {
50 return vfredmax_vs_f32m4_f32m1(dst, vector, scalar, vl);
51 }
52
53 //
54 // CHECK-RV64-LABEL: @test_vfredmax_vs_f32m8_f32m1(
55 // CHECK-RV64-NEXT: entry:
56 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv16f32.i64(<vscale x 2 x float> [[DST:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 [[VL:%.*]])
57 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
58 //
test_vfredmax_vs_f32m8_f32m1(vfloat32m1_t dst,vfloat32m8_t vector,vfloat32m1_t scalar,size_t vl)59 vfloat32m1_t test_vfredmax_vs_f32m8_f32m1(vfloat32m1_t dst, vfloat32m8_t vector,
60 vfloat32m1_t scalar, size_t vl) {
61 return vfredmax_vs_f32m8_f32m1(dst, vector, scalar, vl);
62 }
63
64 //
65 // CHECK-RV64-LABEL: @test_vfredmax_vs_f64m1_f64m1(
66 // CHECK-RV64-NEXT: entry:
67 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]])
68 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
69 //
test_vfredmax_vs_f64m1_f64m1(vfloat64m1_t dst,vfloat64m1_t vector,vfloat64m1_t scalar,size_t vl)70 vfloat64m1_t test_vfredmax_vs_f64m1_f64m1(vfloat64m1_t dst, vfloat64m1_t vector,
71 vfloat64m1_t scalar, size_t vl) {
72 return vfredmax_vs_f64m1_f64m1(dst, vector, scalar, vl);
73 }
74
75 //
76 // CHECK-RV64-LABEL: @test_vfredmax_vs_f64m2_f64m1(
77 // CHECK-RV64-NEXT: entry:
78 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]])
79 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
80 //
test_vfredmax_vs_f64m2_f64m1(vfloat64m1_t dst,vfloat64m2_t vector,vfloat64m1_t scalar,size_t vl)81 vfloat64m1_t test_vfredmax_vs_f64m2_f64m1(vfloat64m1_t dst, vfloat64m2_t vector,
82 vfloat64m1_t scalar, size_t vl) {
83 return vfredmax_vs_f64m2_f64m1(dst, vector, scalar, vl);
84 }
85
86 //
87 // CHECK-RV64-LABEL: @test_vfredmax_vs_f64m4_f64m1(
88 // CHECK-RV64-NEXT: entry:
89 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv4f64.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]])
90 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
91 //
test_vfredmax_vs_f64m4_f64m1(vfloat64m1_t dst,vfloat64m4_t vector,vfloat64m1_t scalar,size_t vl)92 vfloat64m1_t test_vfredmax_vs_f64m4_f64m1(vfloat64m1_t dst, vfloat64m4_t vector,
93 vfloat64m1_t scalar, size_t vl) {
94 return vfredmax_vs_f64m4_f64m1(dst, vector, scalar, vl);
95 }
96
97 //
98 // CHECK-RV64-LABEL: @test_vfredmax_vs_f64m8_f64m1(
99 // CHECK-RV64-NEXT: entry:
100 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv8f64.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]])
101 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
102 //
test_vfredmax_vs_f64m8_f64m1(vfloat64m1_t dst,vfloat64m8_t vector,vfloat64m1_t scalar,size_t vl)103 vfloat64m1_t test_vfredmax_vs_f64m8_f64m1(vfloat64m1_t dst, vfloat64m8_t vector,
104 vfloat64m1_t scalar, size_t vl) {
105 return vfredmax_vs_f64m8_f64m1(dst, vector, scalar, vl);
106 }
107
108 //
109 // CHECK-RV64-LABEL: @test_vfredmax_vs_f32mf2_f32m1_m(
110 // CHECK-RV64-NEXT: entry:
111 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[DST:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
112 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
113 //
test_vfredmax_vs_f32mf2_f32m1_m(vbool64_t mask,vfloat32m1_t dst,vfloat32mf2_t vector,vfloat32m1_t scalar,size_t vl)114 vfloat32m1_t test_vfredmax_vs_f32mf2_f32m1_m(vbool64_t mask, vfloat32m1_t dst,
115 vfloat32mf2_t vector,
116 vfloat32m1_t scalar, size_t vl) {
117 return vfredmax_vs_f32mf2_f32m1_m(mask, dst, vector, scalar, vl);
118 }
119
120 //
121 // CHECK-RV64-LABEL: @test_vfredmax_vs_f32m1_f32m1_m(
122 // CHECK-RV64-NEXT: entry:
123 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[DST:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
124 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
125 //
test_vfredmax_vs_f32m1_f32m1_m(vbool32_t mask,vfloat32m1_t dst,vfloat32m1_t vector,vfloat32m1_t scalar,size_t vl)126 vfloat32m1_t test_vfredmax_vs_f32m1_f32m1_m(vbool32_t mask, vfloat32m1_t dst,
127 vfloat32m1_t vector,
128 vfloat32m1_t scalar, size_t vl) {
129 return vfredmax_vs_f32m1_f32m1_m(mask, dst, vector, scalar, vl);
130 }
131
132 //
133 // CHECK-RV64-LABEL: @test_vfredmax_vs_f32m2_f32m1_m(
134 // CHECK-RV64-NEXT: entry:
135 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[DST:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
136 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
137 //
test_vfredmax_vs_f32m2_f32m1_m(vbool16_t mask,vfloat32m1_t dst,vfloat32m2_t vector,vfloat32m1_t scalar,size_t vl)138 vfloat32m1_t test_vfredmax_vs_f32m2_f32m1_m(vbool16_t mask, vfloat32m1_t dst,
139 vfloat32m2_t vector,
140 vfloat32m1_t scalar, size_t vl) {
141 return vfredmax_vs_f32m2_f32m1_m(mask, dst, vector, scalar, vl);
142 }
143
144 //
145 // CHECK-RV64-LABEL: @test_vfredmax_vs_f32m4_f32m1_m(
146 // CHECK-RV64-NEXT: entry:
147 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv8f32.i64(<vscale x 2 x float> [[DST:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
148 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
149 //
test_vfredmax_vs_f32m4_f32m1_m(vbool8_t mask,vfloat32m1_t dst,vfloat32m4_t vector,vfloat32m1_t scalar,size_t vl)150 vfloat32m1_t test_vfredmax_vs_f32m4_f32m1_m(vbool8_t mask, vfloat32m1_t dst,
151 vfloat32m4_t vector,
152 vfloat32m1_t scalar, size_t vl) {
153 return vfredmax_vs_f32m4_f32m1_m(mask, dst, vector, scalar, vl);
154 }
155
156 //
157 // CHECK-RV64-LABEL: @test_vfredmax_vs_f32m8_f32m1_m(
158 // CHECK-RV64-NEXT: entry:
159 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv16f32.i64(<vscale x 2 x float> [[DST:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
160 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
161 //
test_vfredmax_vs_f32m8_f32m1_m(vbool4_t mask,vfloat32m1_t dst,vfloat32m8_t vector,vfloat32m1_t scalar,size_t vl)162 vfloat32m1_t test_vfredmax_vs_f32m8_f32m1_m(vbool4_t mask, vfloat32m1_t dst,
163 vfloat32m8_t vector,
164 vfloat32m1_t scalar, size_t vl) {
165 return vfredmax_vs_f32m8_f32m1_m(mask, dst, vector, scalar, vl);
166 }
167
168 //
169 // CHECK-RV64-LABEL: @test_vfredmax_vs_f64m1_f64m1_m(
170 // CHECK-RV64-NEXT: entry:
171 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
172 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
173 //
test_vfredmax_vs_f64m1_f64m1_m(vbool64_t mask,vfloat64m1_t dst,vfloat64m1_t vector,vfloat64m1_t scalar,size_t vl)174 vfloat64m1_t test_vfredmax_vs_f64m1_f64m1_m(vbool64_t mask, vfloat64m1_t dst,
175 vfloat64m1_t vector,
176 vfloat64m1_t scalar, size_t vl) {
177 return vfredmax_vs_f64m1_f64m1_m(mask, dst, vector, scalar, vl);
178 }
179
180 //
181 // CHECK-RV64-LABEL: @test_vfredmax_vs_f64m2_f64m1_m(
182 // CHECK-RV64-NEXT: entry:
183 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
184 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
185 //
test_vfredmax_vs_f64m2_f64m1_m(vbool32_t mask,vfloat64m1_t dst,vfloat64m2_t vector,vfloat64m1_t scalar,size_t vl)186 vfloat64m1_t test_vfredmax_vs_f64m2_f64m1_m(vbool32_t mask, vfloat64m1_t dst,
187 vfloat64m2_t vector,
188 vfloat64m1_t scalar, size_t vl) {
189 return vfredmax_vs_f64m2_f64m1_m(mask, dst, vector, scalar, vl);
190 }
191
192 //
193 // CHECK-RV64-LABEL: @test_vfredmax_vs_f64m4_f64m1_m(
194 // CHECK-RV64-NEXT: entry:
195 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv4f64.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
196 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
197 //
test_vfredmax_vs_f64m4_f64m1_m(vbool16_t mask,vfloat64m1_t dst,vfloat64m4_t vector,vfloat64m1_t scalar,size_t vl)198 vfloat64m1_t test_vfredmax_vs_f64m4_f64m1_m(vbool16_t mask, vfloat64m1_t dst,
199 vfloat64m4_t vector,
200 vfloat64m1_t scalar, size_t vl) {
201 return vfredmax_vs_f64m4_f64m1_m(mask, dst, vector, scalar, vl);
202 }
203
204 //
205 // CHECK-RV64-LABEL: @test_vfredmax_vs_f64m8_f64m1_m(
206 // CHECK-RV64-NEXT: entry:
207 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv8f64.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
208 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
209 //
test_vfredmax_vs_f64m8_f64m1_m(vbool8_t mask,vfloat64m1_t dst,vfloat64m8_t vector,vfloat64m1_t scalar,size_t vl)210 vfloat64m1_t test_vfredmax_vs_f64m8_f64m1_m(vbool8_t mask, vfloat64m1_t dst,
211 vfloat64m8_t vector,
212 vfloat64m1_t scalar, size_t vl) {
213 return vfredmax_vs_f64m8_f64m1_m(mask, dst, vector, scalar, vl);
214 }
215