1.. _amdgpu-dwarf-extensions-for-heterogeneous-debugging: 2 3******************************************** 4DWARF Extensions For Heterogeneous Debugging 5******************************************** 6 7.. contents:: 8 :local: 9 10.. warning:: 11 12 This document describes **provisional extensions** to DWARF Version 5 13 [:ref:`DWARF <amdgpu-dwarf-DWARF>`] to support heterogeneous debugging. It is 14 not currently fully implemented and is subject to change. 15 16.. _amdgpu-dwarf-introduction: 17 18Introduction 19============ 20 21AMD [:ref:`AMD <amdgpu-dwarf-AMD>`] has been working on supporting heterogeneous 22computing through the AMD Radeon Open Compute Platform (ROCm) [:ref:`AMD-ROCm 23<amdgpu-dwarf-AMD-ROCm>`]. A heterogeneous computing program can be written in a 24high level language such as C++ or Fortran with OpenMP pragmas, OpenCL, or HIP 25(a portable C++ programming environment for heterogeneous computing [:ref:`HIP 26<amdgpu-dwarf-HIP>`]). A heterogeneous compiler and runtime allows a program to 27execute on multiple devices within the same native process. Devices could 28include CPUs, GPUs, DSPs, FPGAs, or other special purpose accelerators. 29Currently HIP programs execute on systems with CPUs and GPUs. 30 31ROCm is fully open sourced and includes contributions to open source projects 32such as LLVM for compilation [:ref:`LLVM <amdgpu-dwarf-LLVM>`] and GDB for 33debugging [:ref:`GDB <amdgpu-dwarf-GDB>`], as well as collaboration with other 34third party projects such as the GCC compiler [:ref:`GCC <amdgpu-dwarf-GCC>`] 35and the Perforce TotalView HPC debugger [:ref:`Perforce-TotalView 36<amdgpu-dwarf-Perforce-TotalView>`]. 37 38To support debugging heterogeneous programs several features that are not 39provided by current DWARF Version 5 [:ref:`DWARF <amdgpu-dwarf-DWARF>`] have 40been identified. This document contains a collection of extensions to address 41providing those features. 42 43The :ref:`amdgpu-dwarf-motivation` section describes the issues that are being 44addressed for heterogeneous computing. That is followed by the 45:ref:`amdgpu-dwarf-changes-relative-to-dwarf-version-5` section containing the 46textual changes for the extensions relative to the DWARF Version 5 standard. 47Then there is an :ref:`amdgpu-dwarf-examples` section that links to the AMD GPU 48specific usage of the extensions that includes an example. Finally, there is a 49:ref:`amdgpu-dwarf-references` section. There are a number of notes included 50that raise open questions, or provide alternative approaches considered. The 51extensions seek to be general in nature and backwards compatible with DWARF 52Version 5. The goal is to be applicable to meeting the needs of any 53heterogeneous system and not be vendor or architecture specific. 54 55A fundamental aspect of the extensions is that it allows DWARF expression 56location descriptions as stack elements. The extensions are based on DWARF 57Version 5 and maintains compatibility with DWARF Version 5. After attempting 58several alternatives, the current thinking is that such extensions to DWARF 59Version 5 are the simplest and cleanest ways to support debugging optimized GPU 60code. It also appears to be generally useful and may be able to address other 61reported DWARF issues, as well as being helpful in providing better optimization 62support for non-GPU code. 63 64General feedback on these extensions is sought, together with suggestions on how 65to clarify, simplify, or organize them. If their is general interest then some 66or all of these extensions could be submitted as future DWARF proposals. 67 68We are in the process of modifying LLVM and GDB to support these extensions 69which is providing experience and insights. We plan to upstream the changes to 70those projects for any final form of the extensions. 71 72The author very much appreciates the input provided so far by many others which 73has been incorporated into this current version. 74 75.. _amdgpu-dwarf-motivation: 76 77Motivation 78========== 79 80This document presents a set of backwards compatible extensions to DWARF Version 815 [:ref:`DWARF <amdgpu-dwarf-DWARF>`] to support heterogeneous debugging. 82 83The remainder of this section provides motivation for each extension in 84terms of heterogeneous debugging on commercially available AMD GPU hardware 85(AMDGPU). The goal is to add support to the AMD [:ref:`AMD <amdgpu-dwarf-AMD>`] 86open source Radeon Open Compute Platform (ROCm) [:ref:`AMD-ROCm 87<amdgpu-dwarf-AMD-ROCm>`] which is an implementation of the industry standard 88for heterogeneous computing devices defined by the Heterogeneous System 89Architecture (HSA) Foundation [:ref:`HSA <amdgpu-dwarf-HSA>`]. ROCm includes the 90LLVM compiler [:ref:`LLVM <amdgpu-dwarf-LLVM>`] with upstreamed support for 91AMDGPU [:ref:`AMDGPU-LLVM <amdgpu-dwarf-AMDGPU-LLVM>`]. The goal is to also add 92the GDB debugger [:ref:`GDB <amdgpu-dwarf-GDB>`] with upstreamed support for 93AMDGPU [:ref:`AMD-ROCgdb <amdgpu-dwarf-AMD-ROCgdb>`]. In addition, the goal is 94to work with third parties to enable support for AMDGPU debugging in the GCC 95compiler [:ref:`GCC <amdgpu-dwarf-GCC>`] and the Perforce TotalView HPC debugger 96[:ref:`Perforce-TotalView <amdgpu-dwarf-Perforce-TotalView>`]. 97 98However, the extensions are intended to be vendor and architecture neutral. They 99are believed to apply to other heterogeneous hardware devices including GPUs, 100DSPs, FPGAs, and other specialized hardware. These collectively include similar 101characteristics and requirements as AMDGPU devices. Some of the extension can 102also apply to traditional CPU hardware that supports large vector registers. 103Compilers can map source languages and extensions that describe large scale 104parallel execution onto the lanes of the vector registers. This is common in 105programming languages used in ML and HPC. The extensions also include improved 106support for optimized code on any architecture. Some of the generalizations may 107also benefit other issues that have been raised. 108 109The extensions have evolved through collaboration with many individuals and 110active prototyping within the GDB debugger and LLVM compiler. Input has also 111been very much appreciated from the developers working on the Perforce TotalView 112HPC Debugger and GCC compiler. 113 114The AMDGPU has several features that require additional DWARF functionality in 115order to support optimized code. 116 117AMDGPU optimized code may spill vector registers to non-global address space 118memory, and this spilling may be done only for lanes that are active on entry 119to the subprogram. To support this, a location description that can be created 120as a masked select is required. See ``DW_OP_LLVM_select_bit_piece``. 121 122Since the active lane mask may be held in a register, a way to get the value 123of a register on entry to a subprogram is required. To support this an 124operation that returns the caller value of a register as specified by the Call 125Frame Information (CFI) is required. See ``DW_OP_LLVM_call_frame_entry_reg`` 126and :ref:`amdgpu-dwarf-call-frame-information`. 127 128Current DWARF uses an empty expression to indicate an undefined location 129description. Since the masked select composite location description operation 130takes more than one location description, it is necessary to have an explicit 131way to specify an undefined location description. Otherwise it is not possible 132to specify that a particular one of the input location descriptions is 133undefined. See ``DW_OP_LLVM_undefined``. 134 135CFI describes restoring callee saved registers that are spilled. Currently CFI 136only allows a location description that is a register, memory address, or 137implicit location description. AMDGPU optimized code may spill scalar 138registers into portions of vector registers. This requires extending CFI to 139allow any location description. See 140:ref:`amdgpu-dwarf-call-frame-information`. 141 142The vector registers of the AMDGPU are represented as their full wavefront 143size, meaning the wavefront size times the dword size. This reflects the 144actual hardware and allows the compiler to generate DWARF for languages that 145map a thread to the complete wavefront. It also allows more efficient DWARF to 146be generated to describe the CFI as only a single expression is required for 147the whole vector register, rather than a separate expression for each lane's 148dword of the vector register. It also allows the compiler to produce DWARF 149that indexes the vector register if it spills scalar registers into portions 150of a vector register. 151 152Since DWARF stack value entries have a base type and AMDGPU registers are a 153vector of dwords, the ability to specify that a base type is a vector is 154required. See ``DW_AT_LLVM_vector_size``. 155 156If the source language is mapped onto the AMDGPU wavefronts in a SIMT manner, 157then the variable DWARF location expressions must compute the location for a 158single lane of the wavefront. Therefore, a DWARF operation is required to denote 159the current lane, much like ``DW_OP_push_object_address`` denotes the current 160object. The ``DW_OP_*piece`` operations only allow literal indices. Therefore, a 161way to use a computed offset of an arbitrary location description (such as a 162vector register) is required. See ``DW_OP_LLVM_push_lane``, 163``DW_OP_LLVM_offset``, ``DW_OP_LLVM_offset_uconst``, and 164``DW_OP_LLVM_bit_offset``. 165 166If the source language is mapped onto the AMDGPU wavefronts in a SIMT manner 167the compiler can use the AMDGPU execution mask register to control which lanes 168are active. To describe the conceptual location of non-active lanes a DWARF 169expression is needed that can compute a per lane PC. For efficiency, this is 170done for the wavefront as a whole. This expression benefits by having a masked 171select composite location description operation. This requires an attribute 172for source location of each lane. The AMDGPU may update the execution mask for 173whole wavefront operations and so needs an attribute that computes the current 174active lane mask. See ``DW_OP_LLVM_select_bit_piece``, ``DW_OP_LLVM_extend``, 175``DW_AT_LLVM_lane_pc``, and ``DW_AT_LLVM_active_lane``. 176 177AMDGPU needs to be able to describe addresses that are in different kinds of 178memory. Optimized code may need to describe a variable that resides in pieces 179that are in different kinds of storage which may include parts of registers, 180memory that is in a mixture of memory kinds, implicit values, or be undefined. 181DWARF has the concept of segment addresses. However, the segment cannot be 182specified within a DWARF expression, which is only able to specify the offset 183portion of a segment address. The segment index is only provided by the entity 184that specifies the DWARF expression. Therefore, the segment index is a 185property that can only be put on complete objects, such as a variable. That 186makes it only suitable for describing an entity (such as variable or 187subprogram code) that is in a single kind of memory. Therefore, AMDGPU uses 188the DWARF concept of address spaces. For example, a variable may be allocated 189in a register that is partially spilled to the call stack which is in the 190private address space, and partially spilled to the local address space. 191 192DWARF uses the concept of an address in many expression operations but does not 193define how it relates to address spaces. For example, 194``DW_OP_push_object_address`` pushes the address of an object. Other contexts 195implicitly push an address on the stack before evaluating an expression. For 196example, the ``DW_AT_use_location`` attribute of the 197``DW_TAG_ptr_to_member_type``. The expression that uses the address needs to 198do so in a general way and not need to be dependent on the address space of 199the address. For example, a pointer to member value may want to be applied to 200an object that may reside in any address space. 201 202The number of registers and the cost of memory operations is much higher for 203AMDGPU than a typical CPU. The compiler attempts to optimize whole variables 204and arrays into registers. Currently DWARF only allows 205``DW_OP_push_object_address`` and related operations to work with a global 206memory location. To support AMDGPU optimized code it is required to generalize 207DWARF to allow any location description to be used. This allows registers, or 208composite location descriptions that may be a mixture of memory, registers, or 209even implicit values. 210 211DWARF Version 5 does not allow location descriptions to be entries on the 212DWARF stack. They can only be the final result of the evaluation of a DWARF 213expression. However, by allowing a location description to be a first-class 214entry on the DWARF stack it becomes possible to compose expressions containing 215both values and location descriptions naturally. It allows objects to be 216located in any kind of memory address space, in registers, be implicit values, 217be undefined, or a composite of any of these. By extending DWARF carefully, 218all existing DWARF expressions can retain their current semantic meaning. 219DWARF has implicit conversions that convert from a value that represents an 220address in the default address space to a memory location description. This 221can be extended to allow a default address space memory location description 222to be implicitly converted back to its address value. This allows all DWARF 223Version 5 expressions to retain their same meaning, while adding the ability 224to explicitly create memory location descriptions in non-default address 225spaces and generalizing the power of composite location descriptions to any 226kind of location description. See :ref:`amdgpu-dwarf-operation-expressions`. 227 228To allow composition of composite location descriptions, an explicit operation 229that indicates the end of the definition of a composite location description 230is required. This can be implied if the end of a DWARF expression is reached, 231allowing current DWARF expressions to remain legal. See 232``DW_OP_LLVM_piece_end``. 233 234The ``DW_OP_plus`` and ``DW_OP_minus`` can be defined to operate on a memory 235location description in the default target architecture specific address space 236and a generic type value to produce an updated memory location description. This 237allows them to continue to be used to offset an address. To generalize 238offsetting to any location description, including location descriptions that 239describe when bytes are in registers, are implicit, or a composite of these, the 240``DW_OP_LLVM_offset``, ``DW_OP_LLVM_offset_uconst``, and 241``DW_OP_LLVM_bit_offset`` offset operations are added. Unlike ``DW_OP_plus``, 242``DW_OP_plus_uconst``, and ``DW_OP_minus`` arithmetic operations, these do not 243define that integer overflow causes wrap-around. The offset operations can 244operate on location storage of any size. For example, implicit location storage 245could be any number of bits in size. It is simpler to define offsets that exceed 246the size of the location storage as being an evaluation error, than having to 247force an implementation to support potentially infinite precision offsets to 248allow it to correctly track a series of positive and negative offsets that may 249transiently overflow or underflow, but end up in range. This is simple for the 250arithmetic operations as they are defined in terms of two's compliment 251arithmetic on a base type of a fixed size. 252 253Having the offset operations allows ``DW_OP_push_object_address`` to push a 254location description that may be in a register, or be an implicit value, and the 255DWARF expression of ``DW_TAG_ptr_to_member_type`` can contain them to offset 256within it. ``DW_OP_LLVM_bit_offset`` generalizes DWARF to work with bit fields 257which is not possible in DWARF Version 5. 258 259The DWARF ``DW_OP_xderef*`` operations allow a value to be converted into an 260address of a specified address space which is then read. But it provides no 261way to create a memory location description for an address in the non-default 262address space. For example, AMDGPU variables can be allocated in the local 263address space at a fixed address. It is required to have an operation to 264create an address in a specific address space that can be used to define the 265location description of the variable. Defining this operation to produce a 266location description allows the size of addresses in an address space to be 267larger than the generic type. See ``DW_OP_LLVM_form_aspace_address``. 268 269If the ``DW_OP_LLVM_form_aspace_address`` operation had to produce a value 270that can be implicitly converted to a memory location description, then it 271would be limited to the size of the generic type which matches the size of the 272default address space. Its value would be undefined and likely not match any 273value in the actual program. By making the result a location description, it 274allows a consumer great freedom in how it implements it. The implicit 275conversion back to a value can be limited only to the default address space to 276maintain compatibility with DWARF Version 5. For other address spaces the 277producer can use the new operations that explicitly specify the address space. 278 279``DW_OP_breg*`` treats the register as containing an address in the default 280address space. It is required to be able to specify the address space of the 281register value. See ``DW_OP_LLVM_aspace_bregx``. 282 283Similarly, ``DW_OP_implicit_pointer`` treats its implicit pointer value as 284being in the default address space. It is required to be able to specify the 285address space of the pointer value. See 286``DW_OP_LLVM_aspace_implicit_pointer``. 287 288Almost all uses of addresses in DWARF are limited to defining location 289descriptions, or to be dereferenced to read memory. The exception is 290``DW_CFA_val_offset`` which uses the address to set the value of a register. 291By defining the CFA DWARF expression as being a memory location description, 292it can maintain what address space it is, and that can be used to convert the 293offset address back to an address in that address space. See 294:ref:`amdgpu-dwarf-call-frame-information`. 295 296This approach allows all existing DWARF to have the identical semantics. It 297allows the compiler to explicitly specify the address space it is using. For 298example, a compiler could choose to access private memory in a swizzled manner 299when mapping a source language to a wavefront in a SIMT manner, or to access 300it in an unswizzled manner if mapping the same language with the wavefront 301being the thread. It also allows the compiler to mix the address space it uses 302to access private memory. For example, for SIMT it can still spill entire 303vector registers in an unswizzled manner, while using a swizzled private 304memory for SIMT variable access. This approach allows memory location 305descriptions for different address spaces to be combined using the regular 306``DW_OP_*piece`` operations. 307 308Location descriptions are an abstraction of storage, they give freedom to the 309consumer on how to implement them. They allow the address space to encode lane 310information so they can be used to read memory with only the memory 311description and no extra arguments. The same set of operations can operate on 312locations independent of their kind of storage. The ``DW_OP_deref*`` therefore 313can be used on any storage kind. ``DW_OP_xderef*`` is unnecessary, except to 314become a more compact way to convert a non-default address space address 315followed by dereferencing it. 316 317In DWARF Version 5 a location description is defined as a single location 318description or a location list. A location list is defined as either 319effectively an undefined location description or as one or more single 320location descriptions to describe an object with multiple places. The 321``DW_OP_push_object_address`` and ``DW_OP_call*`` operations can put a 322location description on the stack. Furthermore, debugger information entry 323attributes such as ``DW_AT_data_member_location``, ``DW_AT_use_location``, and 324``DW_AT_vtable_elem_location`` are defined as pushing a location description 325on the expression stack before evaluating the expression. However, DWARF 326Version 5 only allows the stack to contain values and so only a single memory 327address can be on the stack which makes these incapable of handling location 328descriptions with multiple places, or places other than memory. Since these 329extensions allow the stack to contain location descriptions, the operations are 330generalized to support location descriptions that can have multiple places. 331This is backwards compatible with DWARF Version 5 and allows objects with 332multiple places to be supported. For example, the expression that describes 333how to access the field of an object can be evaluated with a location 334description that has multiple places and will result in a location description 335with multiple places as expected. With this change, the separate DWARF Version 3365 sections that described DWARF expressions and location lists have been 337unified into a single section that describes DWARF expressions in general. 338This unification seems to be a natural consequence and a necessity of allowing 339location descriptions to be part of the evaluation stack. 340 341For those familiar with the definition of location descriptions in DWARF Version 3425, the definitions in these extensions are presented differently, but does 343in fact define the same concept with the same fundamental semantics. However, 344it does so in a way that allows the concept to extend to support address 345spaces, bit addressing, the ability for composite location descriptions to be 346composed of any kind of location description, and the ability to support 347objects located at multiple places. Collectively these changes expand the set 348of processors that can be supported and improves support for optimized code. 349 350Several approaches were considered, and the one presented appears to be the 351cleanest and offers the greatest improvement of DWARF's ability to support 352optimized code. Examining the GDB debugger and LLVM compiler, it appears only 353to require modest changes as they both already have to support general use of 354location descriptions. It is anticipated that will also be the case for other 355debuggers and compilers. 356 357As an experiment, GDB was modified to evaluate DWARF Version 5 expressions 358with location descriptions as stack entries and implicit conversions. All GDB 359tests have passed, except one that turned out to be an invalid test by DWARF 360Version 5 rules. The code in GDB actually became simpler as all evaluation was 361on the stack and there was no longer a need to maintain a separate structure 362for the location description result. This gives confidence of the backwards 363compatibility. 364 365Since the AMDGPU supports languages such as OpenCL [:ref:`OpenCL 366<amdgpu-dwarf-OpenCL>`], there is a need to define source language address 367classes so they can be used in a consistent way by consumers. It would also be 368desirable to add support for using them in defining language types rather than 369the current target architecture specific address spaces. See 370:ref:`amdgpu-dwarf-segment_addresses`. 371 372A ``DW_AT_LLVM_augmentation`` attribute is added to a compilation unit 373debugger information entry to indicate that there is additional target 374architecture specific information in the debugging information entries of that 375compilation unit. This allows a consumer to know what extensions are present 376in the debugger information entries as is possible with the augmentation 377string of other sections. The format that should be used for the augmentation 378string in the lookup by name table and CFI Common Information Entry is also 379recommended to allow a consumer to parse the string when it contains 380information from multiple vendors. 381 382The AMDGPU supports programming languages that include online compilation 383where the source text may be created at runtime. Therefore, a way to embed the 384source text in the debug information is required. For example, the OpenCL 385language runtime supports online compilation. See 386:ref:`amdgpu-dwarf-line-number-information`. 387 388Support to allow MD5 checksums to be optionally present in the line table is 389added. This allows linking together compilation units where some have MD5 390checksums and some do not. In DWARF Version 5 the file timestamp and file size 391can be optional, but if the MD5 checksum is present it must be valid for all 392files. See :ref:`amdgpu-dwarf-line-number-information`. 393 394Support is added for the HIP programming language [:ref:`HIP 395<amdgpu-dwarf-HIP>`] which is supported by the AMDGPU. See 396:ref:`amdgpu-dwarf-language-names`. 397 398The following sections provide the definitions for the additional operations, 399as well as clarifying how existing expression operations, CFI operations, and 400attributes behave with respect to generalized location descriptions that 401support address spaces and location descriptions that support multiple places. 402It has been defined such that it is backwards compatible with DWARF Version 5. 403The definitions are intended to fully define well-formed DWARF in a consistent 404style based on the DWARF Version 5 specification. Non-normative text is shown 405in *italics*. 406 407The names for the new operations, attributes, and constants include "\ 408``LLVM``\ " and are encoded with vendor specific codes so these extensions can 409be implemented as an LLVM vendor extension to DWARF Version 5. If accepted these 410names would not include the "\ ``LLVM``\ " and would not use encodings in the 411vendor range. 412 413The extensions are described in 414:ref:`amdgpu-dwarf-changes-relative-to-dwarf-version-5` and are 415organized to follow the section ordering of DWARF Version 5. It includes notes 416to indicate the corresponding DWARF Version 5 sections to which they pertain. 417Other notes describe additional changes that may be worth considering, and to 418raise questions. 419 420.. _amdgpu-dwarf-changes-relative-to-dwarf-version-5: 421 422Changes Relative to DWARF Version 5 423=================================== 424 425General Description 426------------------- 427 428Attribute Types 429~~~~~~~~~~~~~~~ 430 431.. note:: 432 433 This augments DWARF Version 5 section 2.2 and Table 2.2. 434 435The following table provides the additional attributes. See 436:ref:`amdgpu-dwarf-debugging-information-entry-attributes`. 437 438.. table:: Attribute names 439 :name: amdgpu-dwarf-attribute-names-table 440 441 =========================== ==================================== 442 Attribute Usage 443 =========================== ==================================== 444 ``DW_AT_LLVM_active_lane`` SIMD or SIMT active lanes 445 ``DW_AT_LLVM_augmentation`` Compilation unit augmentation string 446 ``DW_AT_LLVM_lane_pc`` SIMD or SIMT lane program location 447 ``DW_AT_LLVM_lanes`` SIMD or SIMT thread lane count 448 ``DW_AT_LLVM_vector_size`` Base type vector size 449 =========================== ==================================== 450 451.. _amdgpu-dwarf-expressions: 452 453DWARF Expressions 454~~~~~~~~~~~~~~~~~ 455 456.. note:: 457 458 This section, and its nested sections, replaces DWARF Version 5 section 2.5 459 and section 2.6. The new DWARF expression operation extensions are defined as 460 well as clarifying the extensions to already existing DWARF Version 5 461 operations. It is based on the text of the existing DWARF Version 5 standard. 462 463DWARF expressions describe how to compute a value or specify a location. 464 465*The evaluation of a DWARF expression can provide the location of an object, the 466value of an array bound, the length of a dynamic string, the desired value 467itself, and so on.* 468 469If the evaluation of a DWARF expression does not encounter an error, then it can 470either result in a value (see :ref:`amdgpu-dwarf-expression-value`) or a 471location description (see :ref:`amdgpu-dwarf-location-description`). When a 472DWARF expression is evaluated, it may be specified whether a value or location 473description is required as the result kind. 474 475If a result kind is specified, and the result of the evaluation does not match 476the specified result kind, then the implicit conversions described in 477:ref:`amdgpu-dwarf-memory-location-description-operations` are performed if 478valid. Otherwise, the DWARF expression is ill-formed. 479 480If the evaluation of a DWARF expression encounters an evaluation error, then the 481result is an evaluation error. 482 483.. note:: 484 485 Decided to define the concept of an evaluation error. An alternative is to 486 introduce an undefined value base type in a similar way to location 487 descriptions having an undefined location description. Then operations that 488 encounter an evaluation error can return the undefined location description or 489 value with an undefined base type. 490 491 All operations that act on values would return an undefined entity if given an 492 undefined value. The expression would then always evaluate to completion, and 493 can be tested to determine if it is an undefined entity. 494 495 However, this would add considerable additional complexity and does not match 496 that GDB throws an exception when these evaluation errors occur. 497 498If a DWARF expression is ill-formed, then the result is undefined. 499 500The following sections detail the rules for when a DWARF expression is 501ill-formed or results in an evaluation error. 502 503A DWARF expression can either be encoded as an operation expression (see 504:ref:`amdgpu-dwarf-operation-expressions`), or as a location list expression 505(see :ref:`amdgpu-dwarf-location-list-expressions`). 506 507.. _amdgpu-dwarf-expression-evaluation-context: 508 509DWARF Expression Evaluation Context 510+++++++++++++++++++++++++++++++++++ 511 512A DWARF expression is evaluated in a context that can include a number of 513context elements. If multiple context elements are specified then they must be 514self consistent or the result of the evaluation is undefined. The context 515elements that can be specified are: 516 517*A current result kind* 518 519 The kind of result required by the DWARF expression evaluation. If specified 520 it can be a location description or a value. 521 522*A current thread* 523 524 The target architecture thread identifier of the source program thread of 525 execution for which a user presented expression is currently being evaluated. 526 527 It is required for operations that are related to target architecture threads. 528 529 *For example, the* ``DW_OP_form_tls_address`` *operation and* 530 ``DW_OP_LLVM_form_aspace_address`` *operation when given an address space that 531 is thread specific.* 532 533*A current lane* 534 535 The target architecture lane identifier of the source program thread of 536 execution for which a user presented expression is currently being evaluated. 537 This applies to languages that are implemented using a SIMD or SIMT execution 538 model. 539 540 It is required for operations that are related to target architecture lanes. 541 542 *For example, the* ``DW_OP_LLVM_push_lane`` *operation and* 543 ``DW_OP_LLVM_form_aspace_address`` *operation when given an address space that 544 is lane specific.* 545 546 If specified, it must be consistent with any specified current thread and 547 current target architecture. It is consistent with a thread if it identifies a 548 lane of the thread. It is consistent with a target architecture if it is a 549 valid lane identifier of the target architecture. Otherwise the result is 550 undefined. 551 552*A current call frame* 553 554 The target architecture call frame identifier. It identifies a call frame that 555 corresponds to an active invocation of a subprogram in the current thread. It 556 is identified by its address on the call stack. The address is referred to as 557 the Canonical Frame Address (CFA). The call frame information is used to 558 determine the CFA for the call frames of the current thread's call stack (see 559 :ref:`amdgpu-dwarf-call-frame-information`). 560 561 It is required for operations that specify target architecture registers to 562 support virtual unwinding of the call stack. 563 564 *For example, the* ``DW_OP_*reg*`` *operations.* 565 566 If specified, it must be an active call frame in the current thread. If the 567 current lane is specified, then that lane must have been active on entry to 568 the call frame (see the ``DW_AT_LLVM_lane_pc`` attribute). Otherwise the 569 result is undefined. 570 571 If it is the currently executing call frame, then it is termed the top call 572 frame. 573 574*A current program location* 575 576 The target architecture program location corresponding to the current call 577 frame of the current thread. 578 579 The program location of the top call frame is the target architecture program 580 counter for the current thread. The call frame information is used to obtain 581 the value of the return address register to determine the program location of 582 the other call frames (see :ref:`amdgpu-dwarf-call-frame-information`). 583 584 It is required for the evaluation of location list expressions to select 585 amongst multiple program location ranges. It is required for operations that 586 specify target architecture registers to support virtual unwinding of the call 587 stack (see :ref:`amdgpu-dwarf-call-frame-information`). 588 589 If specified: 590 591 * If the current lane is not specified: 592 593 * If the current call frame is the top call frame, it must be the current 594 target architecture program location. 595 596 * If the current call frame F is not the top call frame, it must be the 597 program location associated with the call site in the current caller frame 598 F that invoked the callee frame. 599 600 * If the current lane is specified and the architecture program location LPC 601 computed by the ``DW_AT_LLVM_lane_pc`` attribute for the current lane is not 602 the undefined location description (indicating the lane was not active on 603 entry to the call frame), it must be LPC. 604 605 * Otherwise the result is undefined. 606 607*A current compilation unit* 608 609 The compilation unit debug information entry that contains the DWARF expression 610 being evaluated. 611 612 It is required for operations that reference debug information associated with 613 the same compilation unit, including indicating if such references use the 614 32-bit or 64-bit DWARF format. It can also provide the default address space 615 address size if no current target architecture is specified. 616 617 *For example, the* ``DW_OP_constx`` *and* ``DW_OP_addrx`` *operations.* 618 619 *Note that this compilation unit may not be the same as the compilation unit 620 determined from the loaded code object corresponding to the current program 621 location. For example, the evaluation of the expression E associated with a 622 ``DW_AT_location`` attribute of the debug information entry operand of the 623 ``DW_OP_call*`` operations is evaluated with the compilation unit that 624 contains E and not the one that contains the ``DW_OP_call*`` operation 625 expression.* 626 627*A current target architecture* 628 629 The target architecture. 630 631 It is required for operations that specify target architecture specific 632 entities. 633 634 *For example, target architecture specific entities include DWARF register 635 identifiers, DWARF lane identifiers, DWARF address space identifiers, the 636 default address space, and the address space address sizes.* 637 638 If specified: 639 640 * If the current thread is specified, then the current target architecture 641 must be the same as the target architecture of the current thread. 642 643 * If the current compilation unit is specified, then the current target 644 architecture default address space address size must be the same as he 645 ``address_size`` field in the header of the current compilation unit and any 646 associated entry in the ``.debug_aranges`` section. 647 648 * If the current program location is specified, then the current target 649 architecture must be the same as the target architecture of any line number 650 information entry (see :ref:`amdgpu-dwarf-line-number-information`) 651 corresponding to the current program location. 652 653 * If the current program location is specified, then the current target 654 architecture default address space address size must be the same as he 655 ``address_size`` field in the header of any entry corresponding to the 656 current program location in the ``.debug_addr``, ``.debug_line``, 657 ``.debug_rnglists``, ``.debug_rnglists.dwo``, ``.debug_loclists``, and 658 ``.debug_loclists.dwo`` sections. 659 660 * Otherwise the result is undefined. 661 662*A current object* 663 664 The location description of a program object. 665 666 It is required for the ``DW_OP_push_object_address`` operation. 667 668 *For example, the* ``DW_AT_data_location`` *attribute on type debug 669 information entries specifies the the program object corresponding to a 670 runtime descriptor as the current object when it evaluates its associated 671 expression.* 672 673 The result is undefined if the location descriptor is invalid (see 674 :ref:`amdgpu-dwarf-location-description`). 675 676*An initial stack* 677 678 This is a list of values or location descriptions that will be pushed on the 679 operation expression evaluation stack in the order provided before evaluation 680 of an operation expression starts. 681 682 Some debugger information entries have attributes that evaluate their DWARF 683 expression value with initial stack entries. In all other cases the initial 684 stack is empty. 685 686 The result is undefined if any location descriptors are invalid (see 687 :ref:`amdgpu-dwarf-location-description`). 688 689If the evaluation requires a context element that is not specified, then the 690result of the evaluation is an error. 691 692*A DWARF expression for the location description may be able to be evaluated 693without a thread, lane, call frame, program location, or architecture context. 694For example, the location of a global variable may be able to be evaluated 695without such context. If the expression evaluates with an error then it may 696indicate the variable has been optimized and so requires more context.* 697 698*The DWARF expression for call frame information (see 699:ref:`amdgpu-dwarf-call-frame-information`) operations are restricted to those 700that do not require the compilation unit context to be specified.* 701 702The DWARF is ill-formed if all the ``address_size`` fields in the headers of all 703the entries in the ``.debug_info``, ``.debug_addr``, ``.debug_line``, 704``.debug_rnglists``, ``.debug_rnglists.dwo``, ``.debug_loclists``, and 705``.debug_loclists.dwo`` sections corresponding to any given program location do 706not match. 707 708.. _amdgpu-dwarf-expression-value: 709 710DWARF Expression Value 711++++++++++++++++++++++ 712 713A value has a type and a literal value. It can represent a literal value of any 714supported base type of the target architecture. The base type specifies the 715size, encoding, and endianity of the literal value. 716 717.. note:: 718 719 It may be desirable to add an implicit pointer base type encoding. It would be 720 used for the type of the value that is produced when the ``DW_OP_deref*`` 721 operation retrieves the full contents of an implicit pointer location storage 722 created by the ``DW_OP_implicit_pointer`` or 723 ``DW_OP_LLVM_aspace_implicit_pointer`` operations. The literal value would 724 record the debugging information entry and byte displacement specified by the 725 associated ``DW_OP_implicit_pointer`` or 726 ``DW_OP_LLVM_aspace_implicit_pointer`` operations. 727 728There is a distinguished base type termed the generic type, which is an integral 729type that has the size of an address in the target architecture default address 730space, a target architecture defined endianity, and unspecified signedness. 731 732*The generic type is the same as the unspecified type used for stack operations 733defined in DWARF Version 4 and before.* 734 735An integral type is a base type that has an encoding of ``DW_ATE_signed``, 736``DW_ATE_signed_char``, ``DW_ATE_unsigned``, ``DW_ATE_unsigned_char``, 737``DW_ATE_boolean``, or any target architecture defined integral encoding in the 738inclusive range ``DW_ATE_lo_user`` to ``DW_ATE_hi_user``. 739 740.. note:: 741 742 It is unclear if ``DW_ATE_address`` is an integral type. GDB does not seem to 743 consider it as integral. 744 745.. _amdgpu-dwarf-location-description: 746 747DWARF Location Description 748++++++++++++++++++++++++++ 749 750*Debugging information must provide consumers a way to find the location of 751program variables, determine the bounds of dynamic arrays and strings, and 752possibly to find the base address of a subprogram’s call frame or the return 753address of a subprogram. Furthermore, to meet the needs of recent computer 754architectures and optimization techniques, debugging information must be able to 755describe the location of an object whose location changes over the object’s 756lifetime, and may reside at multiple locations simultaneously during parts of an 757object's lifetime.* 758 759Information about the location of program objects is provided by location 760descriptions. 761 762Location descriptions can consist of one or more single location descriptions. 763 764A single location description specifies the location storage that holds a 765program object and a position within the location storage where the program 766object starts. The position within the location storage is expressed as a bit 767offset relative to the start of the location storage. 768 769A location storage is a linear stream of bits that can hold values. Each 770location storage has a size in bits and can be accessed using a zero-based bit 771offset. The ordering of bits within a location storage uses the bit numbering 772and direction conventions that are appropriate to the current language on the 773target architecture. 774 775There are five kinds of location storage: 776 777*memory location storage* 778 Corresponds to the target architecture memory address spaces. 779 780*register location storage* 781 Corresponds to the target architecture registers. 782 783*implicit location storage* 784 Corresponds to fixed values that can only be read. 785 786*undefined location storage* 787 Indicates no value is available and therefore cannot be read or written. 788 789*composite location storage* 790 Allows a mixture of these where some bits come from one location storage and 791 some from another location storage, or from disjoint parts of the same 792 location storage. 793 794.. note:: 795 796 It may be better to add an implicit pointer location storage kind used by the 797 ``DW_OP_implicit_pointer`` and ``DW_OP_LLVM_aspace_implicit_pointer`` 798 operations. It would specify the debugger information entry and byte offset 799 provided by the operations. 800 801*Location descriptions are a language independent representation of addressing 802rules. They are created using DWARF operation expressions of arbitrary 803complexity. They can be the result of evaluating a debugger information entry 804attribute that specifies an operation expression. In this usage they can 805describe the location of an object as long as its lifetime is either static or 806the same as the lexical block (see DWARF Version 5 section 3.5) that owns it, 807and it does not move during its lifetime. They can be the result of evaluating a 808debugger information entry attribute that specifies a location list expression. 809In this usage they can describe the location of an object that has a limited 810lifetime, changes its location during its lifetime, or has multiple locations 811over part or all of its lifetime.* 812 813If a location description has more than one single location description, the 814DWARF expression is ill-formed if the object value held in each single location 815description's position within the associated location storage is not the same 816value, except for the parts of the value that are uninitialized. 817 818*A location description that has more than one single location description can 819only be created by a location list expression that has overlapping program 820location ranges, or certain expression operations that act on a location 821description that has more than one single location description. There are no 822operation expression operations that can directly create a location description 823with more than one single location description.* 824 825*A location description with more than one single location description can be 826used to describe objects that reside in more than one piece of storage at the 827same time. An object may have more than one location as a result of 828optimization. For example, a value that is only read may be promoted from memory 829to a register for some region of code, but later code may revert to reading the 830value from memory as the register may be used for other purposes. For the code 831region where the value is in a register, any change to the object value must be 832made in both the register and the memory so both regions of code will read the 833updated value.* 834 835*A consumer of a location description with more than one single location 836description can read the object's value from any of the single location 837descriptions (since they all refer to location storage that has the same value), 838but must write any changed value to all the single location descriptions.* 839 840The evaluation of an expression may require context elements to create a 841location description. If such a location description is accessed, the storage it 842denotes is that associated with the context element values specified when the 843location description was created, which may differ from the context at the time 844it is accessed. 845 846*For example, creating a register location description requires the thread 847context: the location storage is for the specified register of that thread. 848Creating a memory location description for an address space may required a 849thread and a lane context: the location storage is the memory associated with 850that thread and lane.* 851 852If any of the context elements required to create a location description change, 853the location description becomes invalid and accessing it is undefined. 854 855*Examples of context that can invalidate a location description are:* 856 857* *The thread context is required and execution causes the thread to terminate.* 858* *The call frame context is required and further execution causes the call 859 frame to return to the calling frame.* 860* *The program location is required and further execution of the thread occurs. 861 That could change the location list entry or call frame information entry that 862 applies.* 863* *An operation uses call frame information:* 864 865 * *Any of the frames used in the virtual call frame unwinding return.* 866 * *The top call frame is used, the program location is used to select the call 867 frame information entry, and further execution of the thread occurs.* 868 869*A DWARF expression can be used to compute a location description for an object. 870A subsequent DWARF expression evaluation can be given the object location 871description as the object context or initial stack context to compute a 872component of the object. The final result is undefined if the object location 873description becomes invalid between the two expression evaluations.* 874 875A change of a thread's program location may not make a location description 876invalid, yet may still render it as no longer meaningful. Accessing such a 877location description, or using it as the object context or initial stack context 878of an expression evaluation, may produce an undefined result. 879 880*For example, a location description may specify a register that no longer holds 881the intended program object after a program location change. One way to avoid 882such problems is to recompute location descriptions associated with threads when 883their program locations change.* 884 885.. _amdgpu-dwarf-operation-expressions: 886 887DWARF Operation Expressions 888+++++++++++++++++++++++++++ 889 890An operation expression is comprised of a stream of operations, each consisting 891of an opcode followed by zero or more operands. The number of operands is 892implied by the opcode. 893 894Operations represent a postfix operation on a simple stack machine. Each stack 895entry can hold either a value or a location description. Operations can act on 896entries on the stack, including adding entries and removing entries. If the kind 897of a stack entry does not match the kind required by the operation and is not 898implicitly convertible to the required kind (see 899:ref:`amdgpu-dwarf-memory-location-description-operations`), then the DWARF 900operation expression is ill-formed. 901 902Evaluation of an operation expression starts with an empty stack on which the 903entries from the initial stack provided by the context are pushed in the order 904provided. Then the operations are evaluated, starting with the first operation 905of the stream. Evaluation continues until either an operation has an evaluation 906error, or until one past the last operation of the stream is reached. 907 908The result of the evaluation is: 909 910* If an operation has an evaluation error, or an operation evaluates an 911 expression that has an evaluation error, then the result is an evaluation 912 error. 913 914* If the current result kind specifies a location description, then: 915 916 * If the stack is empty, the result is a location description with one 917 undefined location description. 918 919 *This rule is for backwards compatibility with DWARF Version 5 which has no 920 explicit operation to create an undefined location description, and uses an 921 empty operation expression for this purpose.* 922 923 * If the top stack entry is a location description, or can be converted 924 to one (see :ref:`amdgpu-dwarf-memory-location-description-operations`), 925 then the result is that, possibly converted, location description. Any other 926 entries on the stack are discarded. 927 928 * Otherwise the DWARF expression is ill-formed. 929 930 .. note:: 931 932 Could define this case as returning an implicit location description as 933 if the ``DW_OP_implicit`` operation is performed. 934 935* If the current result kind specifies a value, then: 936 937 * If the top stack entry is a value, or can be converted to one (see 938 :ref:`amdgpu-dwarf-memory-location-description-operations`), then the result 939 is that, possibly converted, value. Any other entries on the stack are 940 discarded. 941 942 * Otherwise the DWARF expression is ill-formed. 943 944* If the current result kind is not specified, then: 945 946 * If the stack is empty, the result is a location description with one 947 undefined location description. 948 949 *This rule is for backwards compatibility with DWARF Version 5 which has no 950 explicit operation to create an undefined location description, and uses an 951 empty operation expression for this purpose.* 952 953 .. note:: 954 955 This rule is consistent with the rule above for when a location 956 description is requested. However, GDB appears to report this as an error 957 and no GDB tests appear to cause an empty stack for this case. 958 959 * Otherwise, the top stack entry is returned. Any other entries on the stack 960 are discarded. 961 962An operation expression is encoded as a byte block with some form of prefix that 963specifies the byte count. It can be used: 964 965* as the value of a debugging information entry attribute that is encoded using 966 class ``exprloc`` (see DWARF Version 5 section 7.5.5), 967 968* as the operand to certain operation expression operations, 969 970* as the operand to certain call frame information operations (see 971 :ref:`amdgpu-dwarf-call-frame-information`), 972 973* and in location list entries (see 974 :ref:`amdgpu-dwarf-location-list-expressions`). 975 976.. _amdgpu-dwarf-stack-operations: 977 978Stack Operations 979################ 980 981The following operations manipulate the DWARF stack. Operations that index the 982stack assume that the top of the stack (most recently added entry) has index 0. 983They allow the stack entries to be either a value or location description. 984 985If any stack entry accessed by a stack operation is an incomplete composite 986location description (see 987:ref:`amdgpu-dwarf-composite-location-description-operations`), then the DWARF 988expression is ill-formed. 989 990.. note:: 991 992 These operations now support stack entries that are values and location 993 descriptions. 994 995.. note:: 996 997 If it is desired to also make them work with incomplete composite location 998 descriptions, then would need to define that the composite location storage 999 specified by the incomplete composite location description is also replicated 1000 when a copy is pushed. This ensures that each copy of the incomplete composite 1001 location description can update the composite location storage they specify 1002 independently. 1003 10041. ``DW_OP_dup`` 1005 1006 ``DW_OP_dup`` duplicates the stack entry at the top of the stack. 1007 10082. ``DW_OP_drop`` 1009 1010 ``DW_OP_drop`` pops the stack entry at the top of the stack and discards it. 1011 10123. ``DW_OP_pick`` 1013 1014 ``DW_OP_pick`` has a single unsigned 1-byte operand that represents an index 1015 I. A copy of the stack entry with index I is pushed onto the stack. 1016 10174. ``DW_OP_over`` 1018 1019 ``DW_OP_over`` pushes a copy of the entry with index 1. 1020 1021 *This is equivalent to a ``DW_OP_pick 1`` operation.* 1022 10235. ``DW_OP_swap`` 1024 1025 ``DW_OP_swap`` swaps the top two stack entries. The entry at the top of the 1026 stack becomes the second stack entry, and the second stack entry becomes the 1027 top of the stack. 1028 10296. ``DW_OP_rot`` 1030 1031 ``DW_OP_rot`` rotates the first three stack entries. The entry at the top of 1032 the stack becomes the third stack entry, the second entry becomes the top of 1033 the stack, and the third entry becomes the second entry. 1034 1035.. _amdgpu-dwarf-control-flow-operations: 1036 1037Control Flow Operations 1038####################### 1039 1040The following operations provide simple control of the flow of a DWARF operation 1041expression. 1042 10431. ``DW_OP_nop`` 1044 1045 ``DW_OP_nop`` is a place holder. It has no effect on the DWARF stack 1046 entries. 1047 10482. ``DW_OP_le``, ``DW_OP_ge``, ``DW_OP_eq``, ``DW_OP_lt``, ``DW_OP_gt``, 1049 ``DW_OP_ne`` 1050 1051 .. note:: 1052 1053 The same as in DWARF Version 5 section 2.5.1.5. 1054 10553. ``DW_OP_skip`` 1056 1057 ``DW_OP_skip`` is an unconditional branch. Its single operand is a 2-byte 1058 signed integer constant. The 2-byte constant is the number of bytes of the 1059 DWARF expression to skip forward or backward from the current operation, 1060 beginning after the 2-byte constant. 1061 1062 If the updated position is at one past the end of the last operation, then 1063 the operation expression evaluation is complete. 1064 1065 Otherwise, the DWARF expression is ill-formed if the updated operation 1066 position is not in the range of the first to last operation inclusive, or 1067 not at the start of an operation. 1068 10694. ``DW_OP_bra`` 1070 1071 ``DW_OP_bra`` is a conditional branch. Its single operand is a 2-byte signed 1072 integer constant. This operation pops the top of stack. If the value popped 1073 is not the constant 0, the 2-byte constant operand is the number of bytes of 1074 the DWARF operation expression to skip forward or backward from the current 1075 operation, beginning after the 2-byte constant. 1076 1077 If the updated position is at one past the end of the last operation, then 1078 the operation expression evaluation is complete. 1079 1080 Otherwise, the DWARF expression is ill-formed if the updated operation 1081 position is not in the range of the first to last operation inclusive, or 1082 not at the start of an operation. 1083 10845. ``DW_OP_call2, DW_OP_call4, DW_OP_call_ref`` 1085 1086 ``DW_OP_call2``, ``DW_OP_call4``, and ``DW_OP_call_ref`` perform DWARF 1087 procedure calls during evaluation of a DWARF expression. 1088 1089 ``DW_OP_call2`` and ``DW_OP_call4``, have one operand that is, respectively, 1090 a 2-byte or 4-byte unsigned offset DR that represents the byte offset of a 1091 debugging information entry D relative to the beginning of the current 1092 compilation unit. 1093 1094 ``DW_OP_call_ref`` has one operand that is a 4-byte unsigned value in the 1095 32-bit DWARF format, or an 8-byte unsigned value in the 64-bit DWARF format, 1096 that represents the byte offset DR of a debugging information entry D 1097 relative to the beginning of the ``.debug_info`` section that contains the 1098 current compilation unit. D may not be in the current compilation unit. 1099 1100 .. note: 1101 1102 DWARF Version 5 states that DR can be an offset in a ``.debug_info`` 1103 section other than the one that contains the current compilation unit. It 1104 states that relocation of references from one executable or shared object 1105 file to another must be performed by the consumer. But given that DR is 1106 defined as an offset in a ``.debug_info`` section this seems impossible. 1107 If DR was defined as an implementation defined value, then the consumer 1108 could choose to interpret the value in an implementation defined manner to 1109 reference a debug information in another executable or shared object. 1110 1111 In ELF the ``.debug_info`` section is in a non-\ ``PT_LOAD`` segment so 1112 standard dynamic relocations cannot be used. But even if they were loaded 1113 segments and dynamic relocations were used, DR would need to be the 1114 address of D, not an offset in a ``.debug_info`` section. That would also 1115 need DR to be the size of a global address. So it would not be possible to 1116 use the 32-bit DWARF format in a 64-bit global address space. In addition, 1117 the consumer would need to determine what executable or shared object the 1118 relocated address was in so it could determine the containing compilation 1119 unit. 1120 1121 GDB only interprets DR as an offset in the ``.debug_info`` section that 1122 contains the current compilation unit. 1123 1124 This comment also applies to ``DW_OP_implicit_pointer`` and 1125 ``DW_OP_LLVM_aspace_implicit_pointer``. 1126 1127 *Operand interpretation of* ``DW_OP_call2``\ *,* ``DW_OP_call4``\ *, and* 1128 ``DW_OP_call_ref`` *is exactly like that for* ``DW_FORM_ref2``\ *, 1129 ``DW_FORM_ref4``\ *, and* ``DW_FORM_ref_addr``\ *, respectively.* 1130 1131 The call operation is evaluated by: 1132 1133 * If D has a ``DW_AT_location`` attribute that is encoded as a ``exprloc`` 1134 that specifies an operation expression E, then execution of the current 1135 operation expression continues from the first operation of E. Execution 1136 continues until one past the last operation of E is reached, at which 1137 point execution continues with the operation following the call operation. 1138 The operations of E are evaluated with the same current context, except 1139 current compilation unit is the one that contains D and the stack is the 1140 same as that being used by the call operation. After the call operation 1141 has been evaluated, the stack is therefore as it is left by the evaluation 1142 of the operations of E. Since E is evaluated on the same stack as the call 1143 operation, E can use, and/or remove entries already on the stack, and can 1144 add new entries to the stack. 1145 1146 *Values on the stack at the time of the call may be used as parameters by 1147 the called expression and values left on the stack by the called expression 1148 may be used as return values by prior agreement between the calling and 1149 called expressions.* 1150 1151 * If D has a ``DW_AT_location`` attribute that is encoded as a ``loclist`` or 1152 ``loclistsptr``, then the specified location list expression E is 1153 evaluated. The evaluation of E uses the current context, except the result 1154 kind is a location description, the compilation unit is the one that 1155 contains D, and the initial stack is empty. The location description 1156 result is pushed on the stack. 1157 1158 .. note:: 1159 1160 This rule avoids having to define how to execute a matched location list 1161 entry operation expression on the same stack as the call when there are 1162 multiple matches. But it allows the call to obtain the location 1163 description for a variable or formal parameter which may use a location 1164 list expression. 1165 1166 An alternative is to treat the case when D has a ``DW_AT_location`` 1167 attribute that is encoded as a ``loclist`` or ``loclistsptr``, and the 1168 specified location list expression E' matches a single location list 1169 entry with operation expression E, the same as the ``exprloc`` case and 1170 evaluate on the same stack. 1171 1172 But this is not attractive as if the attribute is for a variable that 1173 happens to end with a non-singleton stack, it will not simply put a 1174 location description on the stack. Presumably the intent of using 1175 ``DW_OP_call*`` on a variable or formal parameter debugger information 1176 entry is to push just one location description on the stack. That 1177 location description may have more than one single location description. 1178 1179 The previous rule for ``exprloc`` also has the same problem as normally 1180 a variable or formal parameter location expression may leave multiple 1181 entries on the stack and only return the top entry. 1182 1183 GDB implements ``DW_OP_call*`` by always executing E on the same stack. 1184 If the location list has multiple matching entries, it simply picks the 1185 first one and ignores the rest. This seems fundamentally at odds with 1186 the desire to supporting multiple places for variables. 1187 1188 So, it feels like ``DW_OP_call*`` should both support pushing a location 1189 description on the stack for a variable or formal parameter, and also 1190 support being able to execute an operation expression on the same stack. 1191 Being able to specify a different operation expression for different 1192 program locations seems a desirable feature to retain. 1193 1194 A solution to that is to have a distinct ``DW_AT_LLVM_proc`` attribute 1195 for the ``DW_TAG_dwarf_procedure`` debugging information entry. Then the 1196 ``DW_AT_location`` attribute expression is always executed separately 1197 and pushes a location description (that may have multiple single 1198 location descriptions), and the ``DW_AT_LLVM_proc`` attribute expression 1199 is always executed on the same stack and can leave anything on the 1200 stack. 1201 1202 The ``DW_AT_LLVM_proc`` attribute could have the new classes 1203 ``exprproc``, ``loclistproc``, and ``loclistsptrproc`` to indicate that 1204 the expression is executed on the same stack. ``exprproc`` is the same 1205 encoding as ``exprloc``. ``loclistproc`` and ``loclistsptrproc`` are the 1206 same encoding as their non-\ ``proc`` counterparts, except the DWARF is 1207 ill-formed if the location list does not match exactly one location list 1208 entry and a default entry is required. These forms indicate explicitly 1209 that the matched single operation expression must be executed on the 1210 same stack. This is better than ad hoc special rules for ``loclistproc`` 1211 and ``loclistsptrproc`` which are currently clearly defined to always 1212 return a location description. The producer then explicitly indicates 1213 the intent through the attribute classes. 1214 1215 Such a change would be a breaking change for how GDB implements 1216 ``DW_OP_call*``. However, are the breaking cases actually occurring in 1217 practice? GDB could implement the current approach for DWARF Version 5, 1218 and the new semantics for DWARF Version 6 which has been done for some 1219 other features. 1220 1221 Another option is to limit the execution to be on the same stack only to 1222 the evaluation of an expression E that is the value of a 1223 ``DW_AT_location`` attribute of a ``DW_TAG_dwarf_procedure`` debugging 1224 information entry. The DWARF would be ill-formed if E is a location list 1225 expression that does not match exactly one location list entry. In all 1226 other cases the evaluation of an expression E that is the value of a 1227 ``DW_AT_location`` attribute would evaluate E with the current context, 1228 except the result kind is a location description, the compilation unit 1229 is the one that contains D, and the initial stack is empty. The location 1230 description result is pushed on the stack. 1231 1232 * If D has a ``DW_AT_const_value`` attribute with a value V, then it is as 1233 if a ``DW_OP_implicit_value V`` operation was executed. 1234 1235 *This allows a call operation to be used to compute the location 1236 description for any variable or formal parameter regardless of whether the 1237 producer has optimized it to a constant. This is consistent with the 1238 ``DW_OP_implicit_pointer`` operation.* 1239 1240 .. note:: 1241 1242 Alternatively, could deprecate using ``DW_AT_const_value`` for 1243 ``DW_TAG_variable`` and ``DW_TAG_formal_parameter`` debugger information 1244 entries that are constants and instead use ``DW_AT_location`` with an 1245 operation expression that results in a location description with one 1246 implicit location description. Then this rule would not be required. 1247 1248 * Otherwise, there is no effect and no changes are made to the stack. 1249 1250 .. note:: 1251 1252 In DWARF Version 5, if D does not have a ``DW_AT_location`` then 1253 ``DW_OP_call*`` is defined to have no effect. It is unclear that this is 1254 the right definition as a producer should be able to rely on using 1255 ``DW_OP_call*`` to get a location description for any non-\ 1256 ``DW_TAG_dwarf_procedure`` debugging information entries. Also, the 1257 producer should not be creating DWARF with ``DW_OP_call*`` to a 1258 ``DW_TAG_dwarf_procedure`` that does not have a ``DW_AT_location`` 1259 attribute. So, should this case be defined as an ill-formed DWARF 1260 expression? 1261 1262 *The* ``DW_TAG_dwarf_procedure`` *debugging information entry can be used to 1263 define DWARF procedures that can be called.* 1264 1265.. _amdgpu-dwarf-value-operations: 1266 1267Value Operations 1268################ 1269 1270This section describes the operations that push values on the stack. 1271 1272Each value stack entry has a type and a literal value and can represent a 1273literal value of any supported base type of the target architecture. The base 1274type specifies the size, encoding, and endianity of the literal value. 1275 1276The base type of value stack entries can be the distinguished generic type. 1277 1278.. _amdgpu-dwarf-literal-operations: 1279 1280Literal Operations 1281^^^^^^^^^^^^^^^^^^ 1282 1283The following operations all push a literal value onto the DWARF stack. 1284 1285Operations other than ``DW_OP_const_type`` push a value V with the generic type. 1286If V is larger than the generic type, then V is truncated to the generic type 1287size and the low-order bits used. 1288 12891. ``DW_OP_lit0``, ``DW_OP_lit1``, ..., ``DW_OP_lit31`` 1290 1291 ``DW_OP_lit<N>`` operations encode an unsigned literal value N from 0 1292 through 31, inclusive. They push the value N with the generic type. 1293 12942. ``DW_OP_const1u``, ``DW_OP_const2u``, ``DW_OP_const4u``, ``DW_OP_const8u`` 1295 1296 ``DW_OP_const<N>u`` operations have a single operand that is a 1, 2, 4, or 1297 8-byte unsigned integer constant U, respectively. They push the value U with 1298 the generic type. 1299 13003. ``DW_OP_const1s``, ``DW_OP_const2s``, ``DW_OP_const4s``, ``DW_OP_const8s`` 1301 1302 ``DW_OP_const<N>s`` operations have a single operand that is a 1, 2, 4, or 1303 8-byte signed integer constant S, respectively. They push the value S with 1304 the generic type. 1305 13064. ``DW_OP_constu`` 1307 1308 ``DW_OP_constu`` has a single unsigned LEB128 integer operand N. It pushes 1309 the value N with the generic type. 1310 13115. ``DW_OP_consts`` 1312 1313 ``DW_OP_consts`` has a single signed LEB128 integer operand N. It pushes the 1314 value N with the generic type. 1315 13166. ``DW_OP_constx`` 1317 1318 ``DW_OP_constx`` has a single unsigned LEB128 integer operand that 1319 represents a zero-based index into the ``.debug_addr`` section relative to 1320 the value of the ``DW_AT_addr_base`` attribute of the associated compilation 1321 unit. The value N in the ``.debug_addr`` section has the size of the generic 1322 type. It pushes the value N with the generic type. 1323 1324 *The* ``DW_OP_constx`` *operation is provided for constants that require 1325 link-time relocation but should not be interpreted by the consumer as a 1326 relocatable address (for example, offsets to thread-local storage).* 1327 13289. ``DW_OP_const_type`` 1329 1330 ``DW_OP_const_type`` has three operands. The first is an unsigned LEB128 1331 integer DR that represents the byte offset of a debugging information entry 1332 D relative to the beginning of the current compilation unit, that provides 1333 the type T of the constant value. The second is a 1-byte unsigned integral 1334 constant S. The third is a block of bytes B, with a length equal to S. 1335 1336 TS is the bit size of the type T. The least significant TS bits of B are 1337 interpreted as a value V of the type D. It pushes the value V with the type 1338 D. 1339 1340 The DWARF is ill-formed if D is not a ``DW_TAG_base_type`` debugging 1341 information entry in the current compilation unit, or if TS divided by 8 1342 (the byte size) and rounded up to a whole number is not equal to S. 1343 1344 *While the size of the byte block B can be inferred from the type D 1345 definition, it is encoded explicitly into the operation so that the 1346 operation can be parsed easily without reference to the* ``.debug_info`` 1347 *section.* 1348 134910. ``DW_OP_LLVM_push_lane`` *New* 1350 1351 ``DW_OP_LLVM_push_lane`` pushes the target architecture lane identifier of 1352 the current lane as a value with the generic type. 1353 1354 *For languages that are implemented using a SIMD or SIMT execution model, 1355 this is the lane number that corresponds to the source language thread of 1356 execution upon which the user is focused.* 1357 1358.. _amdgpu-dwarf-arithmetic-logical-operations: 1359 1360Arithmetic and Logical Operations 1361^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1362 1363.. note:: 1364 1365 This section is the same as DWARF Version 5 section 2.5.1.4. 1366 1367.. _amdgpu-dwarf-type-conversions-operations: 1368 1369Type Conversion Operations 1370^^^^^^^^^^^^^^^^^^^^^^^^^^ 1371 1372.. note:: 1373 1374 This section is the same as DWARF Version 5 section 2.5.1.6. 1375 1376.. _amdgpu-dwarf-general-operations: 1377 1378Special Value Operations 1379^^^^^^^^^^^^^^^^^^^^^^^^ 1380 1381There are these special value operations currently defined: 1382 13831. ``DW_OP_regval_type`` 1384 1385 ``DW_OP_regval_type`` has two operands. The first is an unsigned LEB128 1386 integer that represents a register number R. The second is an unsigned 1387 LEB128 integer DR that represents the byte offset of a debugging information 1388 entry D relative to the beginning of the current compilation unit, that 1389 provides the type T of the register value. 1390 1391 The operation is equivalent to performing ``DW_OP_regx R; DW_OP_deref_type 1392 DR``. 1393 1394 .. note:: 1395 1396 Should DWARF allow the type T to be a larger size than the size of the 1397 register R? Restricting a larger bit size avoids any issue of conversion 1398 as the, possibly truncated, bit contents of the register is simply 1399 interpreted as a value of T. If a conversion is wanted it can be done 1400 explicitly using a ``DW_OP_convert`` operation. 1401 1402 GDB has a per register hook that allows a target specific conversion on a 1403 register by register basis. It defaults to truncation of bigger registers. 1404 Removing use of the target hook does not cause any test failures in common 1405 architectures. If the compiler for a target architecture did want some 1406 form of conversion, including a larger result type, it could always 1407 explicitly used the ``DW_OP_convert`` operation. 1408 1409 If T is a larger type than the register size, then the default GDB 1410 register hook reads bytes from the next register (or reads out of bounds 1411 for the last register!). Removing use of the target hook does not cause 1412 any test failures in common architectures (except an illegal hand written 1413 assembly test). If a target architecture requires this behavior, these 1414 extensions allow a composite location description to be used to combine 1415 multiple registers. 1416 14172. ``DW_OP_deref`` 1418 1419 S is the bit size of the generic type divided by 8 (the byte size) and 1420 rounded up to a whole number. DR is the offset of a hypothetical debug 1421 information entry D in the current compilation unit for a base type of the 1422 generic type. 1423 1424 The operation is equivalent to performing ``DW_OP_deref_type S, DR``. 1425 14263. ``DW_OP_deref_size`` 1427 1428 ``DW_OP_deref_size`` has a single 1-byte unsigned integral constant that 1429 represents a byte result size S. 1430 1431 TS is the smaller of the generic type bit size and S scaled by 8 (the byte 1432 size). If TS is smaller than the generic type bit size then T is an unsigned 1433 integral type of bit size TS, otherwise T is the generic type. DR is the 1434 offset of a hypothetical debug information entry D in the current 1435 compilation unit for a base type T. 1436 1437 .. note:: 1438 1439 Truncating the value when S is larger than the generic type matches what 1440 GDB does. This allows the generic type size to not be an integral byte 1441 size. It does allow S to be arbitrarily large. Should S be restricted to 1442 the size of the generic type rounded up to a multiple of 8? 1443 1444 The operation is equivalent to performing ``DW_OP_deref_type S, DR``, except 1445 if T is not the generic type, the value V pushed is zero-extended to the 1446 generic type bit size and its type changed to the generic type. 1447 14484. ``DW_OP_deref_type`` 1449 1450 ``DW_OP_deref_type`` has two operands. The first is a 1-byte unsigned 1451 integral constant S. The second is an unsigned LEB128 integer DR that 1452 represents the byte offset of a debugging information entry D relative to 1453 the beginning of the current compilation unit, that provides the type T of 1454 the result value. 1455 1456 TS is the bit size of the type T. 1457 1458 *While the size of the pushed value V can be inferred from the type T, it is 1459 encoded explicitly as the operand S so that the operation can be parsed 1460 easily without reference to the* ``.debug_info`` *section.* 1461 1462 .. note:: 1463 1464 It is unclear why the operand S is needed. Unlike ``DW_OP_const_type``, 1465 the size is not needed for parsing. Any evaluation needs to get the base 1466 type T to push with the value to know its encoding and bit size. 1467 1468 It pops one stack entry that must be a location description L. 1469 1470 A value V of TS bits is retrieved from the location storage LS specified by 1471 one of the single location descriptions SL of L. 1472 1473 *If L, or the location description of any composite location description 1474 part that is a subcomponent of L, has more than one single location 1475 description, then any one of them can be selected as they are required to 1476 all have the same value. For any single location description SL, bits are 1477 retrieved from the associated storage location starting at the bit offset 1478 specified by SL. For a composite location description, the retrieved bits 1479 are the concatenation of the N bits from each composite location part PL, 1480 where N is limited to the size of PL.* 1481 1482 V is pushed on the stack with the type T. 1483 1484 .. note:: 1485 1486 This definition makes it an evaluation error if L is a register location 1487 description that has less than TS bits remaining in the register storage. 1488 Particularly since these extensions extend location descriptions to have 1489 a bit offset, it would be odd to define this as performing sign extension 1490 based on the type, or be target architecture dependent, as the number of 1491 remaining bits could be any number. This matches the GDB implementation 1492 for ``DW_OP_deref_type``. 1493 1494 These extensions define ``DW_OP_*breg*`` in terms of 1495 ``DW_OP_regval_type``. ``DW_OP_regval_type`` is defined in terms of 1496 ``DW_OP_regx``, which uses a 0 bit offset, and ``DW_OP_deref_type``. 1497 Therefore, it requires the register size to be greater or equal to the 1498 address size of the address space. This matches the GDB implementation for 1499 ``DW_OP_*breg*``. 1500 1501 The DWARF is ill-formed if D is not in the current compilation unit, D is 1502 not a ``DW_TAG_base_type`` debugging information entry, or if TS divided by 1503 8 (the byte size) and rounded up to a whole number is not equal to S. 1504 1505 .. note:: 1506 1507 This definition allows the base type to be a bit size since there seems no 1508 reason to restrict it. 1509 1510 It is an evaluation error if any bit of the value is retrieved from the 1511 undefined location storage or the offset of any bit exceeds the size of the 1512 location storage LS specified by any single location description SL of L. 1513 1514 See :ref:`amdgpu-dwarf-implicit-location-descriptions` for special rules 1515 concerning implicit location descriptions created by the 1516 ``DW_OP_implicit_pointer`` and ``DW_OP_LLVM_implicit_aspace_pointer`` 1517 operations. 1518 15195. ``DW_OP_xderef`` *Deprecated* 1520 1521 ``DW_OP_xderef`` pops two stack entries. The first must be an integral type 1522 value that represents an address A. The second must be an integral type 1523 value that represents a target architecture specific address space 1524 identifier AS. 1525 1526 The operation is equivalent to performing ``DW_OP_swap; 1527 DW_OP_LLVM_form_aspace_address; DW_OP_deref``. The value V retrieved is left 1528 on the stack with the generic type. 1529 1530 *This operation is deprecated as the* ``DW_OP_LLVM_form_aspace_address`` 1531 *operation can be used and provides greater expressiveness.* 1532 15336. ``DW_OP_xderef_size`` *Deprecated* 1534 1535 ``DW_OP_xderef_size`` has a single 1-byte unsigned integral constant that 1536 represents a byte result size S. 1537 1538 It pops two stack entries. The first must be an integral type value that 1539 represents an address A. The second must be an integral type value that 1540 represents a target architecture specific address space identifier AS. 1541 1542 The operation is equivalent to performing ``DW_OP_swap; 1543 DW_OP_LLVM_form_aspace_address; DW_OP_deref_size S``. The zero-extended 1544 value V retrieved is left on the stack with the generic type. 1545 1546 *This operation is deprecated as the* ``DW_OP_LLVM_form_aspace_address`` 1547 *operation can be used and provides greater expressiveness.* 1548 15497. ``DW_OP_xderef_type`` *Deprecated* 1550 1551 ``DW_OP_xderef_type`` has two operands. The first is a 1-byte unsigned 1552 integral constant S. The second operand is an unsigned LEB128 integer DR 1553 that represents the byte offset of a debugging information entry D relative 1554 to the beginning of the current compilation unit, that provides the type T 1555 of the result value. 1556 1557 It pops two stack entries. The first must be an integral type value that 1558 represents an address A. The second must be an integral type value that 1559 represents a target architecture specific address space identifier AS. 1560 1561 The operation is equivalent to performing ``DW_OP_swap; 1562 DW_OP_LLVM_form_aspace_address; DW_OP_deref_type S R``. The value V 1563 retrieved is left on the stack with the type D. 1564 1565 *This operation is deprecated as the* ``DW_OP_LLVM_form_aspace_address`` 1566 *operation can be used and provides greater expressiveness.* 1567 15688. ``DW_OP_entry_value`` *Deprecated* 1569 1570 ``DW_OP_entry_value`` pushes the value of an expression that is evaluated in 1571 the context of the calling frame. 1572 1573 *It may be used to determine the value of arguments on entry to the current 1574 call frame provided they are not clobbered.* 1575 1576 It has two operands. The first is an unsigned LEB128 integer S. The second 1577 is a block of bytes, with a length equal S, interpreted as a DWARF 1578 operation expression E. 1579 1580 E is evaluated with the current context, except the result kind is 1581 unspecified, the call frame is the one that called the current frame, the 1582 program location is the call site in the calling frame, the object is 1583 unspecified, and the initial stack is empty. The calling frame information 1584 is obtained by virtually unwinding the current call frame using the call 1585 frame information (see :ref:`amdgpu-dwarf-call-frame-information`). 1586 1587 If the result of E is a location description L (see 1588 :ref:`amdgpu-dwarf-register-location-descriptions`), and the last operation 1589 executed by E is a ``DW_OP_reg*`` for register R with a target architecture 1590 specific base type of T, then the contents of the register are retrieved as 1591 if a ``DW_OP_deref_type DR`` operation was performed where DR is the offset 1592 of a hypothetical debug information entry in the current compilation unit 1593 for T. The resulting value V s pushed on the stack. 1594 1595 *Using* ``DW_OP_reg*`` *provides a more compact form for the case where the 1596 value was in a register on entry to the subprogram.* 1597 1598 .. note: 1599 1600 It is unclear how this provides a more compact expression, as 1601 ``DW_OP_regval_type`` could be used which is marginally larger. 1602 1603 If the result of E is a value V, then V is pushed on the stack. 1604 1605 Otherwise, the DWARF expression is ill-formed. 1606 1607 *The* ``DW_OP_entry_value`` *operation is deprecated as its main usage is 1608 provided by other means. DWARF Version 5 added the* 1609 ``DW_TAG_call_site_parameter`` *debugger information entry for call sites 1610 that has* ``DW_AT_call_value``\ *,* ``DW_AT_call_data_location``\ *, and* 1611 ``DW_AT_call_data_value`` *attributes that provide DWARF expressions to 1612 compute actual parameter values at the time of the call, and requires the 1613 producer to ensure the expressions are valid to evaluate even when virtually 1614 unwound. The* ``DW_OP_LLVM_call_frame_entry_reg`` *operation provides access 1615 to registers in the virtually unwound calling frame.* 1616 1617 .. note:: 1618 1619 GDB only implements ``DW_OP_entry_value`` when E is exactly 1620 ``DW_OP_reg*`` or ``DW_OP_breg*; DW_OP_deref*``. 1621 1622.. _amdgpu-dwarf-location-description-operations: 1623 1624Location Description Operations 1625############################### 1626 1627This section describes the operations that push location descriptions on the 1628stack. 1629 1630General Location Description Operations 1631^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1632 16331. ``DW_OP_LLVM_offset`` *New* 1634 1635 ``DW_OP_LLVM_offset`` pops two stack entries. The first must be an integral 1636 type value that represents a byte displacement B. The second must be a 1637 location description L. 1638 1639 It adds the value of B scaled by 8 (the byte size) to the bit offset of each 1640 single location description SL of L, and pushes the updated L. 1641 1642 It is an evaluation error if the updated bit offset of any SL is less than 0 1643 or greater than or equal to the size of the location storage specified by 1644 SL. 1645 16462. ``DW_OP_LLVM_offset_uconst`` *New* 1647 1648 ``DW_OP_LLVM_offset_uconst`` has a single unsigned LEB128 integer operand 1649 that represents a byte displacement B. 1650 1651 The operation is equivalent to performing ``DW_OP_constu B; 1652 DW_OP_LLVM_offset``. 1653 1654 *This operation is supplied specifically to be able to encode more field 1655 displacements in two bytes than can be done with* ``DW_OP_lit*; 1656 DW_OP_LLVM_offset``\ *.* 1657 1658 .. note:: 1659 1660 Should this be named ``DW_OP_LLVM_offset_uconst`` to match 1661 ``DW_OP_plus_uconst``, or ``DW_OP_LLVM_offset_constu`` to match 1662 ``DW_OP_constu``? 1663 16643. ``DW_OP_LLVM_bit_offset`` *New* 1665 1666 ``DW_OP_LLVM_bit_offset`` pops two stack entries. The first must be an 1667 integral type value that represents a bit displacement B. The second must be 1668 a location description L. 1669 1670 It adds the value of B to the bit offset of each single location description 1671 SL of L, and pushes the updated L. 1672 1673 It is an evaluation error if the updated bit offset of any SL is less than 0 1674 or greater than or equal to the size of the location storage specified by 1675 SL. 1676 16774. ``DW_OP_push_object_address`` 1678 1679 ``DW_OP_push_object_address`` pushes the location description L of the 1680 current object. 1681 1682 *This object may correspond to an independent variable that is part of a 1683 user presented expression that is being evaluated. The object location 1684 description may be determined from the variable's own debugging information 1685 entry or it may be a component of an array, structure, or class whose 1686 address has been dynamically determined by an earlier step during user 1687 expression evaluation.* 1688 1689 *This operation provides explicit functionality (especially for arrays 1690 involving descriptions) that is analogous to the implicit push of the base 1691 location description of a structure prior to evaluation of a 1692 ``DW_AT_data_member_location`` to access a data member of a structure.* 1693 1694 .. note:: 1695 1696 This operation could be removed and the object location description 1697 specified as the initial stack as for ``DW_AT_data_member_location``. 1698 1699 The only attribute that specifies a current object is 1700 ``DW_AT_data_location`` so the non-normative text seems to overstate how 1701 this is being used. Or are there other attributes that need to state they 1702 pass an object? 1703 17045. ``DW_OP_LLVM_call_frame_entry_reg`` *New* 1705 1706 ``DW_OP_LLVM_call_frame_entry_reg`` has a single unsigned LEB128 integer 1707 operand that represents a target architecture register number R. 1708 1709 It pushes a location description L that holds the value of register R on 1710 entry to the current subprogram as defined by the call frame information 1711 (see :ref:`amdgpu-dwarf-call-frame-information`). 1712 1713 *If there is no call frame information defined, then the default rules for 1714 the target architecture are used. If the register rule is* undefined\ *, then 1715 the undefined location description is pushed. If the register rule is* same 1716 value\ *, then a register location description for R is pushed.* 1717 1718.. _amdgpu-dwarf-undefined-location-description-operations: 1719 1720Undefined Location Description Operations 1721^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1722 1723*The undefined location storage represents a piece or all of an object that is 1724present in the source but not in the object code (perhaps due to optimization). 1725Neither reading nor writing to the undefined location storage is meaningful.* 1726 1727An undefined location description specifies the undefined location storage. 1728There is no concept of the size of the undefined location storage, nor of a bit 1729offset for an undefined location description. The ``DW_OP_LLVM_*offset`` 1730operations leave an undefined location description unchanged. The 1731``DW_OP_*piece`` operations can explicitly or implicitly specify an undefined 1732location description, allowing any size and offset to be specified, and results 1733in a part with all undefined bits. 1734 17351. ``DW_OP_LLVM_undefined`` *New* 1736 1737 ``DW_OP_LLVM_undefined`` pushes a location description L that comprises one 1738 undefined location description SL. 1739 1740.. _amdgpu-dwarf-memory-location-description-operations: 1741 1742Memory Location Description Operations 1743^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1744 1745Each of the target architecture specific address spaces has a corresponding 1746memory location storage that denotes the linear addressable memory of that 1747address space. The size of each memory location storage corresponds to the range 1748of the addresses in the corresponding address space. 1749 1750*It is target architecture defined how address space location storage maps to 1751target architecture physical memory. For example, they may be independent 1752memory, or more than one location storage may alias the same physical memory 1753possibly at different offsets and with different interleaving. The mapping may 1754also be dictated by the source language address classes.* 1755 1756A memory location description specifies a memory location storage. The bit 1757offset corresponds to a bit position within a byte of the memory. Bits accessed 1758using a memory location description, access the corresponding target 1759architecture memory starting at the bit position within the byte specified by 1760the bit offset. 1761 1762A memory location description that has a bit offset that is a multiple of 8 (the 1763byte size) is defined to be a byte address memory location description. It has a 1764memory byte address A that is equal to the bit offset divided by 8. 1765 1766A memory location description that does not have a bit offset that is a multiple 1767of 8 (the byte size) is defined to be a bit field memory location description. 1768It has a bit position B equal to the bit offset modulo 8, and a memory byte 1769address A equal to the bit offset minus B that is then divided by 8. 1770 1771The address space AS of a memory location description is defined to be the 1772address space that corresponds to the memory location storage associated with 1773the memory location description. 1774 1775A location description that is comprised of one byte address memory location 1776description SL is defined to be a memory byte address location description. It 1777has a byte address equal to A and an address space equal to AS of the 1778corresponding SL. 1779 1780``DW_ASPACE_none`` is defined as the target architecture default address space. 1781 1782If a stack entry is required to be a location description, but it is a value V 1783with the generic type, then it is implicitly converted to a location description 1784L with one memory location description SL. SL specifies the memory location 1785storage that corresponds to the target architecture default address space with a 1786bit offset equal to V scaled by 8 (the byte size). 1787 1788.. note:: 1789 1790 If it is wanted to allow any integral type value to be implicitly converted to 1791 a memory location description in the target architecture default address 1792 space: 1793 1794 If a stack entry is required to be a location description, but is a value V 1795 with an integral type, then it is implicitly converted to a location 1796 description L with a one memory location description SL. If the type size of 1797 V is less than the generic type size, then the value V is zero extended to 1798 the size of the generic type. The least significant generic type size bits 1799 are treated as a twos-complement unsigned value to be used as an address A. 1800 SL specifies memory location storage corresponding to the target 1801 architecture default address space with a bit offset equal to A scaled by 8 1802 (the byte size). 1803 1804 The implicit conversion could also be defined as target architecture specific. 1805 For example, GDB checks if V is an integral type. If it is not it gives an 1806 error. Otherwise, GDB zero-extends V to 64 bits. If the GDB target defines a 1807 hook function, then it is called. The target specific hook function can modify 1808 the 64-bit value, possibly sign extending based on the original value type. 1809 Finally, GDB treats the 64-bit value V as a memory location address. 1810 1811If a stack entry is required to be a location description, but it is an implicit 1812pointer value IPV with the target architecture default address space, then it is 1813implicitly converted to a location description with one single location 1814description specified by IPV. See 1815:ref:`amdgpu-dwarf-implicit-location-descriptions`. 1816 1817.. note:: 1818 1819 Is this rule required for DWARF Version 5 backwards compatibility? If not, it 1820 can be eliminated, and the producer can use 1821 ``DW_OP_LLVM_form_aspace_address``. 1822 1823If a stack entry is required to be a value, but it is a location description L 1824with one memory location description SL in the target architecture default 1825address space with a bit offset B that is a multiple of 8, then it is implicitly 1826converted to a value equal to B divided by 8 (the byte size) with the generic 1827type. 1828 18291. ``DW_OP_addr`` 1830 1831 ``DW_OP_addr`` has a single byte constant value operand, which has the size 1832 of the generic type, that represents an address A. 1833 1834 It pushes a location description L with one memory location description SL 1835 on the stack. SL specifies the memory location storage corresponding to the 1836 target architecture default address space with a bit offset equal to A 1837 scaled by 8 (the byte size). 1838 1839 *If the DWARF is part of a code object, then A may need to be relocated. For 1840 example, in the ELF code object format, A must be adjusted by the difference 1841 between the ELF segment virtual address and the virtual address at which the 1842 segment is loaded.* 1843 18442. ``DW_OP_addrx`` 1845 1846 ``DW_OP_addrx`` has a single unsigned LEB128 integer operand that represents 1847 a zero-based index into the ``.debug_addr`` section relative to the value of 1848 the ``DW_AT_addr_base`` attribute of the associated compilation unit. The 1849 address value A in the ``.debug_addr`` section has the size of the generic 1850 type. 1851 1852 It pushes a location description L with one memory location description SL 1853 on the stack. SL specifies the memory location storage corresponding to the 1854 target architecture default address space with a bit offset equal to A 1855 scaled by 8 (the byte size). 1856 1857 *If the DWARF is part of a code object, then A may need to be relocated. For 1858 example, in the ELF code object format, A must be adjusted by the difference 1859 between the ELF segment virtual address and the virtual address at which the 1860 segment is loaded.* 1861 18623. ``DW_OP_LLVM_form_aspace_address`` *New* 1863 1864 ``DW_OP_LLVM_form_aspace_address`` pops top two stack entries. The first 1865 must be an integral type value that represents a target architecture 1866 specific address space identifier AS. The second must be an integral type 1867 value that represents an address A. 1868 1869 The address size S is defined as the address bit size of the target 1870 architecture specific address space that corresponds to AS. 1871 1872 A is adjusted to S bits by zero extending if necessary, and then treating the 1873 least significant S bits as a twos-complement unsigned value A'. 1874 1875 It pushes a location description L with one memory location description SL 1876 on the stack. SL specifies the memory location storage LS that corresponds 1877 to AS with a bit offset equal to A' scaled by 8 (the byte size). 1878 1879 If AS is an address space that is specific to context elements, then LS 1880 corresponds to the location storage associated with the current context. 1881 1882 *For example, if AS is for per thread storage then LS is the location 1883 storage for the current thread. For languages that are implemented using a 1884 SIMD or SIMT execution model, then if AS is for per lane storage then LS is 1885 the location storage for the current lane of the current thread. Therefore, 1886 if L is accessed by an operation, the location storage selected when the 1887 location description was created is accessed, and not the location storage 1888 associated with the current context of the access operation.* 1889 1890 The DWARF expression is ill-formed if AS is not one of the values defined by 1891 the target architecture specific ``DW_ASPACE_*`` values. 1892 1893 See :ref:`amdgpu-dwarf-implicit-location-descriptions` for special rules 1894 concerning implicit pointer values produced by dereferencing implicit 1895 location descriptions created by the ``DW_OP_implicit_pointer`` and 1896 ``DW_OP_LLVM_implicit_aspace_pointer`` operations. 1897 18984. ``DW_OP_form_tls_address`` 1899 1900 ``DW_OP_form_tls_address`` pops one stack entry that must be an integral 1901 type value and treats it as a thread-local storage address TA. 1902 1903 It pushes a location description L with one memory location description SL 1904 on the stack. SL is the target architecture specific memory location 1905 description that corresponds to the thread-local storage address TA. 1906 1907 The meaning of the thread-local storage address TA is defined by the 1908 run-time environment. If the run-time environment supports multiple 1909 thread-local storage blocks for a single thread, then the block 1910 corresponding to the executable or shared library containing this DWARF 1911 expression is used. 1912 1913 *Some implementations of C, C++, Fortran, and other languages support a 1914 thread-local storage class. Variables with this storage class have distinct 1915 values and addresses in distinct threads, much as automatic variables have 1916 distinct values and addresses in each subprogram invocation. Typically, 1917 there is a single block of storage containing all thread-local variables 1918 declared in the main executable, and a separate block for the variables 1919 declared in each shared library. Each thread-local variable can then be 1920 accessed in its block using an identifier. This identifier is typically a 1921 byte offset into the block and pushed onto the DWARF stack by one of the* 1922 ``DW_OP_const*`` *operations prior to the* ``DW_OP_form_tls_address`` 1923 *operation. Computing the address of the appropriate block can be complex 1924 (in some cases, the compiler emits a function call to do it), and difficult 1925 to describe using ordinary DWARF location descriptions. Instead of forcing 1926 complex thread-local storage calculations into the DWARF expressions, the* 1927 ``DW_OP_form_tls_address`` *allows the consumer to perform the computation 1928 based on the target architecture specific run-time environment.* 1929 19305. ``DW_OP_call_frame_cfa`` 1931 1932 ``DW_OP_call_frame_cfa`` pushes the location description L of the Canonical 1933 Frame Address (CFA) of the current subprogram, obtained from the call frame 1934 information on the stack. See :ref:`amdgpu-dwarf-call-frame-information`. 1935 1936 *Although the value of the* ``DW_AT_frame_base`` *attribute of the debugger 1937 information entry corresponding to the current subprogram can be computed 1938 using a location list expression, in some cases this would require an 1939 extensive location list because the values of the registers used in 1940 computing the CFA change during a subprogram execution. If the call frame 1941 information is present, then it already encodes such changes, and it is 1942 space efficient to reference that using the* ``DW_OP_call_frame_cfa`` 1943 *operation.* 1944 19456. ``DW_OP_fbreg`` 1946 1947 ``DW_OP_fbreg`` has a single signed LEB128 integer operand that represents a 1948 byte displacement B. 1949 1950 The location description L for the *frame base* of the current subprogram is 1951 obtained from the ``DW_AT_frame_base`` attribute of the debugger information 1952 entry corresponding to the current subprogram as described in 1953 :ref:`amdgpu-dwarf-debugging-information-entry-attributes`. 1954 1955 The location description L is updated as if the ``DW_OP_LLVM_offset_uconst 1956 B`` operation was applied. The updated L is pushed on the stack. 1957 19587. ``DW_OP_breg0``, ``DW_OP_breg1``, ..., ``DW_OP_breg31`` 1959 1960 The ``DW_OP_breg<N>`` operations encode the numbers of up to 32 registers, 1961 numbered from 0 through 31, inclusive. The register number R corresponds to 1962 the N in the operation name. 1963 1964 They have a single signed LEB128 integer operand that represents a byte 1965 displacement B. 1966 1967 The address space identifier AS is defined as the one corresponding to the 1968 target architecture specific default address space. 1969 1970 The address size S is defined as the address bit size of the target 1971 architecture specific address space corresponding to AS. 1972 1973 The contents of the register specified by R are retrieved as if a 1974 ``DW_OP_regval_type R, DR`` operation was performed where DR is the offset 1975 of a hypothetical debug information entry in the current compilation unit 1976 for an unsigned integral base type of size S bits. B is added and the least 1977 significant S bits are treated as an unsigned value to be used as an address 1978 A. 1979 1980 They push a location description L comprising one memory location 1981 description LS on the stack. LS specifies the memory location storage that 1982 corresponds to AS with a bit offset equal to A scaled by 8 (the byte size). 1983 19848. ``DW_OP_bregx`` 1985 1986 ``DW_OP_bregx`` has two operands. The first is an unsigned LEB128 integer 1987 that represents a register number R. The second is a signed LEB128 1988 integer that represents a byte displacement B. 1989 1990 The action is the same as for ``DW_OP_breg<N>``, except that R is used as 1991 the register number and B is used as the byte displacement. 1992 19939. ``DW_OP_LLVM_aspace_bregx`` *New* 1994 1995 ``DW_OP_LLVM_aspace_bregx`` has two operands. The first is an unsigned 1996 LEB128 integer that represents a register number R. The second is a signed 1997 LEB128 integer that represents a byte displacement B. It pops one stack 1998 entry that is required to be an integral type value that represents a target 1999 architecture specific address space identifier AS. 2000 2001 The action is the same as for ``DW_OP_breg<N>``, except that R is used as 2002 the register number, B is used as the byte displacement, and AS is used as 2003 the address space identifier. 2004 2005 The DWARF expression is ill-formed if AS is not one of the values defined by 2006 the target architecture specific ``DW_ASPACE_*`` values. 2007 2008 .. note:: 2009 2010 Could also consider adding ``DW_OP_aspace_breg0, DW_OP_aspace_breg1, ..., 2011 DW_OP_aspace_bref31`` which would save encoding size. 2012 2013.. _amdgpu-dwarf-register-location-descriptions: 2014 2015Register Location Description Operations 2016^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2017 2018There is a register location storage that corresponds to each of the target 2019architecture registers. The size of each register location storage corresponds 2020to the size of the corresponding target architecture register. 2021 2022A register location description specifies a register location storage. The bit 2023offset corresponds to a bit position within the register. Bits accessed using a 2024register location description access the corresponding target architecture 2025register starting at the specified bit offset. 2026 20271. ``DW_OP_reg0``, ``DW_OP_reg1``, ..., ``DW_OP_reg31`` 2028 2029 ``DW_OP_reg<N>`` operations encode the numbers of up to 32 registers, 2030 numbered from 0 through 31, inclusive. The target architecture register 2031 number R corresponds to the N in the operation name. 2032 2033 The operation is equivalent to performing ``DW_OP_regx R``. 2034 20352. ``DW_OP_regx`` 2036 2037 ``DW_OP_regx`` has a single unsigned LEB128 integer operand that represents 2038 a target architecture register number R. 2039 2040 If the current call frame is the top call frame, it pushes a location 2041 description L that specifies one register location description SL on the 2042 stack. SL specifies the register location storage that corresponds to R with 2043 a bit offset of 0 for the current thread. 2044 2045 If the current call frame is not the top call frame, call frame information 2046 (see :ref:`amdgpu-dwarf-call-frame-information`) is used to determine the 2047 location description that holds the register for the current call frame and 2048 current program location of the current thread. The resulting location 2049 description L is pushed. 2050 2051 *Note that if call frame information is used, the resulting location 2052 description may be register, memory, or undefined.* 2053 2054 *An implementation may evaluate the call frame information immediately, or 2055 may defer evaluation until L is accessed by an operation. If evaluation is 2056 deferred, R and the current context can be recorded in L. When accessed, the 2057 recorded context is used to evaluate the call frame information, not the 2058 current context of the access operation.* 2059 2060*These operations obtain a register location. To fetch the contents of a 2061register, it is necessary to use* ``DW_OP_regval_type``\ *, use one of the* 2062``DW_OP_breg*`` *register-based addressing operations, or use* ``DW_OP_deref*`` 2063*on a register location description.* 2064 2065.. _amdgpu-dwarf-implicit-location-descriptions: 2066 2067Implicit Location Description Operations 2068^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2069 2070Implicit location storage represents a piece or all of an object which has no 2071actual location in the program but whose contents are nonetheless known, either 2072as a constant or can be computed from other locations and values in the program. 2073 2074An implicit location description specifies an implicit location storage. The bit 2075offset corresponds to a bit position within the implicit location storage. Bits 2076accessed using an implicit location description, access the corresponding 2077implicit storage value starting at the bit offset. 2078 20791. ``DW_OP_implicit_value`` 2080 2081 ``DW_OP_implicit_value`` has two operands. The first is an unsigned LEB128 2082 integer that represents a byte size S. The second is a block of bytes with a 2083 length equal to S treated as a literal value V. 2084 2085 An implicit location storage LS is created with the literal value V and a 2086 size of S. 2087 2088 It pushes location description L with one implicit location description SL 2089 on the stack. SL specifies LS with a bit offset of 0. 2090 20912. ``DW_OP_stack_value`` 2092 2093 ``DW_OP_stack_value`` pops one stack entry that must be a value V. 2094 2095 An implicit location storage LS is created with the literal value V using 2096 the size, encoding, and enianity specified by V's base type. 2097 2098 It pushes a location description L with one implicit location description SL 2099 on the stack. SL specifies LS with a bit offset of 0. 2100 2101 *The* ``DW_OP_stack_value`` *operation specifies that the object does not 2102 exist in memory, but its value is nonetheless known. In this form, the 2103 location description specifies the actual value of the object, rather than 2104 specifying the memory or register storage that holds the value.* 2105 2106 See :ref:`amdgpu-dwarf-implicit-location-descriptions` for special rules 2107 concerning implicit pointer values produced by dereferencing implicit 2108 location descriptions created by the ``DW_OP_implicit_pointer`` and 2109 ``DW_OP_LLVM_implicit_aspace_pointer`` operations. 2110 2111 .. note:: 2112 2113 Since location descriptions are allowed on the stack, the 2114 ``DW_OP_stack_value`` operation no longer terminates the DWARF operation 2115 expression execution as in DWARF Version 5. 2116 21173. ``DW_OP_implicit_pointer`` 2118 2119 *An optimizing compiler may eliminate a pointer, while still retaining the 2120 value that the pointer addressed.* ``DW_OP_implicit_pointer`` *allows a 2121 producer to describe this value.* 2122 2123 ``DW_OP_implicit_pointer`` *specifies an object is a pointer to the target 2124 architecture default address space that cannot be represented as a real 2125 pointer, even though the value it would point to can be described. In this 2126 form, the location description specifies a debugging information entry that 2127 represents the actual location description of the object to which the 2128 pointer would point. Thus, a consumer of the debug information would be able 2129 to access the dereferenced pointer, even when it cannot access the pointer 2130 itself.* 2131 2132 ``DW_OP_implicit_pointer`` has two operands. The first operand is a 4-byte 2133 unsigned value in the 32-bit DWARF format, or an 8-byte unsigned value in 2134 the 64-bit DWARF format, that represents the byte offset DR of a debugging 2135 information entry D relative to the beginning of the ``.debug_info`` section 2136 that contains the current compilation unit. The second operand is a signed 2137 LEB128 integer that represents a byte displacement B. 2138 2139 *Note that D may not be in the current compilation unit.* 2140 2141 *The first operand interpretation is exactly like that for* 2142 ``DW_FORM_ref_addr``\ *.* 2143 2144 The address space identifier AS is defined as the one corresponding to the 2145 target architecture specific default address space. 2146 2147 The address size S is defined as the address bit size of the target 2148 architecture specific address space corresponding to AS. 2149 2150 An implicit location storage LS is created with the debugging information 2151 entry D, address space AS, and size of S. 2152 2153 It pushes a location description L that comprises one implicit location 2154 description SL on the stack. SL specifies LS with a bit offset of 0. 2155 2156 It is an evaluation error if a ``DW_OP_deref*`` operation pops a location 2157 description L', and retrieves S bits, such that any retrieved bits come from 2158 an implicit location storage that is the same as LS, unless both the 2159 following conditions are met: 2160 2161 1. All retrieved bits come from an implicit location description that 2162 refers to an implicit location storage that is the same as LS. 2163 2164 *Note that all bits do not have to come from the same implicit location 2165 description, as L' may involve composite location descriptors.* 2166 2167 2. The bits come from consecutive ascending offsets within their respective 2168 implicit location storage. 2169 2170 *These rules are equivalent to retrieving the complete contents of LS.* 2171 2172 If both the above conditions are met, then the value V pushed by the 2173 ``DW_OP_deref*`` operation is an implicit pointer value IPV with a target 2174 architecture specific address space of AS, a debugging information entry of 2175 D, and a base type of T. If AS is the target architecture default address 2176 space, then T is the generic type. Otherwise, T is a target architecture 2177 specific integral type with a bit size equal to S. 2178 2179 If IPV is either implicitly converted to a location description (only done 2180 if AS is the target architecture default address space) or used by 2181 ``DW_OP_LLVM_form_aspace_address`` (only done if the address space popped by 2182 ``DW_OP_LLVM_form_aspace_address`` is AS), then the resulting location 2183 description RL is: 2184 2185 * If D has a ``DW_AT_location`` attribute, the DWARF expression E from the 2186 ``DW_AT_location`` attribute is evaluated with the current context, except 2187 that the result kind is a location description, the compilation unit is 2188 the one that contains D, the object is unspecified, and the initial stack 2189 is empty. RL is the expression result. 2190 2191 *Note that E is evaluated with the context of the expression accessing 2192 IPV, and not the context of the expression that contained the* 2193 ``DW_OP_implicit_pointer`` *or* ``DW_OP_LLVM_aspace_implicit_pointer`` 2194 *operation that created L.* 2195 2196 * If D has a ``DW_AT_const_value`` attribute, then an implicit location 2197 storage RLS is created from the ``DW_AT_const_value`` attribute's value 2198 with a size matching the size of the ``DW_AT_const_value`` attribute's 2199 value. RL comprises one implicit location description SRL. SRL specifies 2200 RLS with a bit offset of 0. 2201 2202 .. note:: 2203 2204 If using ``DW_AT_const_value`` for variables and formal parameters is 2205 deprecated and instead ``DW_AT_location`` is used with an implicit 2206 location description, then this rule would not be required. 2207 2208 * Otherwise, it is an evaluation error. 2209 2210 The bit offset of RL is updated as if the ``DW_OP_LLVM_offset_uconst B`` 2211 operation was applied. 2212 2213 If a ``DW_OP_stack_value`` operation pops a value that is the same as IPV, 2214 then it pushes a location description that is the same as L. 2215 2216 It is an evaluation error if LS or IPV is accessed in any other manner. 2217 2218 *The restrictions on how an implicit pointer location description created 2219 by* ``DW_OP_implicit_pointer`` *and* ``DW_OP_LLVM_aspace_implicit_pointer`` 2220 *can be used are to simplify the DWARF consumer. Similarly, for an implicit 2221 pointer value created by* ``DW_OP_deref*`` *and* ``DW_OP_stack_value``\ .* 2222 22234. ``DW_OP_LLVM_aspace_implicit_pointer`` *New* 2224 2225 ``DW_OP_LLVM_aspace_implicit_pointer`` has two operands that are the same as 2226 for ``DW_OP_implicit_pointer``. 2227 2228 It pops one stack entry that must be an integral type value that represents 2229 a target architecture specific address space identifier AS. 2230 2231 The location description L that is pushed on the stack is the same as for 2232 ``DW_OP_implicit_pointer``, except that the address space identifier used is 2233 AS. 2234 2235 The DWARF expression is ill-formed if AS is not one of the values defined by 2236 the target architecture specific ``DW_ASPACE_*`` values. 2237 2238 .. note:: 2239 2240 This definition of ``DW_OP_LLVM_aspace_implicit_pointer`` may change when 2241 full support for address classes is added as required for languages such 2242 as OpenCL/SyCL. 2243 2244*Typically a* ``DW_OP_implicit_pointer`` *or* 2245``DW_OP_LLVM_aspace_implicit_pointer`` *operation is used in a DWARF expression 2246E*\ :sub:`1` *of a* ``DW_TAG_variable`` *or* ``DW_TAG_formal_parameter`` 2247*debugging information entry D*\ :sub:`1`\ *'s* ``DW_AT_location`` *attribute. 2248The debugging information entry referenced by the* ``DW_OP_implicit_pointer`` 2249*or* ``DW_OP_LLVM_aspace_implicit_pointer`` *operations is typically itself a* 2250``DW_TAG_variable`` *or* ``DW_TAG_formal_parameter`` *debugging information 2251entry D*\ :sub:`2` *whose* ``DW_AT_location`` *attribute gives a second DWARF 2252expression E*\ :sub:`2`\ *.* 2253 2254*D*\ :sub:`1` *and E*\ :sub:`1` *are describing the location of a pointer type 2255object. D*\ :sub:`2` *and E*\ :sub:`2` *are describing the location of the 2256object pointed to by that pointer object.* 2257 2258*However, D*\ :sub:`2` *may be any debugging information entry that contains a* 2259``DW_AT_location`` *or* ``DW_AT_const_value`` *attribute (for example,* 2260``DW_TAG_dwarf_procedure``\ *). By using E*\ :sub:`2`\ *, a consumer can 2261reconstruct the value of the object when asked to dereference the pointer 2262described by E*\ :sub:`1` *which contains the* ``DW_OP_implicit_pointer`` or 2263``DW_OP_LLVM_aspace_implicit_pointer`` *operation.* 2264 2265.. _amdgpu-dwarf-composite-location-description-operations: 2266 2267Composite Location Description Operations 2268^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2269 2270A composite location storage represents an object or value which may be 2271contained in part of another location storage or contained in parts of more 2272than one location storage. 2273 2274Each part has a part location description L and a part bit size S. L can have 2275one or more single location descriptions SL. If there are more than one SL then 2276that indicates that part is located in more than one place. The bits of each 2277place of the part comprise S contiguous bits from the location storage LS 2278specified by SL starting at the bit offset specified by SL. All the bits must 2279be within the size of LS or the DWARF expression is ill-formed. 2280 2281A composite location storage can have zero or more parts. The parts are 2282contiguous such that the zero-based location storage bit index will range over 2283each part with no gaps between them. Therefore, the size of a composite location 2284storage is the sum of the size of its parts. The DWARF expression is ill-formed 2285if the size of the contiguous location storage is larger than the size of the 2286memory location storage corresponding to the largest target architecture 2287specific address space. 2288 2289A composite location description specifies a composite location storage. The bit 2290offset corresponds to a bit position within the composite location storage. 2291 2292There are operations that create a composite location storage. 2293 2294There are other operations that allow a composite location storage to be 2295incrementally created. Each part is created by a separate operation. There may 2296be one or more operations to create the final composite location storage. A 2297series of such operations describes the parts of the composite location storage 2298that are in the order that the associated part operations are executed. 2299 2300To support incremental creation, a composite location storage can be in an 2301incomplete state. When an incremental operation operates on an incomplete 2302composite location storage, it adds a new part, otherwise it creates a new 2303composite location storage. The ``DW_OP_LLVM_piece_end`` operation explicitly 2304makes an incomplete composite location storage complete. 2305 2306A composite location description that specifies a composite location storage 2307that is incomplete is termed an incomplete composite location description. A 2308composite location description that specifies a composite location storage that 2309is complete is termed a complete composite location description. 2310 2311If the top stack entry is a location description that has one incomplete 2312composite location description SL after the execution of an operation expression 2313has completed, SL is converted to a complete composite location description. 2314 2315*Note that this conversion does not happen after the completion of an operation 2316expression that is evaluated on the same stack by the* ``DW_OP_call*`` 2317*operations. Such executions are not a separate evaluation of an operation 2318expression, but rather the continued evaluation of the same operation expression 2319that contains the* ``DW_OP_call*`` *operation.* 2320 2321If a stack entry is required to be a location description L, but L has an 2322incomplete composite location description, then the DWARF expression is 2323ill-formed. The exception is for the operations involved in incrementally 2324creating a composite location description as described below. 2325 2326*Note that a DWARF operation expression may arbitrarily compose composite 2327location descriptions from any other location description, including those that 2328have multiple single location descriptions, and those that have composite 2329location descriptions.* 2330 2331*The incremental composite location description operations are defined to be 2332compatible with the definitions in DWARF Version 5.* 2333 23341. ``DW_OP_piece`` 2335 2336 ``DW_OP_piece`` has a single unsigned LEB128 integer that represents a byte 2337 size S. 2338 2339 The action is based on the context: 2340 2341 * If the stack is empty, then a location description L comprised of one 2342 incomplete composite location description SL is pushed on the stack. 2343 2344 An incomplete composite location storage LS is created with a single part 2345 P. P specifies a location description PL and has a bit size of S scaled by 2346 8 (the byte size). PL is comprised of one undefined location description 2347 PSL. 2348 2349 SL specifies LS with a bit offset of 0. 2350 2351 * Otherwise, if the top stack entry is a location description L comprised of 2352 one incomplete composite location description SL, then the incomplete 2353 composite location storage LS that SL specifies is updated to append a new 2354 part P. P specifies a location description PL and has a bit size of S 2355 scaled by 8 (the byte size). PL is comprised of one undefined location 2356 description PSL. L is left on the stack. 2357 2358 * Otherwise, if the top stack entry is a location description or can be 2359 converted to one, then it is popped and treated as a part location 2360 description PL. Then: 2361 2362 * If the top stack entry (after popping PL) is a location description L 2363 comprised of one incomplete composite location description SL, then the 2364 incomplete composite location storage LS that SL specifies is updated to 2365 append a new part P. P specifies the location description PL and has a 2366 bit size of S scaled by 8 (the byte size). L is left on the stack. 2367 2368 * Otherwise, a location description L comprised of one incomplete 2369 composite location description SL is pushed on the stack. 2370 2371 An incomplete composite location storage LS is created with a single 2372 part P. P specifies the location description PL and has a bit size of S 2373 scaled by 8 (the byte size). 2374 2375 SL specifies LS with a bit offset of 0. 2376 2377 * Otherwise, the DWARF expression is ill-formed 2378 2379 *Many compilers store a single variable in sets of registers or store a 2380 variable partially in memory and partially in registers.* ``DW_OP_piece`` 2381 *provides a way of describing where a part of a variable is located.* 2382 2383 *If a non-0 byte displacement is required, the* ``DW_OP_LLVM_offset`` 2384 *operation can be used to update the location description before using it as 2385 the part location description of a* ``DW_OP_piece`` *operation.* 2386 2387 *The evaluation rules for the* ``DW_OP_piece`` *operation allow it to be 2388 compatible with the DWARF Version 5 definition.* 2389 2390 .. note:: 2391 2392 Since these extensions allow location descriptions to be entries on the 2393 stack, a simpler operation to create composite location descriptions could 2394 be defined. For example, just one operation that specifies how many parts, 2395 and pops pairs of stack entries for the part size and location 2396 description. Not only would this be a simpler operation and avoid the 2397 complexities of incomplete composite location descriptions, but it may 2398 also have a smaller encoding in practice. However, the desire for 2399 compatibility with DWARF Version 5 is likely a stronger consideration. 2400 24012. ``DW_OP_bit_piece`` 2402 2403 ``DW_OP_bit_piece`` has two operands. The first is an unsigned LEB128 2404 integer that represents the part bit size S. The second is an unsigned 2405 LEB128 integer that represents a bit displacement B. 2406 2407 The action is the same as for ``DW_OP_piece``, except that any part created 2408 has the bit size S, and the location description PL of any created part is 2409 updated as if the ``DW_OP_constu B; DW_OP_LLVM_bit_offset`` operations were 2410 applied. 2411 2412 ``DW_OP_bit_piece`` *is used instead of* ``DW_OP_piece`` *when the piece to 2413 be assembled is not byte-sized or is not at the start of the part location 2414 description.* 2415 2416 *If a computed bit displacement is required, the* ``DW_OP_LLVM_bit_offset`` 2417 *operation can be used to update the location description before using it as 2418 the part location description of a* ``DW_OP_bit_piece`` *operation.* 2419 2420 .. note:: 2421 2422 The bit offset operand is not needed as ``DW_OP_LLVM_bit_offset`` can be 2423 used on the part's location description. 2424 24253. ``DW_OP_LLVM_piece_end`` *New* 2426 2427 If the top stack entry is not a location description L comprised of one 2428 incomplete composite location description SL, then the DWARF expression is 2429 ill-formed. 2430 2431 Otherwise, the incomplete composite location storage LS specified by SL is 2432 updated to be a complete composite location description with the same parts. 2433 24344. ``DW_OP_LLVM_extend`` *New* 2435 2436 ``DW_OP_LLVM_extend`` has two operands. The first is an unsigned LEB128 2437 integer that represents the element bit size S. The second is an unsigned 2438 LEB128 integer that represents a count C. 2439 2440 It pops one stack entry that must be a location description and is treated 2441 as the part location description PL. 2442 2443 A location description L comprised of one complete composite location 2444 description SL is pushed on the stack. 2445 2446 A complete composite location storage LS is created with C identical parts 2447 P. Each P specifies PL and has a bit size of S. 2448 2449 SL specifies LS with a bit offset of 0. 2450 2451 The DWARF expression is ill-formed if the element bit size or count are 0. 2452 24535. ``DW_OP_LLVM_select_bit_piece`` *New* 2454 2455 ``DW_OP_LLVM_select_bit_piece`` has two operands. The first is an unsigned 2456 LEB128 integer that represents the element bit size S. The second is an 2457 unsigned LEB128 integer that represents a count C. 2458 2459 It pops three stack entries. The first must be an integral type value that 2460 represents a bit mask value M. The second must be a location description 2461 that represents the one-location description L1. The third must be a 2462 location description that represents the zero-location description L0. 2463 2464 A complete composite location storage LS is created with C parts P\ :sub:`N` 2465 ordered in ascending N from 0 to C-1 inclusive. Each P\ :sub:`N` specifies 2466 location description PL\ :sub:`N` and has a bit size of S. 2467 2468 PL\ :sub:`N` is as if the ``DW_OP_LLVM_bit_offset N*S`` operation was 2469 applied to PLX\ :sub:`N`\ . 2470 2471 PLX\ :sub:`N` is the same as L0 if the N\ :sup:`th` least significant bit of 2472 M is a zero, otherwise it is the same as L1. 2473 2474 A location description L comprised of one complete composite location 2475 description SL is pushed on the stack. SL specifies LS with a bit offset of 2476 0. 2477 2478 The DWARF expression is ill-formed if S or C are 0, or if the bit size of M 2479 is less than C. 2480 2481.. _amdgpu-dwarf-location-list-expressions: 2482 2483DWARF Location List Expressions 2484+++++++++++++++++++++++++++++++ 2485 2486*To meet the needs of recent computer architectures and optimization techniques, 2487debugging information must be able to describe the location of an object whose 2488location changes over the object’s lifetime, and may reside at multiple 2489locations during parts of an object's lifetime. Location list expressions are 2490used in place of operation expressions whenever the object whose location is 2491being described has these requirements.* 2492 2493A location list expression consists of a series of location list entries. Each 2494location list entry is one of the following kinds: 2495 2496*Bounded location description* 2497 2498 This kind of location list entry provides an operation expression that 2499 evaluates to the location description of an object that is valid over a 2500 lifetime bounded by a starting and ending address. The starting address is the 2501 lowest address of the address range over which the location is valid. The 2502 ending address is the address of the first location past the highest address 2503 of the address range. 2504 2505 The location list entry matches when the current program location is within 2506 the given range. 2507 2508 There are several kinds of bounded location description entries which differ 2509 in the way that they specify the starting and ending addresses. 2510 2511*Default location description* 2512 2513 This kind of location list entry provides an operation expression that 2514 evaluates to the location description of an object that is valid when no 2515 bounded location description entry applies. 2516 2517 The location list entry matches when the current program location is not 2518 within the range of any bounded location description entry. 2519 2520*Base address* 2521 2522 This kind of location list entry provides an address to be used as the base 2523 address for beginning and ending address offsets given in certain kinds of 2524 bounded location description entries. The applicable base address of a bounded 2525 location description entry is the address specified by the closest preceding 2526 base address entry in the same location list. If there is no preceding base 2527 address entry, then the applicable base address defaults to the base address 2528 of the compilation unit (see DWARF Version 5 section 3.1.1). 2529 2530 In the case of a compilation unit where all of the machine code is contained 2531 in a single contiguous section, no base address entry is needed. 2532 2533*End-of-list* 2534 2535 This kind of location list entry marks the end of the location list 2536 expression. 2537 2538The address ranges defined by the bounded location description entries of a 2539location list expression may overlap. When they do, they describe a situation in 2540which an object exists simultaneously in more than one place. 2541 2542If all of the address ranges in a given location list expression do not 2543collectively cover the entire range over which the object in question is 2544defined, and there is no following default location description entry, it is 2545assumed that the object is not available for the portion of the range that is 2546not covered. 2547 2548The result of the evaluation of a DWARF location list expression is: 2549 2550* If the current program location is not specified, then it is an evaluation 2551 error. 2552 2553 .. note:: 2554 2555 If the location list only has a single default entry, should that be 2556 considered a match if there is no program location? If there are non-default 2557 entries then it seems it has to be an evaluation error when there is no 2558 program location as that indicates the location depends on the program 2559 location which is not known. 2560 2561* If there are no matching location list entries, then the result is a location 2562 description that comprises one undefined location description. 2563 2564* Otherwise, the operation expression E of each matching location list entry is 2565 evaluated with the current context, except that the result kind is a location 2566 description, the object is unspecified, and the initial stack is empty. The 2567 location list entry result is the location description returned by the 2568 evaluation of E. 2569 2570 The result is a location description that is comprised of the union of the 2571 single location descriptions of the location description result of each 2572 matching location list entry. 2573 2574A location list expression can only be used as the value of a debugger 2575information entry attribute that is encoded using class ``loclist`` or 2576``loclistsptr`` (see DWARF Version 5 section 7.5.5). The value of the attribute 2577provides an index into a separate object file section called ``.debug_loclists`` 2578or ``.debug_loclists.dwo`` (for split DWARF object files) that contains the 2579location list entries. 2580 2581A ``DW_OP_call*`` and ``DW_OP_implicit_pointer`` operation can be used to 2582specify a debugger information entry attribute that has a location list 2583expression. Several debugger information entry attributes allow DWARF 2584expressions that are evaluated with an initial stack that includes a location 2585description that may originate from the evaluation of a location list 2586expression. 2587 2588*This location list representation, the* ``loclist`` *and* ``loclistsptr`` 2589*class, and the related* ``DW_AT_loclists_base`` *attribute are new in DWARF 2590Version 5. Together they eliminate most, or all of the code object relocations 2591previously needed for location list expressions.* 2592 2593.. note:: 2594 2595 The rest of this section is the same as DWARF Version 5 section 2.6.2. 2596 2597.. _amdgpu-dwarf-segment_addresses: 2598 2599Segmented Addresses 2600~~~~~~~~~~~~~~~~~~~ 2601 2602.. note:: 2603 2604 This augments DWARF Version 5 section 2.12. 2605 2606DWARF address classes are used for source languages that have the concept of 2607memory spaces. They are used in the ``DW_AT_address_class`` attribute for 2608pointer type, reference type, subprogram, and subprogram type debugger 2609information entries. 2610 2611Each DWARF address class is conceptually a separate source language memory space 2612with its own lifetime and aliasing rules. DWARF address classes are used to 2613specify the source language memory spaces that pointer type and reference type 2614values refer, and to specify the source language memory space in which variables 2615are allocated. 2616 2617The set of currently defined source language DWARF address classes, together 2618with source language mappings, is given in 2619:ref:`amdgpu-dwarf-address-class-table`. 2620 2621Vendor defined source language address classes may be defined using codes in the 2622range ``DW_ADDR_LLVM_lo_user`` to ``DW_ADDR_LLVM_hi_user``. 2623 2624.. table:: Address class 2625 :name: amdgpu-dwarf-address-class-table 2626 2627 ========================= ============ ========= ========= ========= 2628 Address Class Name Meaning C/C++ OpenCL CUDA/HIP 2629 ========================= ============ ========= ========= ========= 2630 ``DW_ADDR_none`` generic *default* generic *default* 2631 ``DW_ADDR_LLVM_global`` global global 2632 ``DW_ADDR_LLVM_constant`` constant constant constant 2633 ``DW_ADDR_LLVM_group`` thread-group local shared 2634 ``DW_ADDR_LLVM_private`` thread private 2635 ``DW_ADDR_LLVM_lo_user`` 2636 ``DW_ADDR_LLVM_hi_user`` 2637 ========================= ============ ========= ========= ========= 2638 2639DWARF address spaces correspond to target architecture specific linear 2640addressable memory areas. They are used in DWARF expression location 2641descriptions to describe in which target architecture specific memory area data 2642resides. 2643 2644*Target architecture specific DWARF address spaces may correspond to hardware 2645supported facilities such as memory utilizing base address registers, scratchpad 2646memory, and memory with special interleaving. The size of addresses in these 2647address spaces may vary. Their access and allocation may be hardware managed 2648with each thread or group of threads having access to independent storage. For 2649these reasons they may have properties that do not allow them to be viewed as 2650part of the unified global virtual address space accessible by all threads.* 2651 2652*It is target architecture specific whether multiple DWARF address spaces are 2653supported and how source language DWARF address classes map to target 2654architecture specific DWARF address spaces. A target architecture may map 2655multiple source language DWARF address classes to the same target architecture 2656specific DWARF address class. Optimization may determine that variable lifetime 2657and access pattern allows them to be allocated in faster scratchpad memory 2658represented by a different DWARF address space.* 2659 2660Although DWARF address space identifiers are target architecture specific, 2661``DW_ASPACE_none`` is a common address space supported by all target 2662architectures. 2663 2664DWARF address space identifiers are used by: 2665 2666* The DWARF expression operations: ``DW_OP_LLVM_aspace_bregx``, 2667 ``DW_OP_LLVM_form_aspace_address``, ``DW_OP_LLVM_implicit_aspace_pointer``, 2668 and ``DW_OP_xderef*``. 2669 2670* The CFI instructions: ``DW_CFA_LLVM_def_aspace_cfa`` and 2671 ``DW_CFA_LLVM_def_aspace_cfa_sf``. 2672 2673.. note:: 2674 2675 With the definition of DWARF address classes and DWARF address spaces in these 2676 extensions, DWARF Version 5 table 2.7 needs to be updated. It seems it is an 2677 example of DWARF address spaces and not DWARF address classes. 2678 2679.. note:: 2680 2681 With the expanded support for DWARF address spaces in these extensions, it may 2682 be worth examining if DWARF segments can be eliminated and DWARF address 2683 spaces used instead. 2684 2685 That may involve extending DWARF address spaces to also be used to specify 2686 code locations. In target architectures that use different memory areas for 2687 code and data this would seem a natural use for DWARF address spaces. This 2688 would allow DWARF expression location descriptions to be used to describe the 2689 location of subprograms and entry points that are used in expressions 2690 involving subprogram pointer type values. 2691 2692 Currently, DWARF expressions assume data and code resides in the same default 2693 DWARF address space, and only the address ranges in DWARF location list 2694 entries and in the ``.debug_aranges`` section for accelerated access for 2695 addresses allow DWARF segments to be used to distinguish. 2696 2697.. note:: 2698 2699 Currently, DWARF defines address class values as being target architecture 2700 specific. It is unclear how language specific memory spaces are intended to be 2701 represented in DWARF using these. 2702 2703 For example, OpenCL defines memory spaces (called address spaces in OpenCL) 2704 for ``global``, ``local``, ``constant``, and ``private``. These are part of 2705 the type system and are modifiers to pointer types. In addition, OpenCL 2706 defines ``generic`` pointers that can reference either the ``global``, 2707 ``local``, or ``private`` memory spaces. To support the OpenCL language the 2708 debugger would want to support casting pointers between the ``generic`` and 2709 other memory spaces, querying what memory space a ``generic`` pointer value is 2710 currently referencing, and possibly using pointer casting to form an address 2711 for a specific memory space out of an integral value. 2712 2713 The method to use to dereference a pointer type or reference type value is 2714 defined in DWARF expressions using ``DW_OP_xderef*`` which uses a target 2715 architecture specific address space. 2716 2717 DWARF defines the ``DW_AT_address_class`` attribute on pointer type and 2718 reference type debugger information entries. It specifies the method to use to 2719 dereference them. Why is the value of this not the same as the address space 2720 value used in ``DW_OP_xderef*``? In both cases it is target architecture 2721 specific and the architecture presumably will use the same set of methods to 2722 dereference pointers in both cases. 2723 2724 Since ``DW_AT_address_class`` uses a target architecture specific value, it 2725 cannot in general capture the source language memory space type modifier 2726 concept. On some architectures all source language memory space modifiers may 2727 actually use the same method for dereferencing pointers. 2728 2729 One possibility is for DWARF to add an ``DW_TAG_LLVM_address_class_type`` 2730 debugger information entry type modifier that can be applied to a pointer type 2731 and reference type. The ``DW_AT_address_class`` attribute could be re-defined 2732 to not be target architecture specific and instead define generalized language 2733 values (as presented above for DWARF address classes in the table 2734 :ref:`amdgpu-dwarf-address-class-table`) that will support OpenCL and other 2735 languages using memory spaces. The ``DW_AT_address_class`` attribute could be 2736 defined to not be applied to pointer types or reference types, but instead 2737 only to the new ``DW_TAG_LLVM_address_class_type`` type modifier debugger 2738 information entry. 2739 2740 If a pointer type or reference type is not modified by 2741 ``DW_TAG_LLVM_address_class_type`` or if ``DW_TAG_LLVM_address_class_type`` 2742 has no ``DW_AT_address_class`` attribute, then the pointer type or reference 2743 type would be defined to use the ``DW_ADDR_none`` address class as currently. 2744 Since modifiers can be chained, it would need to be defined if multiple 2745 ``DW_TAG_LLVM_address_class_type`` modifiers were legal, and if so if the 2746 outermost one is the one that takes precedence. 2747 2748 A target architecture implementation that supports multiple address spaces 2749 would need to map ``DW_ADDR_none`` appropriately to support CUDA-like 2750 languages that have no address classes in the type system but do support 2751 variable allocation in address classes. Such variable allocation would result 2752 in the variable's location description needing an address space. 2753 2754 The approach presented in :ref:`amdgpu-dwarf-address-class-table` is to define 2755 the default ``DW_ADDR_none`` to be the generic address class and not the 2756 global address class. This matches how CLANG and LLVM have added support for 2757 CUDA-like languages on top of existing C++ language support. This allows all 2758 addresses to be generic by default which matches CUDA-like languages. 2759 2760 An alternative approach is to define ``DW_ADDR_none`` as being the global 2761 address class and then change ``DW_ADDR_LLVM_global`` to 2762 ``DW_ADDR_LLVM_generic``. This would match the reality that languages that do 2763 not support multiple memory spaces only have one default global memory space. 2764 Generally, in these languages if they expose that the target architecture 2765 supports multiple address spaces, the default one is still the global memory 2766 space. Then a language that does support multiple memory spaces has to 2767 explicitly indicate which pointers have the added ability to reference more 2768 than the global memory space. However, compilers generating DWARF for 2769 CUDA-like languages would then have to define every CUDA-like language pointer 2770 type or reference type using ``DW_TAG_LLVM_address_class_type`` with a 2771 ``DW_AT_address_class`` attribute of ``DW_ADDR_LLVM_generic`` to match the 2772 language semantics. 2773 2774 A new ``DW_AT_LLVM_address_space`` attribute could be defined that can be 2775 applied to pointer type, reference type, subprogram, and subprogram type to 2776 describe how objects having the given type are dereferenced or called (the 2777 role that ``DW_AT_address_class`` currently provides). The values of 2778 ``DW_AT_address_space`` would be target architecture specific and the same as 2779 used in ``DW_OP_xderef*``. 2780 2781.. note:: 2782 2783 Some additional changes will be made to support languages such as OpenCL/SyCL 2784 that allow address class pointer casting and queries. 2785 2786 This requires the compiler to provide the mapping from address space to 2787 address class which may be runtime and not target architecture dependent. Some 2788 implementations may have a one-to-one mapping from source language address 2789 class to target architecture address space, and some may have a many-to-one 2790 mapping which requires knowledge of the address class when determining if 2791 pointer address class casts are allowed. 2792 2793 The changes will likely add an attribute that has an expression provided by 2794 the compiler to map from address class to address space. The 2795 ``DW_OP_implicit_pointer`` and ``DW_OP_LLVM_aspace_implicit_pointer`` 2796 operations may be changed as the current IPV definition may not provide enough 2797 information when used to cast between address classes. Other attributes and 2798 operations may be needed. The legal casts between address classes may need to 2799 be defined on a per language address class basis. 2800 2801.. _amdgpu-dwarf-debugging-information-entry-attributes: 2802 2803Debugging Information Entry Attributes 2804~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2805 2806.. note:: 2807 2808 This section provides changes to existing debugger information entry 2809 attributes and defines attributes added by these extensions. These would be 2810 incorporated into the appropriate DWARF Version 5 chapter 2 sections. 2811 28121. ``DW_AT_location`` 2813 2814 Any debugging information entry describing a data object (which includes 2815 variables and parameters) or common blocks may have a ``DW_AT_location`` 2816 attribute, whose value is a DWARF expression E. 2817 2818 The result of the attribute is obtained by evaluating E with a context that 2819 has a result kind of a location description, an unspecified object, the 2820 compilation unit that contains E, an empty initial stack, and other context 2821 elements corresponding to the source language thread of execution upon which 2822 the user is focused, if any. The result of the evaluation is the location 2823 description of the base of the data object. 2824 2825 See :ref:`amdgpu-dwarf-control-flow-operations` for special evaluation rules 2826 used by the ``DW_OP_call*`` operations. 2827 2828 .. note:: 2829 2830 Delete the description of how the ``DW_OP_call*`` operations evaluate a 2831 ``DW_AT_location`` attribute as that is now described in the operations. 2832 2833 .. note:: 2834 2835 See the discussion about the ``DW_AT_location`` attribute in the 2836 ``DW_OP_call*`` operation. Having each attribute only have a single 2837 purpose and single execution semantics seems desirable. It makes it easier 2838 for the consumer that no longer have to track the context. It makes it 2839 easier for the producer as it can rely on a single semantics for each 2840 attribute. 2841 2842 For that reason, limiting the ``DW_AT_location`` attribute to only 2843 supporting evaluating the location description of an object, and using a 2844 different attribute and encoding class for the evaluation of DWARF 2845 expression *procedures* on the same operation expression stack seems 2846 desirable. 2847 28482. ``DW_AT_const_value`` 2849 2850 .. note:: 2851 2852 Could deprecate using the ``DW_AT_const_value`` attribute for 2853 ``DW_TAG_variable`` or ``DW_TAG_formal_parameter`` debugger information 2854 entries that have been optimized to a constant. Instead, 2855 ``DW_AT_location`` could be used with a DWARF expression that produces an 2856 implicit location description now that any location description can be 2857 used within a DWARF expression. This allows the ``DW_OP_call*`` operations 2858 to be used to push the location description of any variable regardless of 2859 how it is optimized. 2860 28613. ``DW_AT_frame_base`` 2862 2863 A ``DW_TAG_subprogram`` or ``DW_TAG_entry_point`` debugger information entry 2864 may have a ``DW_AT_frame_base`` attribute, whose value is a DWARF expression 2865 E. 2866 2867 The result of the attribute is obtained by evaluating E with a context that 2868 has a result kind of a location description, an unspecified object, the 2869 compilation unit that contains E, an empty initial stack, and other context 2870 elements corresponding to the source language thread of execution upon which 2871 the user is focused, if any. 2872 2873 The DWARF is ill-formed if E contains an ``DW_OP_fbreg`` operation, or the 2874 resulting location description L is not comprised of one single location 2875 description SL. 2876 2877 If SL a register location description for register R, then L is replaced 2878 with the result of evaluating a ``DW_OP_bregx R, 0`` operation. This 2879 computes the frame base memory location description in the target 2880 architecture default address space. 2881 2882 *This allows the more compact* ``DW_OPreg*`` *to be used instead of* 2883 ``DW_OP_breg* 0``\ *.* 2884 2885 .. note:: 2886 2887 This rule could be removed and require the producer to create the required 2888 location description directly using ``DW_OP_call_frame_cfa``, 2889 ``DW_OP_breg*``, or ``DW_OP_LLVM_aspace_bregx``. This would also then 2890 allow a target to implement the call frames within a large register. 2891 2892 Otherwise, the DWARF is ill-formed if SL is not a memory location 2893 description in any of the target architecture specific address spaces. 2894 2895 The resulting L is the *frame base* for the subprogram or entry point. 2896 2897 *Typically, E will use the* ``DW_OP_call_frame_cfa`` *operation or be a 2898 stack pointer register plus or minus some offset.* 2899 29004. ``DW_AT_data_member_location`` 2901 2902 For a ``DW_AT_data_member_location`` attribute there are two cases: 2903 2904 1. If the attribute is an integer constant B, it provides the offset in 2905 bytes from the beginning of the containing entity. 2906 2907 The result of the attribute is obtained by evaluating a 2908 ``DW_OP_LLVM_offset B`` operation with an initial stack comprising the 2909 location description of the beginning of the containing entity. The 2910 result of the evaluation is the location description of the base of the 2911 member entry. 2912 2913 *If the beginning of the containing entity is not byte aligned, then the 2914 beginning of the member entry has the same bit displacement within a 2915 byte.* 2916 2917 2. Otherwise, the attribute must be a DWARF expression E which is evaluated 2918 with a context that has a result kind of a location description, an 2919 unspecified object, the compilation unit that contains E, an initial 2920 stack comprising the location description of the beginning of the 2921 containing entity, and other context elements corresponding to the 2922 source language thread of execution upon which the user is focused, if 2923 any. The result of the evaluation is the location description of the 2924 base of the member entry. 2925 2926 .. note:: 2927 2928 The beginning of the containing entity can now be any location 2929 description, including those with more than one single location 2930 description, and those with single location descriptions that are of any 2931 kind and have any bit offset. 2932 29335. ``DW_AT_use_location`` 2934 2935 The ``DW_TAG_ptr_to_member_type`` debugging information entry has a 2936 ``DW_AT_use_location`` attribute whose value is a DWARF expression E. It is 2937 used to compute the location description of the member of the class to which 2938 the pointer to member entry points. 2939 2940 *The method used to find the location description of a given member of a 2941 class, structure, or union is common to any instance of that class, 2942 structure, or union and to any instance of the pointer to member type. The 2943 method is thus associated with the pointer to member type, rather than with 2944 each object that has a pointer to member type.* 2945 2946 The ``DW_AT_use_location`` DWARF expression is used in conjunction with the 2947 location description for a particular object of the given pointer to member 2948 type and for a particular structure or class instance. 2949 2950 The result of the attribute is obtained by evaluating E with a context that 2951 has a result kind of a location description, an unspecified object, the 2952 compilation unit that contains E, an initial stack comprising two entries, 2953 and other context elements corresponding to the source language thread of 2954 execution upon which the user is focused, if any. The first stack entry is 2955 the value of the pointer to member object itself. The second stack entry is 2956 the location description of the base of the entire class, structure, or 2957 union instance containing the member whose location is being calculated. The 2958 result of the evaluation is the location description of the member of the 2959 class to which the pointer to member entry points. 2960 29616. ``DW_AT_data_location`` 2962 2963 The ``DW_AT_data_location`` attribute may be used with any type that 2964 provides one or more levels of hidden indirection and/or run-time parameters 2965 in its representation. Its value is a DWARF operation expression E which 2966 computes the location description of the data for an object. When this 2967 attribute is omitted, the location description of the data is the same as 2968 the location description of the object. 2969 2970 The result of the attribute is obtained by evaluating E with a context that 2971 has a result kind of a location description, an object that is the location 2972 description of the data descriptor, the compilation unit that contains E, an 2973 empty initial stack, and other context elements corresponding to the source 2974 language thread of execution upon which the user is focused, if any. The 2975 result of the evaluation is the location description of the base of the 2976 member entry. 2977 2978 *E will typically involve an operation expression that begins with a* 2979 ``DW_OP_push_object_address`` *operation which loads the location 2980 description of the object which can then serve as a description in 2981 subsequent calculation.* 2982 2983 .. note:: 2984 2985 Since ``DW_AT_data_member_location``, ``DW_AT_use_location``, and 2986 ``DW_AT_vtable_elem_location`` allow both operation expressions and 2987 location list expressions, why does ``DW_AT_data_location`` not allow 2988 both? In all cases they apply to data objects so less likely that 2989 optimization would cause different operation expressions for different 2990 program location ranges. But if supporting for some then should be for 2991 all. 2992 2993 It seems odd this attribute is not the same as 2994 ``DW_AT_data_member_location`` in having an initial stack with the 2995 location description of the object since the expression has to need it. 2996 29977. ``DW_AT_vtable_elem_location`` 2998 2999 An entry for a virtual function also has a ``DW_AT_vtable_elem_location`` 3000 attribute whose value is a DWARF expression E. 3001 3002 The result of the attribute is obtained by evaluating E with a context that 3003 has a result kind of a location description, an unspecified object, the 3004 compilation unit that contains E, an initial stack comprising the location 3005 description of the object of the enclosing type, and other context elements 3006 corresponding to the source language thread of execution upon which the user 3007 is focused, if any. The result of the evaluation is the location description 3008 of the slot for the function within the virtual function table for the 3009 enclosing class. 3010 30118. ``DW_AT_static_link`` 3012 3013 If a ``DW_TAG_subprogram`` or ``DW_TAG_entry_point`` debugger information 3014 entry is lexically nested, it may have a ``DW_AT_static_link`` attribute, 3015 whose value is a DWARF expression E. 3016 3017 The result of the attribute is obtained by evaluating E with a context that 3018 has a result kind of a location description, an unspecified object, the 3019 compilation unit that contains E, an empty initial stack, and other context 3020 elements corresponding to the source language thread of execution upon which 3021 the user is focused, if any. The result of the evaluation is the location 3022 description L of the *canonical frame address* (see 3023 :ref:`amdgpu-dwarf-call-frame-information`) of the relevant call frame of 3024 the subprogram instance that immediately lexically encloses the current call 3025 frame's subprogram or entry point. 3026 3027 The DWARF is ill-formed if L is is not comprised of one memory location 3028 description for one of the target architecture specific address spaces. 3029 30309. ``DW_AT_return_addr`` 3031 3032 A ``DW_TAG_subprogram``, ``DW_TAG_inlined_subroutine``, or 3033 ``DW_TAG_entry_point`` debugger information entry may have a 3034 ``DW_AT_return_addr`` attribute, whose value is a DWARF expression E. 3035 3036 The result of the attribute is obtained by evaluating E with a context that 3037 has a result kind of a location description, an unspecified object, the 3038 compilation unit that contains E, an empty initial stack, and other context 3039 elements corresponding to the source language thread of execution upon which 3040 the user is focused, if any. The result of the evaluation is the location 3041 description L of the place where the return address for the current call 3042 frame's subprogram or entry point is stored. 3043 3044 The DWARF is ill-formed if L is not comprised of one memory location 3045 description for one of the target architecture specific address spaces. 3046 3047 .. note:: 3048 3049 It is unclear why ``DW_TAG_inlined_subroutine`` has a 3050 ``DW_AT_return_addr`` attribute but not a ``DW_AT_frame_base`` or 3051 ``DW_AT_static_link`` attribute. Seems it would either have all of them or 3052 none. Since inlined subprograms do not have a call frame it seems they 3053 would have none of these attributes. 3054 305510. ``DW_AT_call_value``, ``DW_AT_call_data_location``, and 3056 ``DW_AT_call_data_value`` 3057 3058 A ``DW_TAG_call_site_parameter`` debugger information entry may have a 3059 ``DW_AT_call_value`` attribute, whose value is a DWARF operation expression 3060 E\ :sub:`1`\ . 3061 3062 The result of the ``DW_AT_call_value`` attribute is obtained by evaluating 3063 E\ :sub:`1` with a context that has a result kind of a value, an unspecified 3064 object, the compilation unit that contains E, an empty initial stack, and 3065 other context elements corresponding to the source language thread of 3066 execution upon which the user is focused, if any. The resulting value V\ 3067 :sub:`1` is the value of the parameter at the time of the call made by the 3068 call site. 3069 3070 For parameters passed by reference, where the code passes a pointer to a 3071 location which contains the parameter, or for reference type parameters, the 3072 ``DW_TAG_call_site_parameter`` debugger information entry may also have a 3073 ``DW_AT_call_data_location`` attribute whose value is a DWARF operation 3074 expression E\ :sub:`2`\ , and a ``DW_AT_call_data_value`` attribute whose 3075 value is a DWARF operation expression E\ :sub:`3`\ . 3076 3077 The value of the ``DW_AT_call_data_location`` attribute is obtained by 3078 evaluating E\ :sub:`2` with a context that has a result kind of a location 3079 description, an unspecified object, the compilation unit that contains E, an 3080 empty initial stack, and other context elements corresponding to the source 3081 language thread of execution upon which the user is focused, if any. The 3082 resulting location description L\ :sub:`2` is the location where the 3083 referenced parameter lives during the call made by the call site. If E\ 3084 :sub:`2` would just be a ``DW_OP_push_object_address``, then the 3085 ``DW_AT_call_data_location`` attribute may be omitted. 3086 3087 The value of the ``DW_AT_call_data_value`` attribute is obtained by 3088 evaluating E\ :sub:`3` with a context that has a result kind of a value, an 3089 unspecified object, the compilation unit that contains E, an empty initial 3090 stack, and other context elements corresponding to the source language 3091 thread of execution upon which the user is focused, if any. The resulting 3092 value V\ :sub:`3` is the value in L\ :sub:`2` at the time of the call made 3093 by the call site. 3094 3095 The result of these attributes is undefined if the current call frame is 3096 not for the subprogram containing the ``DW_TAG_call_site_parameter`` 3097 debugger information entry or the current program location is not for the 3098 call site containing the ``DW_TAG_call_site_parameter`` debugger information 3099 entry in the current call frame. 3100 3101 *The consumer may have to virtually unwind to the call site (see* 3102 :ref:`amdgpu-dwarf-call-frame-information`\ *) in order to evaluate these 3103 attributes. This will ensure the source language thread of execution upon 3104 which the user is focused corresponds to the call site needed to evaluate 3105 the expression.* 3106 3107 If it is not possible to avoid the expressions of these attributes from 3108 accessing registers or memory locations that might be clobbered by the 3109 subprogram being called by the call site, then the associated attribute 3110 should not be provided. 3111 3112 *The reason for the restriction is that the parameter may need to be 3113 accessed during the execution of the callee. The consumer may virtually 3114 unwind from the called subprogram back to the caller and then evaluate the 3115 attribute expressions. The call frame information (see* 3116 :ref:`amdgpu-dwarf-call-frame-information`\ *) will not be able to restore 3117 registers that have been clobbered, and clobbered memory will no longer have 3118 the value at the time of the call.* 3119 312011. ``DW_AT_LLVM_lanes`` *New* 3121 3122 For languages that are implemented using a SIMD or SIMT execution model, a 3123 ``DW_TAG_subprogram``, ``DW_TAG_inlined_subroutine``, or 3124 ``DW_TAG_entry_point`` debugger information entry may have a 3125 ``DW_AT_LLVM_lanes`` attribute whose value is an integer constant that is 3126 the number of lanes per thread. This is the static number of lanes per 3127 thread. It is not the dynamic number of lanes with which the thread was 3128 initiated, for example, due to smaller or partial work-groups. 3129 3130 If not present, the default value of 1 is used. 3131 3132 The DWARF is ill-formed if the value is 0. 3133 313412. ``DW_AT_LLVM_lane_pc`` *New* 3135 3136 For languages that are implemented using a SIMD or SIMT execution model, a 3137 ``DW_TAG_subprogram``, ``DW_TAG_inlined_subroutine``, or 3138 ``DW_TAG_entry_point`` debugging information entry may have a 3139 ``DW_AT_LLVM_lane_pc`` attribute whose value is a DWARF expression E. 3140 3141 The result of the attribute is obtained by evaluating E with a context that 3142 has a result kind of a location description, an unspecified object, the 3143 compilation unit that contains E, an empty initial stack, and other context 3144 elements corresponding to the source language thread of execution upon which 3145 the user is focused, if any. 3146 3147 The resulting location description L is for a thread lane count sized vector 3148 of generic type elements. The thread lane count is the value of the 3149 ``DW_AT_LLVM_lanes`` attribute. Each element holds the conceptual program 3150 location of the corresponding lane, where the least significant element 3151 corresponds to the first target architecture specific lane identifier and so 3152 forth. If the lane was not active when the current subprogram was called, 3153 its element is an undefined location description. 3154 3155 ``DW_AT_LLVM_lane_pc`` *allows the compiler to indicate conceptually where 3156 each lane of a SIMT thread is positioned even when it is in divergent 3157 control flow that is not active.* 3158 3159 *Typically, the result is a location description with one composite location 3160 description with each part being a location description with either one 3161 undefined location description or one memory location description.* 3162 3163 If not present, the thread is not being used in a SIMT manner, and the 3164 thread's current program location is used. 3165 316613. ``DW_AT_LLVM_active_lane`` *New* 3167 3168 For languages that are implemented using a SIMD or SIMT execution model, a 3169 ``DW_TAG_subprogram``, ``DW_TAG_inlined_subroutine``, or 3170 ``DW_TAG_entry_point`` debugger information entry may have a 3171 ``DW_AT_LLVM_active_lane`` attribute whose value is a DWARF expression E. 3172 3173 The result of the attribute is obtained by evaluating E with a context that 3174 has a result kind of a value, an unspecified object, the compilation unit 3175 that contains E, an empty initial stack, and other context elements 3176 corresponding to the source language thread of execution upon which the user 3177 is focused, if any. 3178 3179 The DWARF is ill-formed if the resulting value V is not an integral value. 3180 3181 The resulting V is a bit mask of active lanes for the current program 3182 location. The N\ :sup:`th` least significant bit of the mask corresponds to 3183 the N\ :sup:`th` lane. If the bit is 1 the lane is active, otherwise it is 3184 inactive. 3185 3186 *Some targets may update the target architecture execution mask for regions 3187 of code that must execute with different sets of lanes than the current 3188 active lanes. For example, some code must execute with all lanes made 3189 temporarily active.* ``DW_AT_LLVM_active_lane`` *allows the compiler to 3190 provide the means to determine the source language active lanes.* 3191 3192 If not present and ``DW_AT_LLVM_lanes`` is greater than 1, then the target 3193 architecture execution mask is used. 3194 319514. ``DW_AT_LLVM_vector_size`` *New* 3196 3197 A ``DW_TAG_base_type`` debugger information entry for a base type T may have 3198 a ``DW_AT_LLVM_vector_size`` attribute whose value is an integer constant 3199 that is the vector type size N. 3200 3201 The representation of a vector base type is as N contiguous elements, each 3202 one having the representation of a base type T' that is the same as T 3203 without the ``DW_AT_LLVM_vector_size`` attribute. 3204 3205 If a ``DW_TAG_base_type`` debugger information entry does not have a 3206 ``DW_AT_LLVM_vector_size`` attribute, then the base type is not a vector 3207 type. 3208 3209 The DWARF is ill-formed if N is not greater than 0. 3210 3211 .. note:: 3212 3213 LLVM has mention of a non-upstreamed debugger information entry that is 3214 intended to support vector types. However, that was not for a base type so 3215 would not be suitable as the type of a stack value entry. But perhaps that 3216 could be replaced by using this attribute. 3217 321815. ``DW_AT_LLVM_augmentation`` *New* 3219 3220 A ``DW_TAG_compile_unit`` debugger information entry for a compilation unit 3221 may have a ``DW_AT_LLVM_augmentation`` attribute, whose value is an 3222 augmentation string. 3223 3224 *The augmentation string allows producers to indicate that there is 3225 additional vendor or target specific information in the debugging 3226 information entries. For example, this might be information about the 3227 version of vendor specific extensions that are being used.* 3228 3229 If not present, or if the string is empty, then the compilation unit has no 3230 augmentation string. 3231 3232 The format for the augmentation string is: 3233 3234 | ``[``\ *vendor*\ ``:v``\ *X*\ ``.``\ *Y*\ [\ ``:``\ *options*\ ]\ ``]``\ * 3235 3236 Where *vendor* is the producer, ``vX.Y`` specifies the major X and minor Y 3237 version number of the extensions used, and *options* is an optional string 3238 providing additional information about the extensions. The version number 3239 must conform to semantic versioning [:ref:`SEMVER <amdgpu-dwarf-SEMVER>`]. 3240 The *options* string must not contain the "\ ``]``\ " character. 3241 3242 For example: 3243 3244 :: 3245 3246 [abc:v0.0][def:v1.2:feature-a=on,feature-b=3] 3247 3248Program Scope Entities 3249---------------------- 3250 3251.. _amdgpu-dwarf-language-names: 3252 3253Unit Entities 3254~~~~~~~~~~~~~ 3255 3256.. note:: 3257 3258 This augments DWARF Version 5 section 3.1.1 and Table 3.1. 3259 3260Additional language codes defined for use with the ``DW_AT_language`` attribute 3261are defined in :ref:`amdgpu-dwarf-language-names-table`. 3262 3263.. table:: Language Names 3264 :name: amdgpu-dwarf-language-names-table 3265 3266 ==================== ============================= 3267 Language Name Meaning 3268 ==================== ============================= 3269 ``DW_LANG_LLVM_HIP`` HIP Language. 3270 ==================== ============================= 3271 3272The HIP language [:ref:`HIP <amdgpu-dwarf-HIP>`] can be supported by extending 3273the C++ language. 3274 3275Other Debugger Information 3276-------------------------- 3277 3278Accelerated Access 3279~~~~~~~~~~~~~~~~~~ 3280 3281.. _amdgpu-dwarf-lookup-by-name: 3282 3283Lookup By Name 3284++++++++++++++ 3285 3286Contents of the Name Index 3287########################## 3288 3289.. note:: 3290 3291 The following provides changes to DWARF Version 5 section 6.1.1.1. 3292 3293 The rule for debugger information entries included in the name index in the 3294 optional ``.debug_names`` section is extended to also include named 3295 ``DW_TAG_variable`` debugging information entries with a ``DW_AT_location`` 3296 attribute that includes a ``DW_OP_LLVM_form_aspace_address`` operation. 3297 3298The name index must contain an entry for each debugging information entry that 3299defines a named subprogram, label, variable, type, or namespace, subject to the 3300following rules: 3301 3302* ``DW_TAG_variable`` debugging information entries with a ``DW_AT_location`` 3303 attribute that includes a ``DW_OP_addr``, ``DW_OP_LLVM_form_aspace_address``, 3304 or ``DW_OP_form_tls_address`` operation are included; otherwise, they are 3305 excluded. 3306 3307Data Representation of the Name Index 3308##################################### 3309 3310Section Header 3311^^^^^^^^^^^^^^ 3312 3313.. note:: 3314 3315 The following provides an addition to DWARF Version 5 section 6.1.1.4.1 item 3316 14 ``augmentation_string``. 3317 3318A null-terminated UTF-8 vendor specific augmentation string, which provides 3319additional information about the contents of this index. If provided, the 3320recommended format for augmentation string is: 3321 3322 | ``[``\ *vendor*\ ``:v``\ *X*\ ``.``\ *Y*\ [\ ``:``\ *options*\ ]\ ``]``\ * 3323 3324Where *vendor* is the producer, ``vX.Y`` specifies the major X and minor Y 3325version number of the extensions used in the DWARF of the compilation unit, and 3326*options* is an optional string providing additional information about the 3327extensions. The version number must conform to semantic versioning [:ref:`SEMVER 3328<amdgpu-dwarf-SEMVER>`]. The *options* string must not contain the "\ ``]``\ " 3329character. 3330 3331For example: 3332 3333 :: 3334 3335 [abc:v0.0][def:v1.2:feature-a=on,feature-b=3] 3336 3337.. note:: 3338 3339 This is different to the definition in DWARF Version 5 but is consistent with 3340 the other augmentation strings and allows multiple vendor extensions to be 3341 supported. 3342 3343.. _amdgpu-dwarf-line-number-information: 3344 3345Line Number Information 3346~~~~~~~~~~~~~~~~~~~~~~~ 3347 3348The Line Number Program Header 3349++++++++++++++++++++++++++++++ 3350 3351Standard Content Descriptions 3352############################# 3353 3354.. note:: 3355 3356 This augments DWARF Version 5 section 6.2.4.1. 3357 3358.. _amdgpu-dwarf-line-number-information-dw-lnct-llvm-source: 3359 33601. ``DW_LNCT_LLVM_source`` 3361 3362 The component is a null-terminated UTF-8 source text string with "\ ``\n``\ 3363 " line endings. This content code is paired with the same forms as 3364 ``DW_LNCT_path``. It can be used for file name entries. 3365 3366 The value is an empty null-terminated string if no source is available. If 3367 the source is available but is an empty file then the value is a 3368 null-terminated single "\ ``\n``\ ". 3369 3370 *When the source field is present, consumers can use the embedded source 3371 instead of attempting to discover the source on disk using the file path 3372 provided by the* ``DW_LNCT_path`` *field. When the source field is absent, 3373 consumers can access the file to get the source text.* 3374 3375 *This is particularly useful for programming languages that support runtime 3376 compilation and runtime generation of source text. In these cases, the 3377 source text does not reside in any permanent file. For example, the OpenCL 3378 language [:ref:`OpenCL <amdgpu-dwarf-OpenCL>`] supports online compilation.* 3379 33802. ``DW_LNCT_LLVM_is_MD5`` 3381 3382 ``DW_LNCT_LLVM_is_MD5`` indicates if the ``DW_LNCT_MD5`` content kind, if 3383 present, is valid: when 0 it is not valid and when 1 it is valid. If 3384 ``DW_LNCT_LLVM_is_MD5`` content kind is not present, and ``DW_LNCT_MD5`` 3385 content kind is present, then the MD5 checksum is valid. 3386 3387 ``DW_LNCT_LLVM_is_MD5`` is always paired with the ``DW_FORM_udata`` form. 3388 3389 *This allows a compilation unit to have a mixture of files with and without 3390 MD5 checksums. This can happen when multiple relocatable files are linked 3391 together.* 3392 3393.. _amdgpu-dwarf-call-frame-information: 3394 3395Call Frame Information 3396~~~~~~~~~~~~~~~~~~~~~~ 3397 3398.. note:: 3399 3400 This section provides changes to existing call frame information and defines 3401 instructions added by these extensions. Additional support is added for 3402 address spaces. Register unwind DWARF expressions are generalized to allow any 3403 location description, including those with composite and implicit location 3404 descriptions. 3405 3406 These changes would be incorporated into the DWARF Version 5 section 6.1. 3407 3408.. _amdgpu-dwarf-structure_of-call-frame-information: 3409 3410Structure of Call Frame Information 3411+++++++++++++++++++++++++++++++++++ 3412 3413The register rules are: 3414 3415*undefined* 3416 A register that has this rule has no recoverable value in the previous frame. 3417 The previous value of this register is the undefined location description (see 3418 :ref:`amdgpu-dwarf-undefined-location-description-operations`). 3419 3420 *By convention, the register is not preserved by a callee.* 3421 3422*same value* 3423 This register has not been modified from the previous caller frame. 3424 3425 If the current frame is the top frame, then the previous value of this 3426 register is the location description L that specifies one register location 3427 description SL. SL specifies the register location storage that corresponds to 3428 the register with a bit offset of 0 for the current thread. 3429 3430 If the current frame is not the top frame, then the previous value of this 3431 register is the location description obtained using the call frame information 3432 for the callee frame and callee program location invoked by the current caller 3433 frame for the same register. 3434 3435 *By convention, the register is preserved by the callee, but the callee has 3436 not modified it.* 3437 3438*offset(N)* 3439 N is a signed byte offset. The previous value of this register is saved at the 3440 location description computed as if the DWARF operation expression 3441 ``DW_OP_LLVM_offset N`` is evaluated with the current context, except the 3442 result kind is a location description, the compilation unit is unspecified, 3443 the object is unspecified, and an initial stack comprising the location 3444 description of the current CFA (see 3445 :ref:`amdgpu-dwarf-operation-expressions`). 3446 3447*val_offset(N)* 3448 N is a signed byte offset. The previous value of this register is the memory 3449 byte address of the location description computed as if the DWARF operation 3450 expression ``DW_OP_LLVM_offset N`` is evaluated with the current context, 3451 except the result kind is a location description, the compilation unit is 3452 unspecified, the object is unspecified, and an initial stack comprising the 3453 location description of the current CFA (see 3454 :ref:`amdgpu-dwarf-operation-expressions`). 3455 3456 The DWARF is ill-formed if the CFA location description is not a memory byte 3457 address location description, or if the register size does not match the size 3458 of an address in the address space of the current CFA location description. 3459 3460 *Since the CFA location description is required to be a memory byte address 3461 location description, the value of val_offset(N) will also be a memory byte 3462 address location description since it is offsetting the CFA location 3463 description by N bytes. Furthermore, the value of val_offset(N) will be a 3464 memory byte address in the same address space as the CFA location 3465 description.* 3466 3467 .. note:: 3468 3469 Should DWARF allow the address size to be a different size to the size of 3470 the register? Requiring them to be the same bit size avoids any issue of 3471 conversion as the bit contents of the register is simply interpreted as a 3472 value of the address. 3473 3474 GDB has a per register hook that allows a target specific conversion on a 3475 register by register basis. It defaults to truncation of bigger registers, 3476 and to actually reading bytes from the next register (or reads out of bounds 3477 for the last register) for smaller registers. There are no GDB tests that 3478 read a register out of bounds (except an illegal hand written assembly 3479 test). 3480 3481*register(R)* 3482 This register has been stored in another register numbered R. 3483 3484 The previous value of this register is the location description obtained using 3485 the call frame information for the current frame and current program location 3486 for register R. 3487 3488 The DWARF is ill-formed if the size of this register does not match the size 3489 of register R or if there is a cyclic dependency in the call frame 3490 information. 3491 3492 .. note:: 3493 3494 Should this also allow R to be larger than this register? If so is the value 3495 stored in the low order bits and it is undefined what is stored in the 3496 extra upper bits? 3497 3498*expression(E)* 3499 The previous value of this register is located at the location description 3500 produced by evaluating the DWARF operation expression E (see 3501 :ref:`amdgpu-dwarf-operation-expressions`). 3502 3503 E is evaluated with the current context, except the result kind is a location 3504 description, the compilation unit is unspecified, the object is unspecified, 3505 and an initial stack comprising the location description of the current CFA 3506 (see :ref:`amdgpu-dwarf-operation-expressions`). 3507 3508*val_expression(E)* 3509 The previous value of this register is the value produced by evaluating the 3510 DWARF operation expression E (see :ref:`amdgpu-dwarf-operation-expressions`). 3511 3512 E is evaluated with the current context, except the result kind is a value, 3513 the compilation unit is unspecified, the object is unspecified, and an initial 3514 stack comprising the location description of the current CFA (see 3515 :ref:`amdgpu-dwarf-operation-expressions`). 3516 3517 The DWARF is ill-formed if the resulting value type size does not match the 3518 register size. 3519 3520 .. note:: 3521 3522 This has limited usefulness as the DWARF expression E can only produce 3523 values up to the size of the generic type. This is due to not allowing any 3524 operations that specify a type in a CFI operation expression. This makes it 3525 unusable for registers that are larger than the generic type. However, 3526 *expression(E)* can be used to create an implicit location description of 3527 any size. 3528 3529*architectural* 3530 The rule is defined externally to this specification by the augmenter. 3531 3532A Common Information Entry (CIE) holds information that is shared among many 3533Frame Description Entries (FDE). There is at least one CIE in every non-empty 3534``.debug_frame`` section. A CIE contains the following fields, in order: 3535 35361. ``length`` (initial length) 3537 3538 A constant that gives the number of bytes of the CIE structure, not 3539 including the length field itself. The size of the length field plus the 3540 value of length must be an integral multiple of the address size specified 3541 in the ``address_size`` field. 3542 35432. ``CIE_id`` (4 or 8 bytes, see 3544 :ref:`amdgpu-dwarf-32-bit-and-64-bit-dwarf-formats`) 3545 3546 A constant that is used to distinguish CIEs from FDEs. 3547 3548 In the 32-bit DWARF format, the value of the CIE id in the CIE header is 3549 0xffffffff; in the 64-bit DWARF format, the value is 0xffffffffffffffff. 3550 35513. ``version`` (ubyte) 3552 3553 A version number. This number is specific to the call frame information and 3554 is independent of the DWARF version number. 3555 3556 The value of the CIE version number is 4. 3557 3558 .. note:: 3559 3560 Would this be increased to 5 to reflect the changes in these extensions? 3561 35624. ``augmentation`` (sequence of UTF-8 characters) 3563 3564 A null-terminated UTF-8 string that identifies the augmentation to this CIE 3565 or to the FDEs that use it. If a reader encounters an augmentation string 3566 that is unexpected, then only the following fields can be read: 3567 3568 * CIE: length, CIE_id, version, augmentation 3569 * FDE: length, CIE_pointer, initial_location, address_range 3570 3571 If there is no augmentation, this value is a zero byte. 3572 3573 *The augmentation string allows users to indicate that there is additional 3574 vendor and target architecture specific information in the CIE or FDE which 3575 is needed to virtually unwind a stack frame. For example, this might be 3576 information about dynamically allocated data which needs to be freed on exit 3577 from the routine.* 3578 3579 *Because the* ``.debug_frame`` *section is useful independently of any* 3580 ``.debug_info`` *section, the augmentation string always uses UTF-8 3581 encoding.* 3582 3583 The recommended format for the augmentation string is: 3584 3585 | ``[``\ *vendor*\ ``:v``\ *X*\ ``.``\ *Y*\ [\ ``:``\ *options*\ ]\ ``]``\ * 3586 3587 Where *vendor* is the producer, ``vX.Y`` specifies the major X and minor Y 3588 version number of the extensions used, and *options* is an optional string 3589 providing additional information about the extensions. The version number 3590 must conform to semantic versioning [:ref:`SEMVER <amdgpu-dwarf-SEMVER>`]. 3591 The *options* string must not contain the "\ ``]``\ " character. 3592 3593 For example: 3594 3595 :: 3596 3597 [abc:v0.0][def:v1.2:feature-a=on,feature-b=3] 3598 35995. ``address_size`` (ubyte) 3600 3601 The size of a target address in this CIE and any FDEs that use it, in bytes. 3602 If a compilation unit exists for this frame, its address size must match the 3603 address size here. 3604 36056. ``segment_selector_size`` (ubyte) 3606 3607 The size of a segment selector in this CIE and any FDEs that use it, in 3608 bytes. 3609 36107. ``code_alignment_factor`` (unsigned LEB128) 3611 3612 A constant that is factored out of all advance location instructions (see 3613 :ref:`amdgpu-dwarf-row-creation-instructions`). The resulting value is 3614 ``(operand * code_alignment_factor)``. 3615 36168. ``data_alignment_factor`` (signed LEB128) 3617 3618 A constant that is factored out of certain offset instructions (see 3619 :ref:`amdgpu-dwarf-cfa-definition-instructions` and 3620 :ref:`amdgpu-dwarf-register-rule-instructions`). The resulting value is 3621 ``(operand * data_alignment_factor)``. 3622 36239. ``return_address_register`` (unsigned LEB128) 3624 3625 An unsigned LEB128 constant that indicates which column in the rule table 3626 represents the return address of the subprogram. Note that this column might 3627 not correspond to an actual machine register. 3628 3629 The value of the return address register is used to determine the program 3630 location of the caller frame. The program location of the top frame is the 3631 target architecture program counter value of the current thread. 3632 363310. ``initial_instructions`` (array of ubyte) 3634 3635 A sequence of rules that are interpreted to create the initial setting of 3636 each column in the table. 3637 3638 The default rule for all columns before interpretation of the initial 3639 instructions is the undefined rule. However, an ABI authoring body or a 3640 compilation system authoring body may specify an alternate default value for 3641 any or all columns. 3642 364311. ``padding`` (array of ubyte) 3644 3645 Enough ``DW_CFA_nop`` instructions to make the size of this entry match the 3646 length value above. 3647 3648An FDE contains the following fields, in order: 3649 36501. ``length`` (initial length) 3651 3652 A constant that gives the number of bytes of the header and instruction 3653 stream for this subprogram, not including the length field itself. The size 3654 of the length field plus the value of length must be an integral multiple of 3655 the address size. 3656 36572. ``CIE_pointer`` (4 or 8 bytes, see 3658 :ref:`amdgpu-dwarf-32-bit-and-64-bit-dwarf-formats`) 3659 3660 A constant offset into the ``.debug_frame`` section that denotes the CIE 3661 that is associated with this FDE. 3662 36633. ``initial_location`` (segment selector and target address) 3664 3665 The address of the first location associated with this table entry. If the 3666 segment_selector_size field of this FDE’s CIE is non-zero, the initial 3667 location is preceded by a segment selector of the given length. 3668 36694. ``address_range`` (target address) 3670 3671 The number of bytes of program instructions described by this entry. 3672 36735. ``instructions`` (array of ubyte) 3674 3675 A sequence of table defining instructions that are described in 3676 :ref:`amdgpu-dwarf-call-frame-instructions`. 3677 36786. ``padding`` (array of ubyte) 3679 3680 Enough ``DW_CFA_nop`` instructions to make the size of this entry match the 3681 length value above. 3682 3683.. _amdgpu-dwarf-call-frame-instructions: 3684 3685Call Frame Instructions 3686+++++++++++++++++++++++ 3687 3688Some call frame instructions have operands that are encoded as DWARF operation 3689expressions E (see :ref:`amdgpu-dwarf-operation-expressions`). The DWARF 3690operations that can be used in E have the following restrictions: 3691 3692* ``DW_OP_addrx``, ``DW_OP_call2``, ``DW_OP_call4``, ``DW_OP_call_ref``, 3693 ``DW_OP_const_type``, ``DW_OP_constx``, ``DW_OP_convert``, 3694 ``DW_OP_deref_type``, ``DW_OP_fbreg``, ``DW_OP_implicit_pointer``, 3695 ``DW_OP_regval_type``, ``DW_OP_reinterpret``, and ``DW_OP_xderef_type`` 3696 operations are not allowed because the call frame information must not depend 3697 on other debug sections. 3698 3699* ``DW_OP_push_object_address`` is not allowed because there is no object 3700 context to provide a value to push. 3701 3702* ``DW_OP_LLVM_push_lane`` is not allowed because the call frame instructions 3703 describe the actions for the whole thread, not the lanes independently. 3704 3705* ``DW_OP_call_frame_cfa`` and ``DW_OP_entry_value`` are not allowed because 3706 their use would be circular. 3707 3708* ``DW_OP_LLVM_call_frame_entry_reg`` is not allowed if evaluating E causes a 3709 circular dependency between ``DW_OP_LLVM_call_frame_entry_reg`` operations. 3710 3711 *For example, if a register R1 has a* ``DW_CFA_def_cfa_expression`` 3712 *instruction that evaluates a* ``DW_OP_LLVM_call_frame_entry_reg`` *operation 3713 that specifies register R2, and register R2 has a* 3714 ``DW_CFA_def_cfa_expression`` *instruction that that evaluates a* 3715 ``DW_OP_LLVM_call_frame_entry_reg`` *operation that specifies register R1.* 3716 3717*Call frame instructions to which these restrictions apply include* 3718``DW_CFA_def_cfa_expression``\ *,* ``DW_CFA_expression``\ *, and* 3719``DW_CFA_val_expression``\ *.* 3720 3721.. _amdgpu-dwarf-row-creation-instructions: 3722 3723Row Creation Instructions 3724######################### 3725 3726.. note:: 3727 3728 These instructions are the same as in DWARF Version 5 section 6.4.2.1. 3729 3730.. _amdgpu-dwarf-cfa-definition-instructions: 3731 3732CFA Definition Instructions 3733########################### 3734 37351. ``DW_CFA_def_cfa`` 3736 3737 The ``DW_CFA_def_cfa`` instruction takes two unsigned LEB128 operands 3738 representing a register number R and a (non-factored) byte displacement B. 3739 AS is set to the target architecture default address space identifier. The 3740 required action is to define the current CFA rule to be the result of 3741 evaluating the DWARF operation expression ``DW_OP_constu AS; 3742 DW_OP_aspace_bregx R, B`` as a location description. 3743 37442. ``DW_CFA_def_cfa_sf`` 3745 3746 The ``DW_CFA_def_cfa_sf`` instruction takes two operands: an unsigned LEB128 3747 value representing a register number R and a signed LEB128 factored byte 3748 displacement B. AS is set to the target architecture default address space 3749 identifier. The required action is to define the current CFA rule to be the 3750 result of evaluating the DWARF operation expression ``DW_OP_constu AS; 3751 DW_OP_aspace_bregx R, B*data_alignment_factor`` as a location description. 3752 3753 *The action is the same as* ``DW_CFA_def_cfa``\ *, except that the second 3754 operand is signed and factored.* 3755 37563. ``DW_CFA_LLVM_def_aspace_cfa`` *New* 3757 3758 The ``DW_CFA_LLVM_def_aspace_cfa`` instruction takes three unsigned LEB128 3759 operands representing a register number R, a (non-factored) byte 3760 displacement B, and a target architecture specific address space identifier 3761 AS. The required action is to define the current CFA rule to be the result 3762 of evaluating the DWARF operation expression ``DW_OP_constu AS; 3763 DW_OP_aspace_bregx R, B`` as a location description. 3764 3765 If AS is not one of the values defined by the target architecture specific 3766 ``DW_ASPACE_*`` values then the DWARF expression is ill-formed. 3767 37684. ``DW_CFA_LLVM_def_aspace_cfa_sf`` *New* 3769 3770 The ``DW_CFA_def_cfa_sf`` instruction takes three operands: an unsigned 3771 LEB128 value representing a register number R, a signed LEB128 factored byte 3772 displacement B, and an unsigned LEB128 value representing a target 3773 architecture specific address space identifier AS. The required action is to 3774 define the current CFA rule to be the result of evaluating the DWARF 3775 operation expression ``DW_OP_constu AS; DW_OP_aspace_bregx R, 3776 B*data_alignment_factor`` as a location description. 3777 3778 If AS is not one of the values defined by the target architecture specific 3779 ``DW_ASPACE_*`` values, then the DWARF expression is ill-formed. 3780 3781 *The action is the same as* ``DW_CFA_aspace_def_cfa``\ *, except that the 3782 second operand is signed and factored.* 3783 37845. ``DW_CFA_def_cfa_register`` 3785 3786 The ``DW_CFA_def_cfa_register`` instruction takes a single unsigned LEB128 3787 operand representing a register number R. The required action is to define 3788 the current CFA rule to be the result of evaluating the DWARF operation 3789 expression ``DW_OP_constu AS; DW_OP_aspace_bregx R, B`` as a location 3790 description. B and AS are the old CFA byte displacement and address space 3791 respectively. 3792 3793 If the subprogram has no current CFA rule, or the rule was defined by a 3794 ``DW_CFA_def_cfa_expression`` instruction, then the DWARF is ill-formed. 3795 37966. ``DW_CFA_def_cfa_offset`` 3797 3798 The ``DW_CFA_def_cfa_offset`` instruction takes a single unsigned LEB128 3799 operand representing a (non-factored) byte displacement B. The required 3800 action is to define the current CFA rule to be the result of evaluating the 3801 DWARF operation expression ``DW_OP_constu AS; DW_OP_aspace_bregx R, B`` as a 3802 location description. R and AS are the old CFA register number and address 3803 space respectively. 3804 3805 If the subprogram has no current CFA rule, or the rule was defined by a 3806 ``DW_CFA_def_cfa_expression`` instruction, then the DWARF is ill-formed. 3807 38087. ``DW_CFA_def_cfa_offset_sf`` 3809 3810 The ``DW_CFA_def_cfa_offset_sf`` instruction takes a signed LEB128 operand 3811 representing a factored byte displacement B. The required action is to 3812 define the current CFA rule to be the result of evaluating the DWARF 3813 operation expression ``DW_OP_constu AS; DW_OP_aspace_bregx R, 3814 B*data_alignment_factor`` as a location description. R and AS are the old 3815 CFA register number and address space respectively. 3816 3817 If the subprogram has no current CFA rule, or the rule was defined by a 3818 ``DW_CFA_def_cfa_expression`` instruction, then the DWARF is ill-formed. 3819 3820 *The action is the same as* ``DW_CFA_def_cfa_offset``\ *, except that the 3821 operand is signed and factored.* 3822 38238. ``DW_CFA_def_cfa_expression`` 3824 3825 The ``DW_CFA_def_cfa_expression`` instruction takes a single operand encoded 3826 as a ``DW_FORM_exprloc`` value representing a DWARF operation expression E. 3827 The required action is to define the current CFA rule to be the result of 3828 evaluating E with the current context, except the result kind is a location 3829 description, the compilation unit is unspecified, the object is unspecified, 3830 and an empty initial stack. 3831 3832 *See* :ref:`amdgpu-dwarf-call-frame-instructions` *regarding restrictions on 3833 the DWARF expression operations that can be used in E.* 3834 3835 The DWARF is ill-formed if the result of evaluating E is not a memory byte 3836 address location description. 3837 3838.. _amdgpu-dwarf-register-rule-instructions: 3839 3840Register Rule Instructions 3841########################## 3842 38431. ``DW_CFA_undefined`` 3844 3845 The ``DW_CFA_undefined`` instruction takes a single unsigned LEB128 operand 3846 that represents a register number R. The required action is to set the rule 3847 for the register specified by R to ``undefined``. 3848 38492. ``DW_CFA_same_value`` 3850 3851 The ``DW_CFA_same_value`` instruction takes a single unsigned LEB128 operand 3852 that represents a register number R. The required action is to set the rule 3853 for the register specified by R to ``same value``. 3854 38553. ``DW_CFA_offset`` 3856 3857 The ``DW_CFA_offset`` instruction takes two operands: a register number R 3858 (encoded with the opcode) and an unsigned LEB128 constant representing a 3859 factored displacement B. The required action is to change the rule for the 3860 register specified by R to be an *offset(B\*data_alignment_factor)* rule. 3861 3862 .. note:: 3863 3864 Seems this should be named ``DW_CFA_offset_uf`` since the offset is 3865 unsigned factored. 3866 38674. ``DW_CFA_offset_extended`` 3868 3869 The ``DW_CFA_offset_extended`` instruction takes two unsigned LEB128 3870 operands representing a register number R and a factored displacement B. 3871 This instruction is identical to ``DW_CFA_offset``, except for the encoding 3872 and size of the register operand. 3873 3874 .. note:: 3875 3876 Seems this should be named ``DW_CFA_offset_extended_uf`` since the 3877 displacement is unsigned factored. 3878 38795. ``DW_CFA_offset_extended_sf`` 3880 3881 The ``DW_CFA_offset_extended_sf`` instruction takes two operands: an 3882 unsigned LEB128 value representing a register number R and a signed LEB128 3883 factored displacement B. This instruction is identical to 3884 ``DW_CFA_offset_extended``, except that B is signed. 3885 38866. ``DW_CFA_val_offset`` 3887 3888 The ``DW_CFA_val_offset`` instruction takes two unsigned LEB128 operands 3889 representing a register number R and a factored displacement B. The required 3890 action is to change the rule for the register indicated by R to be a 3891 *val_offset(B\*data_alignment_factor)* rule. 3892 3893 .. note:: 3894 3895 Seems this should be named ``DW_CFA_val_offset_uf`` since the displacement 3896 is unsigned factored. 3897 3898 .. note:: 3899 3900 An alternative is to define ``DW_CFA_val_offset`` to implicitly use the 3901 target architecture default address space, and add another operation that 3902 specifies the address space. 3903 39047. ``DW_CFA_val_offset_sf`` 3905 3906 The ``DW_CFA_val_offset_sf`` instruction takes two operands: an unsigned 3907 LEB128 value representing a register number R and a signed LEB128 factored 3908 displacement B. This instruction is identical to ``DW_CFA_val_offset``, 3909 except that B is signed. 3910 39118. ``DW_CFA_register`` 3912 3913 The ``DW_CFA_register`` instruction takes two unsigned LEB128 operands 3914 representing register numbers R1 and R2 respectively. The required action is 3915 to set the rule for the register specified by R1 to be a *register(R2)* rule. 3916 39179. ``DW_CFA_expression`` 3918 3919 The ``DW_CFA_expression`` instruction takes two operands: an unsigned LEB128 3920 value representing a register number R, and a ``DW_FORM_block`` value 3921 representing a DWARF operation expression E. The required action is to 3922 change the rule for the register specified by R to be an *expression(E)* 3923 rule. 3924 3925 *That is, E computes the location description where the register value can 3926 be retrieved.* 3927 3928 *See* :ref:`amdgpu-dwarf-call-frame-instructions` *regarding restrictions on 3929 the DWARF expression operations that can be used in E.* 3930 393110. ``DW_CFA_val_expression`` 3932 3933 The ``DW_CFA_val_expression`` instruction takes two operands: an unsigned 3934 LEB128 value representing a register number R, and a ``DW_FORM_block`` value 3935 representing a DWARF operation expression E. The required action is to 3936 change the rule for the register specified by R to be a *val_expression(E)* 3937 rule. 3938 3939 *That is, E computes the value of register R.* 3940 3941 *See* :ref:`amdgpu-dwarf-call-frame-instructions` *regarding restrictions on 3942 the DWARF expression operations that can be used in E.* 3943 3944 If the result of evaluating E is not a value with a base type size that 3945 matches the register size, then the DWARF is ill-formed. 3946 394711. ``DW_CFA_restore`` 3948 3949 The ``DW_CFA_restore`` instruction takes a single operand (encoded with the 3950 opcode) that represents a register number R. The required action is to 3951 change the rule for the register specified by R to the rule assigned it by 3952 the ``initial_instructions`` in the CIE. 3953 395412. ``DW_CFA_restore_extended`` 3955 3956 The ``DW_CFA_restore_extended`` instruction takes a single unsigned LEB128 3957 operand that represents a register number R. This instruction is identical 3958 to ``DW_CFA_restore``, except for the encoding and size of the register 3959 operand. 3960 3961Row State Instructions 3962###################### 3963 3964.. note:: 3965 3966 These instructions are the same as in DWARF Version 5 section 6.4.2.4. 3967 3968Padding Instruction 3969################### 3970 3971.. note:: 3972 3973 These instructions are the same as in DWARF Version 5 section 6.4.2.5. 3974 3975Call Frame Instruction Usage 3976++++++++++++++++++++++++++++ 3977 3978.. note:: 3979 3980 The same as in DWARF Version 5 section 6.4.3. 3981 3982.. _amdgpu-dwarf-call-frame-calling-address: 3983 3984Call Frame Calling Address 3985++++++++++++++++++++++++++ 3986 3987.. note:: 3988 3989 The same as in DWARF Version 5 section 6.4.4. 3990 3991Data Representation 3992------------------- 3993 3994.. _amdgpu-dwarf-32-bit-and-64-bit-dwarf-formats: 3995 399632-Bit and 64-Bit DWARF Formats 3997~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3998 3999.. note:: 4000 4001 This augments DWARF Version 5 section 7.4. 4002 40031. Within the body of the ``.debug_info`` section, certain forms of attribute 4004 value depend on the choice of DWARF format as follows. For the 32-bit DWARF 4005 format, the value is a 4-byte unsigned integer; for the 64-bit DWARF format, 4006 the value is an 8-byte unsigned integer. 4007 4008 .. table:: ``.debug_info`` section attribute form roles 4009 :name: amdgpu-dwarf-debug-info-section-attribute-form-roles-table 4010 4011 ================================== =================================== 4012 Form Role 4013 ================================== =================================== 4014 DW_FORM_line_strp offset in ``.debug_line_str`` 4015 DW_FORM_ref_addr offset in ``.debug_info`` 4016 DW_FORM_sec_offset offset in a section other than 4017 ``.debug_info`` or ``.debug_str`` 4018 DW_FORM_strp offset in ``.debug_str`` 4019 DW_FORM_strp_sup offset in ``.debug_str`` section of 4020 supplementary object file 4021 DW_OP_call_ref offset in ``.debug_info`` 4022 DW_OP_implicit_pointer offset in ``.debug_info`` 4023 DW_OP_LLVM_aspace_implicit_pointer offset in ``.debug_info`` 4024 ================================== =================================== 4025 4026Format of Debugging Information 4027~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 4028 4029Attribute Encodings 4030+++++++++++++++++++ 4031 4032.. note:: 4033 4034 This augments DWARF Version 5 section 7.5.4 and Table 7.5. 4035 4036The following table gives the encoding of the additional debugging information 4037entry attributes. 4038 4039.. table:: Attribute encodings 4040 :name: amdgpu-dwarf-attribute-encodings-table 4041 4042 ================================== ====== =================================== 4043 Attribute Name Value Classes 4044 ================================== ====== =================================== 4045 DW_AT_LLVM_active_lane 0x3e08 exprloc, loclist 4046 DW_AT_LLVM_augmentation 0x3e09 string 4047 DW_AT_LLVM_lanes 0x3e0a constant 4048 DW_AT_LLVM_lane_pc 0x3e0b exprloc, loclist 4049 DW_AT_LLVM_vector_size 0x3e0c constant 4050 ================================== ====== =================================== 4051 4052DWARF Expressions 4053~~~~~~~~~~~~~~~~~ 4054 4055.. note:: 4056 4057 Rename DWARF Version 5 section 7.7 to reflect the unification of location 4058 descriptions into DWARF expressions. 4059 4060Operation Expressions 4061+++++++++++++++++++++ 4062 4063.. note:: 4064 4065 Rename DWARF Version 5 section 7.7.1 and delete section 7.7.2 to reflect the 4066 unification of location descriptions into DWARF expressions. 4067 4068 This augments DWARF Version 5 section 7.7.1 and Table 7.9. 4069 4070The following table gives the encoding of the additional DWARF expression 4071operations. 4072 4073.. table:: DWARF Operation Encodings 4074 :name: amdgpu-dwarf-operation-encodings-table 4075 4076 ================================== ===== ======== =============================== 4077 Operation Code Number Notes 4078 of 4079 Operands 4080 ================================== ===== ======== =============================== 4081 DW_OP_LLVM_form_aspace_address 0xe1 0 4082 DW_OP_LLVM_push_lane 0xe2 0 4083 DW_OP_LLVM_offset 0xe3 0 4084 DW_OP_LLVM_offset_uconst 0xe4 1 ULEB128 byte displacement 4085 DW_OP_LLVM_bit_offset 0xe5 0 4086 DW_OP_LLVM_call_frame_entry_reg 0xe6 1 ULEB128 register number 4087 DW_OP_LLVM_undefined 0xe7 0 4088 DW_OP_LLVM_aspace_bregx 0xe8 2 ULEB128 register number, 4089 ULEB128 byte displacement 4090 DW_OP_LLVM_aspace_implicit_pointer 0xe9 2 4-byte or 8-byte offset of DIE, 4091 SLEB128 byte displacement 4092 DW_OP_LLVM_piece_end 0xea 0 4093 DW_OP_LLVM_extend 0xeb 2 ULEB128 bit size, 4094 ULEB128 count 4095 DW_OP_LLVM_select_bit_piece 0xec 2 ULEB128 bit size, 4096 ULEB128 count 4097 ================================== ===== ======== =============================== 4098 4099Location List Expressions 4100+++++++++++++++++++++++++ 4101 4102.. note:: 4103 4104 Rename DWARF Version 5 section 7.7.3 to reflect that location lists are a kind 4105 of DWARF expression. 4106 4107Source Languages 4108~~~~~~~~~~~~~~~~ 4109 4110.. note:: 4111 4112 This augments DWARF Version 5 section 7.12 and Table 7.17. 4113 4114The following table gives the encoding of the additional DWARF languages. 4115 4116.. table:: Language encodings 4117 :name: amdgpu-dwarf-language-encodings-table 4118 4119 ==================== ====== =================== 4120 Language Name Value Default Lower Bound 4121 ==================== ====== =================== 4122 ``DW_LANG_LLVM_HIP`` 0x8100 0 4123 ==================== ====== =================== 4124 4125Address Class and Address Space Encodings 4126~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 4127 4128.. note:: 4129 4130 This replaces DWARF Version 5 section 7.13. 4131 4132The encodings of the constants used for the currently defined address classes 4133are given in :ref:`amdgpu-dwarf-address-class-encodings-table`. 4134 4135.. table:: Address class encodings 4136 :name: amdgpu-dwarf-address-class-encodings-table 4137 4138 ========================== ====== 4139 Address Class Name Value 4140 ========================== ====== 4141 ``DW_ADDR_none`` 0x0000 4142 ``DW_ADDR_LLVM_global`` 0x0001 4143 ``DW_ADDR_LLVM_constant`` 0x0002 4144 ``DW_ADDR_LLVM_group`` 0x0003 4145 ``DW_ADDR_LLVM_private`` 0x0004 4146 ``DW_ADDR_LLVM_lo_user`` 0x8000 4147 ``DW_ADDR_LLVM_hi_user`` 0xffff 4148 ========================== ====== 4149 4150Line Number Information 4151~~~~~~~~~~~~~~~~~~~~~~~ 4152 4153.. note:: 4154 4155 This augments DWARF Version 5 section 7.22 and Table 7.27. 4156 4157The following table gives the encoding of the additional line number header 4158entry formats. 4159 4160.. table:: Line number header entry format encodings 4161 :name: amdgpu-dwarf-line-number-header-entry-format-encodings-table 4162 4163 ==================================== ==================== 4164 Line number header entry format name Value 4165 ==================================== ==================== 4166 ``DW_LNCT_LLVM_source`` 0x2001 4167 ``DW_LNCT_LLVM_is_MD5`` 0x2002 4168 ==================================== ==================== 4169 4170Call Frame Information 4171~~~~~~~~~~~~~~~~~~~~~~ 4172 4173.. note:: 4174 4175 This augments DWARF Version 5 section 7.24 and Table 7.29. 4176 4177The following table gives the encoding of the additional call frame information 4178instructions. 4179 4180.. table:: Call frame instruction encodings 4181 :name: amdgpu-dwarf-call-frame-instruction-encodings-table 4182 4183 ============================= ====== ====== ================ ================ ===================== 4184 Instruction High 2 Low 6 Operand 1 Operand 2 Operand 3 4185 Bits Bits 4186 ============================= ====== ====== ================ ================ ===================== 4187 DW_CFA_LLVM_def_aspace_cfa 0 0x30 ULEB128 register ULEB128 offset ULEB128 address space 4188 DW_CFA_LLVM_def_aspace_cfa_sf 0 0x31 ULEB128 register SLEB128 offset ULEB128 address space 4189 ============================= ====== ====== ================ ================ ===================== 4190 4191Attributes by Tag Value (Informative) 4192------------------------------------- 4193 4194.. note:: 4195 4196 This augments DWARF Version 5 Appendix A and Table A.1. 4197 4198The following table provides the additional attributes that are applicable to 4199debugger information entries. 4200 4201.. table:: Attributes by tag value 4202 :name: amdgpu-dwarf-attributes-by-tag-value-table 4203 4204 ============================= ============================= 4205 Tag Name Applicable Attributes 4206 ============================= ============================= 4207 ``DW_TAG_base_type`` * ``DW_AT_LLVM_vector_size`` 4208 ``DW_TAG_compile_unit`` * ``DW_AT_LLVM_augmentation`` 4209 ``DW_TAG_entry_point`` * ``DW_AT_LLVM_active_lane`` 4210 * ``DW_AT_LLVM_lane_pc`` 4211 * ``DW_AT_LLVM_lanes`` 4212 ``DW_TAG_inlined_subroutine`` * ``DW_AT_LLVM_active_lane`` 4213 * ``DW_AT_LLVM_lane_pc`` 4214 * ``DW_AT_LLVM_lanes`` 4215 ``DW_TAG_subprogram`` * ``DW_AT_LLVM_active_lane`` 4216 * ``DW_AT_LLVM_lane_pc`` 4217 * ``DW_AT_LLVM_lanes`` 4218 ============================= ============================= 4219 4220.. _amdgpu-dwarf-examples: 4221 4222Examples 4223======== 4224 4225The AMD GPU specific usage of the features in these extensions, including 4226examples, is available at *User Guide for AMDGPU Backend* section 4227:ref:`amdgpu-dwarf-debug-information`. 4228 4229.. note:: 4230 4231 Change examples to use ``DW_OP_LLVM_offset`` instead of ``DW_OP_add`` when 4232 acting on a location description. 4233 4234 Need to provide examples of new features. 4235 4236.. _amdgpu-dwarf-references: 4237 4238References 4239========== 4240 4241 .. _amdgpu-dwarf-AMD: 4242 42431. [AMD] `Advanced Micro Devices <https://www.amd.com/>`__ 4244 4245 .. _amdgpu-dwarf-AMD-ROCm: 4246 42472. [AMD-ROCm] `AMD ROCm Platform <https://rocm-documentation.readthedocs.io>`__ 4248 4249 .. _amdgpu-dwarf-AMD-ROCgdb: 4250 42513. [AMD-ROCgdb] `AMD ROCm Debugger (ROCgdb) <https://github.com/ROCm-Developer-Tools/ROCgdb>`__ 4252 4253 .. _amdgpu-dwarf-AMDGPU-LLVM: 4254 42554. [AMDGPU-LLVM] `User Guide for AMDGPU LLVM Backend <https://llvm.org/docs/AMDGPUUsage.html>`__ 4256 4257 .. _amdgpu-dwarf-CUDA: 4258 42595. [CUDA] `Nvidia CUDA Language <https://docs.nvidia.com/cuda/cuda-c-programming-guide/>`__ 4260 4261 .. _amdgpu-dwarf-DWARF: 4262 42636. [DWARF] `DWARF Debugging Information Format <http://dwarfstd.org/>`__ 4264 4265 .. _amdgpu-dwarf-ELF: 4266 42677. [ELF] `Executable and Linkable Format (ELF) <http://www.sco.com/developers/gabi/>`__ 4268 4269 .. _amdgpu-dwarf-GCC: 4270 42718. [GCC] `GCC: The GNU Compiler Collection <https://www.gnu.org/software/gcc/>`__ 4272 4273 .. _amdgpu-dwarf-GDB: 4274 42759. [GDB] `GDB: The GNU Project Debugger <https://www.gnu.org/software/gdb/>`__ 4276 4277 .. _amdgpu-dwarf-HIP: 4278 427910. [HIP] `HIP Programming Guide <https://rocm-documentation.readthedocs.io/en/latest/Programming_Guides/Programming-Guides.html#hip-programing-guide>`__ 4280 4281 .. _amdgpu-dwarf-HSA: 4282 428311. [HSA] `Heterogeneous System Architecture (HSA) Foundation <http://www.hsafoundation.com/>`__ 4284 4285 .. _amdgpu-dwarf-LLVM: 4286 428712. [LLVM] `The LLVM Compiler Infrastructure <https://llvm.org/>`__ 4288 4289 .. _amdgpu-dwarf-OpenCL: 4290 429113. [OpenCL] `The OpenCL Specification Version 2.0 <http://www.khronos.org/registry/cl/specs/opencl-2.0.pdf>`__ 4292 4293 .. _amdgpu-dwarf-Perforce-TotalView: 4294 429514. [Perforce-TotalView] `Perforce TotalView HPC Debugging Software <https://totalview.io/products/totalview>`__ 4296 4297 .. _amdgpu-dwarf-SEMVER: 4298 429915. [SEMVER] `Semantic Versioning <https://semver.org/>`__ 4300