1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s 3 4; ANDV 5 6define i1 @andv_nxv32i1(<vscale x 32 x i1> %a) { 7; CHECK-LABEL: andv_nxv32i1: 8; CHECK: // %bb.0: 9; CHECK-NEXT: ptrue p2.b 10; CHECK-NEXT: and p0.b, p2/z, p0.b, p1.b 11; CHECK-NEXT: not p0.b, p2/z, p0.b 12; CHECK-NEXT: ptest p2, p0.b 13; CHECK-NEXT: cset w0, eq 14; CHECK-NEXT: ret 15 %res = call i1 @llvm.vector.reduce.and.nxv32i1(<vscale x 32 x i1> %a) 16 ret i1 %res 17} 18 19define i1 @andv_nxv64i1(<vscale x 64 x i1> %a) { 20; CHECK-LABEL: andv_nxv64i1: 21; CHECK: // %bb.0: 22; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 23; CHECK-NEXT: addvl sp, sp, #-1 24; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Folded Spill 25; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG 26; CHECK-NEXT: .cfi_offset w29, -16 27; CHECK-NEXT: ptrue p4.b 28; CHECK-NEXT: and p1.b, p4/z, p1.b, p3.b 29; CHECK-NEXT: and p0.b, p4/z, p0.b, p2.b 30; CHECK-NEXT: and p0.b, p4/z, p0.b, p1.b 31; CHECK-NEXT: not p0.b, p4/z, p0.b 32; CHECK-NEXT: ptest p4, p0.b 33; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Folded Reload 34; CHECK-NEXT: cset w0, eq 35; CHECK-NEXT: addvl sp, sp, #1 36; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 37; CHECK-NEXT: ret 38 %res = call i1 @llvm.vector.reduce.and.nxv64i1(<vscale x 64 x i1> %a) 39 ret i1 %res 40} 41 42; ORV 43 44define i1 @orv_nxv32i1(<vscale x 32 x i1> %a) { 45; CHECK-LABEL: orv_nxv32i1: 46; CHECK: // %bb.0: 47; CHECK-NEXT: ptrue p2.b 48; CHECK-NEXT: orr p0.b, p2/z, p0.b, p1.b 49; CHECK-NEXT: ptest p2, p0.b 50; CHECK-NEXT: cset w0, ne 51; CHECK-NEXT: ret 52 %res = call i1 @llvm.vector.reduce.or.nxv32i1(<vscale x 32 x i1> %a) 53 ret i1 %res 54} 55 56; XORV 57 58define i1 @xorv_nxv32i1(<vscale x 32 x i1> %a) { 59; CHECK-LABEL: xorv_nxv32i1: 60; CHECK: // %bb.0: 61; CHECK-NEXT: ptrue p2.b 62; CHECK-NEXT: eor p0.b, p2/z, p0.b, p1.b 63; CHECK-NEXT: cntp x8, p2, p0.b 64; CHECK-NEXT: and w0, w8, #0x1 65; CHECK-NEXT: ret 66 %res = call i1 @llvm.vector.reduce.xor.nxv32i1(<vscale x 32 x i1> %a) 67 ret i1 %res 68} 69 70; SMAXV 71 72define i1 @smaxv_nxv32i1(<vscale x 32 x i1> %a) { 73; CHECK-LABEL: smaxv_nxv32i1: 74; CHECK: // %bb.0: 75; CHECK-NEXT: ptrue p2.b 76; CHECK-NEXT: and p0.b, p2/z, p0.b, p1.b 77; CHECK-NEXT: not p0.b, p2/z, p0.b 78; CHECK-NEXT: ptest p2, p0.b 79; CHECK-NEXT: cset w0, eq 80; CHECK-NEXT: ret 81 %res = call i1 @llvm.vector.reduce.smax.nxv32i1(<vscale x 32 x i1> %a) 82 ret i1 %res 83} 84 85; SMINV 86 87define i1 @sminv_nxv32i1(<vscale x 32 x i1> %a) { 88; CHECK-LABEL: sminv_nxv32i1: 89; CHECK: // %bb.0: 90; CHECK-NEXT: ptrue p2.b 91; CHECK-NEXT: orr p0.b, p2/z, p0.b, p1.b 92; CHECK-NEXT: ptest p2, p0.b 93; CHECK-NEXT: cset w0, ne 94; CHECK-NEXT: ret 95 %res = call i1 @llvm.vector.reduce.smin.nxv32i1(<vscale x 32 x i1> %a) 96 ret i1 %res 97} 98 99; UMAXV 100 101define i1 @umaxv_nxv32i1(<vscale x 32 x i1> %a) { 102; CHECK-LABEL: umaxv_nxv32i1: 103; CHECK: // %bb.0: 104; CHECK-NEXT: ptrue p2.b 105; CHECK-NEXT: orr p0.b, p2/z, p0.b, p1.b 106; CHECK-NEXT: ptest p2, p0.b 107; CHECK-NEXT: cset w0, ne 108; CHECK-NEXT: ret 109 %res = call i1 @llvm.vector.reduce.umax.nxv32i1(<vscale x 32 x i1> %a) 110 ret i1 %res 111} 112 113; UMINV 114 115define i1 @uminv_nxv32i1(<vscale x 32 x i1> %a) { 116; CHECK-LABEL: uminv_nxv32i1: 117; CHECK: // %bb.0: 118; CHECK-NEXT: ptrue p2.b 119; CHECK-NEXT: and p0.b, p2/z, p0.b, p1.b 120; CHECK-NEXT: not p0.b, p2/z, p0.b 121; CHECK-NEXT: ptest p2, p0.b 122; CHECK-NEXT: cset w0, eq 123; CHECK-NEXT: ret 124 %res = call i1 @llvm.vector.reduce.umin.nxv32i1(<vscale x 32 x i1> %a) 125 ret i1 %res 126} 127 128declare i1 @llvm.vector.reduce.and.nxv32i1(<vscale x 32 x i1>) 129declare i1 @llvm.vector.reduce.and.nxv64i1(<vscale x 64 x i1>) 130 131declare i1 @llvm.vector.reduce.or.nxv32i1(<vscale x 32 x i1>) 132 133declare i1 @llvm.vector.reduce.xor.nxv32i1(<vscale x 32 x i1>) 134 135declare i1 @llvm.vector.reduce.smax.nxv32i1(<vscale x 32 x i1>) 136 137declare i1 @llvm.vector.reduce.smin.nxv32i1(<vscale x 32 x i1>) 138 139declare i1 @llvm.vector.reduce.umax.nxv32i1(<vscale x 32 x i1>) 140 141declare i1 @llvm.vector.reduce.umin.nxv32i1(<vscale x 32 x i1>) 142