1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=GCN %s 3# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -run-pass=legalizer %s -o - | FileCheck -check-prefix=GCN %s 4 5--- 6name: s_buffer_load_s32 7body: | 8 bb.0: 9 liveins: $sgpr0_sgpr1_sgpr2_sgpr3 10 11 ; GCN-LABEL: name: s_buffer_load_s32 12 ; GCN: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 13 ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 14 ; GCN: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_S_BUFFER_LOAD [[COPY]](<4 x s32>), [[C]](s32), 0 :: (dereferenceable invariant load (s32)) 15 ; GCN: S_ENDPGM 0, implicit [[AMDGPU_S_BUFFER_LOAD]](s32) 16 %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 17 %1:_(s32) = G_CONSTANT i32 0 18 %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), %0, %1, 0 19 S_ENDPGM 0, implicit %2 20 21... 22 23--- 24name: s_buffer_load_v3s32 25body: | 26 bb.0: 27 liveins: $sgpr0_sgpr1_sgpr2_sgpr3 28 29 ; GCN-LABEL: name: s_buffer_load_v3s32 30 ; GCN: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 31 ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 32 ; GCN: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[COPY]](<4 x s32>), [[C]](s32), 0 :: (dereferenceable invariant load (s96), align 4) 33 ; GCN: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF 34 ; GCN: [[CONCAT_VECTORS:%[0-9]+]]:_(<12 x s32>) = G_CONCAT_VECTORS [[AMDGPU_S_BUFFER_LOAD]](<4 x s32>), [[DEF]](<4 x s32>), [[DEF]](<4 x s32>) 35 ; GCN: [[UV:%[0-9]+]]:_(<3 x s32>), [[UV1:%[0-9]+]]:_(<3 x s32>), [[UV2:%[0-9]+]]:_(<3 x s32>), [[UV3:%[0-9]+]]:_(<3 x s32>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<12 x s32>) 36 ; GCN: S_ENDPGM 0, implicit [[UV]](<3 x s32>) 37 %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 38 %1:_(s32) = G_CONSTANT i32 0 39 %2:_(<3 x s32>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), %0, %1, 0 40 S_ENDPGM 0, implicit %2 41 42... 43 44--- 45name: s_buffer_load_v3p3 46body: | 47 bb.0: 48 liveins: $sgpr0_sgpr1_sgpr2_sgpr3 49 50 ; GCN-LABEL: name: s_buffer_load_v3p3 51 ; GCN: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 52 ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 53 ; GCN: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[COPY]](<4 x s32>), [[C]](s32), 0 :: (dereferenceable invariant load (s96), align 4) 54 ; GCN: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF 55 ; GCN: [[CONCAT_VECTORS:%[0-9]+]]:_(<12 x s32>) = G_CONCAT_VECTORS [[AMDGPU_S_BUFFER_LOAD]](<4 x s32>), [[DEF]](<4 x s32>), [[DEF]](<4 x s32>) 56 ; GCN: [[UV:%[0-9]+]]:_(<3 x s32>), [[UV1:%[0-9]+]]:_(<3 x s32>), [[UV2:%[0-9]+]]:_(<3 x s32>), [[UV3:%[0-9]+]]:_(<3 x s32>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<12 x s32>) 57 ; GCN: [[BITCAST:%[0-9]+]]:_(<3 x p3>) = G_BITCAST [[UV]](<3 x s32>) 58 ; GCN: S_ENDPGM 0, implicit [[BITCAST]](<3 x p3>) 59 %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 60 %1:_(s32) = G_CONSTANT i32 0 61 %2:_(<3 x p3>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), %0, %1, 0 62 S_ENDPGM 0, implicit %2 63 64... 65 66--- 67name: s_buffer_load_v6s16 68body: | 69 bb.0: 70 liveins: $sgpr0_sgpr1_sgpr2_sgpr3 71 72 ; GCN-LABEL: name: s_buffer_load_v6s16 73 ; GCN: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 74 ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 75 ; GCN: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[COPY]](<4 x s32>), [[C]](s32), 0 :: (dereferenceable invariant load (s96), align 4) 76 ; GCN: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF 77 ; GCN: [[CONCAT_VECTORS:%[0-9]+]]:_(<12 x s32>) = G_CONCAT_VECTORS [[AMDGPU_S_BUFFER_LOAD]](<4 x s32>), [[DEF]](<4 x s32>), [[DEF]](<4 x s32>) 78 ; GCN: [[UV:%[0-9]+]]:_(<3 x s32>), [[UV1:%[0-9]+]]:_(<3 x s32>), [[UV2:%[0-9]+]]:_(<3 x s32>), [[UV3:%[0-9]+]]:_(<3 x s32>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<12 x s32>) 79 ; GCN: [[BITCAST:%[0-9]+]]:_(<6 x s16>) = G_BITCAST [[UV]](<3 x s32>) 80 ; GCN: S_ENDPGM 0, implicit [[BITCAST]](<6 x s16>) 81 %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 82 %1:_(s32) = G_CONSTANT i32 0 83 %2:_(<6 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), %0, %1, 0 84 S_ENDPGM 0, implicit %2 85 86... 87 88--- 89name: s_buffer_load_v6s32 90body: | 91 bb.0: 92 liveins: $sgpr0_sgpr1_sgpr2_sgpr3 93 94 ; GCN-LABEL: name: s_buffer_load_v6s32 95 ; GCN: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 96 ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 97 ; GCN: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:_(<8 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[COPY]](<4 x s32>), [[C]](s32), 0 :: (dereferenceable invariant load (s192), align 4) 98 ; GCN: [[DEF:%[0-9]+]]:_(<8 x s32>) = G_IMPLICIT_DEF 99 ; GCN: [[CONCAT_VECTORS:%[0-9]+]]:_(<24 x s32>) = G_CONCAT_VECTORS [[AMDGPU_S_BUFFER_LOAD]](<8 x s32>), [[DEF]](<8 x s32>), [[DEF]](<8 x s32>) 100 ; GCN: [[UV:%[0-9]+]]:_(<6 x s32>), [[UV1:%[0-9]+]]:_(<6 x s32>), [[UV2:%[0-9]+]]:_(<6 x s32>), [[UV3:%[0-9]+]]:_(<6 x s32>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<24 x s32>) 101 ; GCN: S_ENDPGM 0, implicit [[UV]](<6 x s32>) 102 %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 103 %1:_(s32) = G_CONSTANT i32 0 104 %2:_(<6 x s32>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), %0, %1, 0 105 S_ENDPGM 0, implicit %2 106 107... 108 109--- 110name: s_buffer_load_v3s64 111body: | 112 bb.0: 113 liveins: $sgpr0_sgpr1_sgpr2_sgpr3 114 115 ; GCN-LABEL: name: s_buffer_load_v3s64 116 ; GCN: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 117 ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 118 ; GCN: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:_(<4 x s64>) = G_AMDGPU_S_BUFFER_LOAD [[COPY]](<4 x s32>), [[C]](s32), 0 :: (dereferenceable invariant load (s192), align 4) 119 ; GCN: [[DEF:%[0-9]+]]:_(<4 x s64>) = G_IMPLICIT_DEF 120 ; GCN: [[CONCAT_VECTORS:%[0-9]+]]:_(<12 x s64>) = G_CONCAT_VECTORS [[AMDGPU_S_BUFFER_LOAD]](<4 x s64>), [[DEF]](<4 x s64>), [[DEF]](<4 x s64>) 121 ; GCN: [[UV:%[0-9]+]]:_(<3 x s64>), [[UV1:%[0-9]+]]:_(<3 x s64>), [[UV2:%[0-9]+]]:_(<3 x s64>), [[UV3:%[0-9]+]]:_(<3 x s64>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<12 x s64>) 122 ; GCN: S_ENDPGM 0, implicit [[UV]](<3 x s64>) 123 %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 124 %1:_(s32) = G_CONSTANT i32 0 125 %2:_(<3 x s64>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), %0, %1, 0 126 S_ENDPGM 0, implicit %2 127 128... 129 130--- 131name: s_buffer_load_v12s8 132body: | 133 bb.0: 134 liveins: $sgpr0_sgpr1_sgpr2_sgpr3 135 136 ; GCN-LABEL: name: s_buffer_load_v12s8 137 ; GCN: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 138 ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 139 ; GCN: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[COPY]](<4 x s32>), [[C]](s32), 0 :: (dereferenceable invariant load (s96), align 4) 140 ; GCN: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF 141 ; GCN: [[CONCAT_VECTORS:%[0-9]+]]:_(<12 x s32>) = G_CONCAT_VECTORS [[AMDGPU_S_BUFFER_LOAD]](<4 x s32>), [[DEF]](<4 x s32>), [[DEF]](<4 x s32>) 142 ; GCN: [[UV:%[0-9]+]]:_(<3 x s32>), [[UV1:%[0-9]+]]:_(<3 x s32>), [[UV2:%[0-9]+]]:_(<3 x s32>), [[UV3:%[0-9]+]]:_(<3 x s32>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<12 x s32>) 143 ; GCN: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](<3 x s32>) 144 ; GCN: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 145 ; GCN: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C1]](s32) 146 ; GCN: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 147 ; GCN: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C2]](s32) 148 ; GCN: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 149 ; GCN: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C3]](s32) 150 ; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV4]](s32) 151 ; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) 152 ; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32) 153 ; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32) 154 ; GCN: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C1]](s32) 155 ; GCN: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C2]](s32) 156 ; GCN: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C3]](s32) 157 ; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV5]](s32) 158 ; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32) 159 ; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32) 160 ; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32) 161 ; GCN: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C1]](s32) 162 ; GCN: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C2]](s32) 163 ; GCN: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C3]](s32) 164 ; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV6]](s32) 165 ; GCN: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32) 166 ; GCN: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32) 167 ; GCN: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32) 168 ; GCN: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 169 ; GCN: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) 170 ; GCN: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C4]] 171 ; GCN: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32) 172 ; GCN: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C4]] 173 ; GCN: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32) 174 ; GCN: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]] 175 ; GCN: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32) 176 ; GCN: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32) 177 ; GCN: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C4]] 178 ; GCN: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32) 179 ; GCN: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C4]] 180 ; GCN: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32) 181 ; GCN: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]] 182 ; GCN: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32) 183 ; GCN: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32) 184 ; GCN: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C4]] 185 ; GCN: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32) 186 ; GCN: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C4]] 187 ; GCN: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32) 188 ; GCN: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]] 189 ; GCN: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32) 190 ; GCN: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY7]](s32) 191 ; GCN: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C4]] 192 ; GCN: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32) 193 ; GCN: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C4]] 194 ; GCN: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32) 195 ; GCN: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]] 196 ; GCN: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32) 197 ; GCN: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32) 198 ; GCN: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C4]] 199 ; GCN: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32) 200 ; GCN: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C4]] 201 ; GCN: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C2]](s32) 202 ; GCN: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL4]] 203 ; GCN: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32) 204 ; GCN: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32) 205 ; GCN: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C4]] 206 ; GCN: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32) 207 ; GCN: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C4]] 208 ; GCN: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32) 209 ; GCN: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL5]] 210 ; GCN: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32) 211 ; GCN: [[CONCAT_VECTORS1:%[0-9]+]]:_(<12 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>) 212 ; GCN: S_ENDPGM 0, implicit [[CONCAT_VECTORS1]](<12 x s16>) 213 %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 214 %1:_(s32) = G_CONSTANT i32 0 215 %2:_(<12 x s8>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), %0, %1, 0 216 %3:_(<12 x s16>) = G_ANYEXT %2 217 S_ENDPGM 0, implicit %3 218 219... 220 221--- 222name: s_buffer_load_s96 223body: | 224 bb.0: 225 liveins: $sgpr0_sgpr1_sgpr2_sgpr3 226 227 ; GCN-LABEL: name: s_buffer_load_s96 228 ; GCN: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 229 ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 230 ; GCN: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[COPY]](<4 x s32>), [[C]](s32), 0 :: (dereferenceable invariant load (s96), align 4) 231 ; GCN: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF 232 ; GCN: [[CONCAT_VECTORS:%[0-9]+]]:_(<12 x s32>) = G_CONCAT_VECTORS [[AMDGPU_S_BUFFER_LOAD]](<4 x s32>), [[DEF]](<4 x s32>), [[DEF]](<4 x s32>) 233 ; GCN: [[UV:%[0-9]+]]:_(<3 x s32>), [[UV1:%[0-9]+]]:_(<3 x s32>), [[UV2:%[0-9]+]]:_(<3 x s32>), [[UV3:%[0-9]+]]:_(<3 x s32>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<12 x s32>) 234 ; GCN: S_ENDPGM 0, implicit [[UV]](<3 x s32>) 235 %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 236 %1:_(s32) = G_CONSTANT i32 0 237 %2:_(<3 x s32>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), %0, %1, 0 238 S_ENDPGM 0, implicit %2 239 240... 241