1; RUN: llc -march=hexagon < %s | FileCheck %s
2
3; CHECK-LABEL: test0000:
4; CHECK: v0.h = vasl(v0.h,r0)
5define <64 x i16> @test0000(<64 x i16> %a0, i16 %a1) #0 {
6  %b0 = insertelement <64 x i16> zeroinitializer, i16 %a1, i32 0
7  %b1 = shufflevector <64 x i16> %b0, <64 x i16> undef, <64 x i32> zeroinitializer
8  %v0 = shl <64 x i16> %a0, %b1
9  ret <64 x i16> %v0
10}
11
12; CHECK-LABEL: test0001:
13; CHECK: v0.h = vasr(v0.h,r0)
14define <64 x i16> @test0001(<64 x i16> %a0, i16 %a1) #0 {
15  %b0 = insertelement <64 x i16> zeroinitializer, i16 %a1, i32 0
16  %b1 = shufflevector <64 x i16> %b0, <64 x i16> undef, <64 x i32> zeroinitializer
17  %v0 = ashr <64 x i16> %a0, %b1
18  ret <64 x i16> %v0
19}
20
21; CHECK-LABEL: test0002:
22; CHECK: v0.uh = vlsr(v0.uh,r0)
23define <64 x i16> @test0002(<64 x i16> %a0, i16 %a1) #0 {
24  %b0 = insertelement <64 x i16> zeroinitializer, i16 %a1, i32 0
25  %b1 = shufflevector <64 x i16> %b0, <64 x i16> undef, <64 x i32> zeroinitializer
26  %v0 = lshr <64 x i16> %a0, %b1
27  ret <64 x i16> %v0
28}
29
30; CHECK-LABEL: test0010:
31; CHECK: v0.w = vasl(v0.w,r0)
32define <32 x i32> @test0010(<32 x i32> %a0, i32 %a1) #0 {
33  %b0 = insertelement <32 x i32> zeroinitializer, i32 %a1, i32 0
34  %b1 = shufflevector <32 x i32> %b0, <32 x i32> undef, <32 x i32> zeroinitializer
35  %v0 = shl <32 x i32> %a0, %b1
36  ret <32 x i32> %v0
37}
38
39; CHECK-LABEL: test0011:
40; CHECK: v0.w = vasr(v0.w,r0)
41define <32 x i32> @test0011(<32 x i32> %a0, i32 %a1) #0 {
42  %b0 = insertelement <32 x i32> zeroinitializer, i32 %a1, i32 0
43  %b1 = shufflevector <32 x i32> %b0, <32 x i32> undef, <32 x i32> zeroinitializer
44  %v0 = ashr <32 x i32> %a0, %b1
45  ret <32 x i32> %v0
46}
47
48; CHECK-LABEL: test0012:
49; CHECK: v0.uw = vlsr(v0.uw,r0)
50define <32 x i32> @test0012(<32 x i32> %a0, i32 %a1) #0 {
51  %b0 = insertelement <32 x i32> zeroinitializer, i32 %a1, i32 0
52  %b1 = shufflevector <32 x i32> %b0, <32 x i32> undef, <32 x i32> zeroinitializer
53  %v0 = lshr <32 x i32> %a0, %b1
54  ret <32 x i32> %v0
55}
56
57; CHECK-LABEL: test0013:
58; CHECK: v0.w += vasl(v1.w,r0)
59define <32 x i32> @test0013(<32 x i32> %a0, <32 x i32> %a1, i32 %a2) #0 {
60  %b0 = insertelement <32 x i32> zeroinitializer, i32 %a2, i32 0
61  %b1 = shufflevector <32 x i32> %b0, <32 x i32> undef, <32 x i32> zeroinitializer
62  %v0 = shl <32 x i32> %a1, %b1
63  %v1 = add <32 x i32> %a0, %v0
64  ret <32 x i32> %v1
65}
66
67; CHECK-LABEL: test0014:
68; CHECK: v0.w += vasr(v1.w,r0)
69define <32 x i32> @test0014(<32 x i32> %a0, <32 x i32> %a1, i32 %a2) #0 {
70  %b0 = insertelement <32 x i32> zeroinitializer, i32 %a2, i32 0
71  %b1 = shufflevector <32 x i32> %b0, <32 x i32> undef, <32 x i32> zeroinitializer
72  %v0 = ashr <32 x i32> %a1, %b1
73  %v1 = add <32 x i32> %a0, %v0
74  ret <32 x i32> %v1
75}
76
77; CHECK-LABEL: test0020:
78; CHECK: v0.h = vasl(v0.h,v1.h)
79define <64 x i16> @test0020(<64 x i16> %a0, <64 x i16> %a1) #0 {
80  %v0 = shl <64 x i16> %a0, %a1
81  ret <64 x i16> %v0
82}
83
84; CHECK-LABEL: test0021:
85; CHECK: v0.h = vasr(v0.h,v1.h)
86define <64 x i16> @test0021(<64 x i16> %a0, <64 x i16> %a1) #0 {
87  %v0 = ashr <64 x i16> %a0, %a1
88  ret <64 x i16> %v0
89}
90
91; CHECK-LABEL: test0022:
92; CHECK: v0.h = vlsr(v0.h,v1.h)
93define <64 x i16> @test0022(<64 x i16> %a0, <64 x i16> %a1) #0 {
94  %v0 = lshr <64 x i16> %a0, %a1
95  ret <64 x i16> %v0
96}
97
98; CHECK-LABEL: test0030:
99; CHECK: v0.w = vasl(v0.w,v1.w)
100define <32 x i32> @test0030(<32 x i32> %a0, <32 x i32> %a1) #0 {
101  %v0 = shl <32 x i32> %a0, %a1
102  ret <32 x i32> %v0
103}
104
105; CHECK-LABEL: test0031:
106; CHECK: v0.w = vasr(v0.w,v1.w)
107define <32 x i32> @test0031(<32 x i32> %a0, <32 x i32> %a1) #0 {
108  %v0 = ashr <32 x i32> %a0, %a1
109  ret <32 x i32> %v0
110}
111
112; CHECK-LABEL: test0032:
113; CHECK: v0.w = vlsr(v0.w,v1.w)
114define <32 x i32> @test0032(<32 x i32> %a0, <32 x i32> %a1) #0 {
115  %v0 = lshr <32 x i32> %a0, %a1
116  ret <32 x i32> %v0
117}
118
119attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
120
121