1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s --check-prefixes=CHECK,RV32
4; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s --check-prefixes=CHECK,RV64
6
7declare <2 x i8> @llvm.vp.sub.v2i8(<2 x i8>, <2 x i8>, <2 x i1>, i32)
8
9define <2 x i8> @vrsub_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl) {
10; CHECK-LABEL: vrsub_vx_v2i8:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, mu
13; CHECK-NEXT:    vrsub.vx v8, v8, a0, v0.t
14; CHECK-NEXT:    ret
15  %elt.head = insertelement <2 x i8> undef, i8 %b, i32 0
16  %vb = shufflevector <2 x i8> %elt.head, <2 x i8> undef, <2 x i32> zeroinitializer
17  %v = call <2 x i8> @llvm.vp.sub.v2i8(<2 x i8> %vb, <2 x i8> %va, <2 x i1> %m, i32 %evl)
18  ret <2 x i8> %v
19}
20
21define <2 x i8> @vrsub_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) {
22; CHECK-LABEL: vrsub_vx_v2i8_unmasked:
23; CHECK:       # %bb.0:
24; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, mu
25; CHECK-NEXT:    vrsub.vx v8, v8, a0
26; CHECK-NEXT:    ret
27  %elt.head = insertelement <2 x i8> undef, i8 %b, i32 0
28  %vb = shufflevector <2 x i8> %elt.head, <2 x i8> undef, <2 x i32> zeroinitializer
29  %head = insertelement <2 x i1> undef, i1 true, i32 0
30  %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer
31  %v = call <2 x i8> @llvm.vp.sub.v2i8(<2 x i8> %vb, <2 x i8> %va, <2 x i1> %m, i32 %evl)
32  ret <2 x i8> %v
33}
34
35define <2 x i8> @vrsub_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {
36; CHECK-LABEL: vrsub_vi_v2i8:
37; CHECK:       # %bb.0:
38; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu
39; CHECK-NEXT:    vrsub.vi v8, v8, 2, v0.t
40; CHECK-NEXT:    ret
41  %elt.head = insertelement <2 x i8> undef, i8 2, i32 0
42  %vb = shufflevector <2 x i8> %elt.head, <2 x i8> undef, <2 x i32> zeroinitializer
43  %v = call <2 x i8> @llvm.vp.sub.v2i8(<2 x i8> %vb, <2 x i8> %va, <2 x i1> %m, i32 %evl)
44  ret <2 x i8> %v
45}
46
47define <2 x i8> @vrsub_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {
48; CHECK-LABEL: vrsub_vi_v2i8_unmasked:
49; CHECK:       # %bb.0:
50; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu
51; CHECK-NEXT:    vrsub.vi v8, v8, 2
52; CHECK-NEXT:    ret
53  %elt.head = insertelement <2 x i8> undef, i8 2, i32 0
54  %vb = shufflevector <2 x i8> %elt.head, <2 x i8> undef, <2 x i32> zeroinitializer
55  %head = insertelement <2 x i1> undef, i1 true, i32 0
56  %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer
57  %v = call <2 x i8> @llvm.vp.sub.v2i8(<2 x i8> %vb, <2 x i8> %va, <2 x i1> %m, i32 %evl)
58  ret <2 x i8> %v
59}
60
61declare <4 x i8> @llvm.vp.sub.v4i8(<4 x i8>, <4 x i8>, <4 x i1>, i32)
62
63define <4 x i8> @vrsub_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {
64; CHECK-LABEL: vrsub_vx_v4i8:
65; CHECK:       # %bb.0:
66; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, mu
67; CHECK-NEXT:    vrsub.vx v8, v8, a0, v0.t
68; CHECK-NEXT:    ret
69  %elt.head = insertelement <4 x i8> undef, i8 %b, i32 0
70  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> undef, <4 x i32> zeroinitializer
71  %v = call <4 x i8> @llvm.vp.sub.v4i8(<4 x i8> %vb, <4 x i8> %va, <4 x i1> %m, i32 %evl)
72  ret <4 x i8> %v
73}
74
75define <4 x i8> @vrsub_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) {
76; CHECK-LABEL: vrsub_vx_v4i8_unmasked:
77; CHECK:       # %bb.0:
78; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, mu
79; CHECK-NEXT:    vrsub.vx v8, v8, a0
80; CHECK-NEXT:    ret
81  %elt.head = insertelement <4 x i8> undef, i8 %b, i32 0
82  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> undef, <4 x i32> zeroinitializer
83  %head = insertelement <4 x i1> undef, i1 true, i32 0
84  %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer
85  %v = call <4 x i8> @llvm.vp.sub.v4i8(<4 x i8> %vb, <4 x i8> %va, <4 x i1> %m, i32 %evl)
86  ret <4 x i8> %v
87}
88
89define <4 x i8> @vrsub_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
90; CHECK-LABEL: vrsub_vi_v4i8:
91; CHECK:       # %bb.0:
92; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, mu
93; CHECK-NEXT:    vrsub.vi v8, v8, 2, v0.t
94; CHECK-NEXT:    ret
95  %elt.head = insertelement <4 x i8> undef, i8 2, i32 0
96  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> undef, <4 x i32> zeroinitializer
97  %v = call <4 x i8> @llvm.vp.sub.v4i8(<4 x i8> %vb, <4 x i8> %va, <4 x i1> %m, i32 %evl)
98  ret <4 x i8> %v
99}
100
101define <4 x i8> @vrsub_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
102; CHECK-LABEL: vrsub_vi_v4i8_unmasked:
103; CHECK:       # %bb.0:
104; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, mu
105; CHECK-NEXT:    vrsub.vi v8, v8, 2
106; CHECK-NEXT:    ret
107  %elt.head = insertelement <4 x i8> undef, i8 2, i32 0
108  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> undef, <4 x i32> zeroinitializer
109  %head = insertelement <4 x i1> undef, i1 true, i32 0
110  %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer
111  %v = call <4 x i8> @llvm.vp.sub.v4i8(<4 x i8> %vb, <4 x i8> %va, <4 x i1> %m, i32 %evl)
112  ret <4 x i8> %v
113}
114
115declare <8 x i8> @llvm.vp.sub.v8i8(<8 x i8>, <8 x i8>, <8 x i1>, i32)
116
117define <8 x i8> @vrsub_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %evl) {
118; CHECK-LABEL: vrsub_vx_v8i8:
119; CHECK:       # %bb.0:
120; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, mu
121; CHECK-NEXT:    vrsub.vx v8, v8, a0, v0.t
122; CHECK-NEXT:    ret
123  %elt.head = insertelement <8 x i8> undef, i8 %b, i32 0
124  %vb = shufflevector <8 x i8> %elt.head, <8 x i8> undef, <8 x i32> zeroinitializer
125  %v = call <8 x i8> @llvm.vp.sub.v8i8(<8 x i8> %vb, <8 x i8> %va, <8 x i1> %m, i32 %evl)
126  ret <8 x i8> %v
127}
128
129define <8 x i8> @vrsub_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) {
130; CHECK-LABEL: vrsub_vx_v8i8_unmasked:
131; CHECK:       # %bb.0:
132; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, mu
133; CHECK-NEXT:    vrsub.vx v8, v8, a0
134; CHECK-NEXT:    ret
135  %elt.head = insertelement <8 x i8> undef, i8 %b, i32 0
136  %vb = shufflevector <8 x i8> %elt.head, <8 x i8> undef, <8 x i32> zeroinitializer
137  %head = insertelement <8 x i1> undef, i1 true, i32 0
138  %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer
139  %v = call <8 x i8> @llvm.vp.sub.v8i8(<8 x i8> %vb, <8 x i8> %va, <8 x i1> %m, i32 %evl)
140  ret <8 x i8> %v
141}
142
143define <8 x i8> @vrsub_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
144; CHECK-LABEL: vrsub_vi_v8i8:
145; CHECK:       # %bb.0:
146; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, mu
147; CHECK-NEXT:    vrsub.vi v8, v8, 2, v0.t
148; CHECK-NEXT:    ret
149  %elt.head = insertelement <8 x i8> undef, i8 2, i32 0
150  %vb = shufflevector <8 x i8> %elt.head, <8 x i8> undef, <8 x i32> zeroinitializer
151  %v = call <8 x i8> @llvm.vp.sub.v8i8(<8 x i8> %vb, <8 x i8> %va, <8 x i1> %m, i32 %evl)
152  ret <8 x i8> %v
153}
154
155define <8 x i8> @vrsub_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {
156; CHECK-LABEL: vrsub_vi_v8i8_unmasked:
157; CHECK:       # %bb.0:
158; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, mu
159; CHECK-NEXT:    vrsub.vi v8, v8, 2
160; CHECK-NEXT:    ret
161  %elt.head = insertelement <8 x i8> undef, i8 2, i32 0
162  %vb = shufflevector <8 x i8> %elt.head, <8 x i8> undef, <8 x i32> zeroinitializer
163  %head = insertelement <8 x i1> undef, i1 true, i32 0
164  %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer
165  %v = call <8 x i8> @llvm.vp.sub.v8i8(<8 x i8> %vb, <8 x i8> %va, <8 x i1> %m, i32 %evl)
166  ret <8 x i8> %v
167}
168
169declare <16 x i8> @llvm.vp.sub.v16i8(<16 x i8>, <16 x i8>, <16 x i1>, i32)
170
171define <16 x i8> @vrsub_vx_v16i8(<16 x i8> %va, i8 %b, <16 x i1> %m, i32 zeroext %evl) {
172; CHECK-LABEL: vrsub_vx_v16i8:
173; CHECK:       # %bb.0:
174; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, mu
175; CHECK-NEXT:    vrsub.vx v8, v8, a0, v0.t
176; CHECK-NEXT:    ret
177  %elt.head = insertelement <16 x i8> undef, i8 %b, i32 0
178  %vb = shufflevector <16 x i8> %elt.head, <16 x i8> undef, <16 x i32> zeroinitializer
179  %v = call <16 x i8> @llvm.vp.sub.v16i8(<16 x i8> %vb, <16 x i8> %va, <16 x i1> %m, i32 %evl)
180  ret <16 x i8> %v
181}
182
183define <16 x i8> @vrsub_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) {
184; CHECK-LABEL: vrsub_vx_v16i8_unmasked:
185; CHECK:       # %bb.0:
186; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, mu
187; CHECK-NEXT:    vrsub.vx v8, v8, a0
188; CHECK-NEXT:    ret
189  %elt.head = insertelement <16 x i8> undef, i8 %b, i32 0
190  %vb = shufflevector <16 x i8> %elt.head, <16 x i8> undef, <16 x i32> zeroinitializer
191  %head = insertelement <16 x i1> undef, i1 true, i32 0
192  %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer
193  %v = call <16 x i8> @llvm.vp.sub.v16i8(<16 x i8> %vb, <16 x i8> %va, <16 x i1> %m, i32 %evl)
194  ret <16 x i8> %v
195}
196
197define <16 x i8> @vrsub_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {
198; CHECK-LABEL: vrsub_vi_v16i8:
199; CHECK:       # %bb.0:
200; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, mu
201; CHECK-NEXT:    vrsub.vi v8, v8, 2, v0.t
202; CHECK-NEXT:    ret
203  %elt.head = insertelement <16 x i8> undef, i8 2, i32 0
204  %vb = shufflevector <16 x i8> %elt.head, <16 x i8> undef, <16 x i32> zeroinitializer
205  %v = call <16 x i8> @llvm.vp.sub.v16i8(<16 x i8> %vb, <16 x i8> %va, <16 x i1> %m, i32 %evl)
206  ret <16 x i8> %v
207}
208
209define <16 x i8> @vrsub_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {
210; CHECK-LABEL: vrsub_vi_v16i8_unmasked:
211; CHECK:       # %bb.0:
212; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, mu
213; CHECK-NEXT:    vrsub.vi v8, v8, 2
214; CHECK-NEXT:    ret
215  %elt.head = insertelement <16 x i8> undef, i8 2, i32 0
216  %vb = shufflevector <16 x i8> %elt.head, <16 x i8> undef, <16 x i32> zeroinitializer
217  %head = insertelement <16 x i1> undef, i1 true, i32 0
218  %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer
219  %v = call <16 x i8> @llvm.vp.sub.v16i8(<16 x i8> %vb, <16 x i8> %va, <16 x i1> %m, i32 %evl)
220  ret <16 x i8> %v
221}
222
223declare <2 x i16> @llvm.vp.sub.v2i16(<2 x i16>, <2 x i16>, <2 x i1>, i32)
224
225define <2 x i16> @vrsub_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext %evl) {
226; CHECK-LABEL: vrsub_vx_v2i16:
227; CHECK:       # %bb.0:
228; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu
229; CHECK-NEXT:    vrsub.vx v8, v8, a0, v0.t
230; CHECK-NEXT:    ret
231  %elt.head = insertelement <2 x i16> undef, i16 %b, i32 0
232  %vb = shufflevector <2 x i16> %elt.head, <2 x i16> undef, <2 x i32> zeroinitializer
233  %v = call <2 x i16> @llvm.vp.sub.v2i16(<2 x i16> %vb, <2 x i16> %va, <2 x i1> %m, i32 %evl)
234  ret <2 x i16> %v
235}
236
237define <2 x i16> @vrsub_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl) {
238; CHECK-LABEL: vrsub_vx_v2i16_unmasked:
239; CHECK:       # %bb.0:
240; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu
241; CHECK-NEXT:    vrsub.vx v8, v8, a0
242; CHECK-NEXT:    ret
243  %elt.head = insertelement <2 x i16> undef, i16 %b, i32 0
244  %vb = shufflevector <2 x i16> %elt.head, <2 x i16> undef, <2 x i32> zeroinitializer
245  %head = insertelement <2 x i1> undef, i1 true, i32 0
246  %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer
247  %v = call <2 x i16> @llvm.vp.sub.v2i16(<2 x i16> %vb, <2 x i16> %va, <2 x i1> %m, i32 %evl)
248  ret <2 x i16> %v
249}
250
251define <2 x i16> @vrsub_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {
252; CHECK-LABEL: vrsub_vi_v2i16:
253; CHECK:       # %bb.0:
254; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, mu
255; CHECK-NEXT:    vrsub.vi v8, v8, 2, v0.t
256; CHECK-NEXT:    ret
257  %elt.head = insertelement <2 x i16> undef, i16 2, i32 0
258  %vb = shufflevector <2 x i16> %elt.head, <2 x i16> undef, <2 x i32> zeroinitializer
259  %v = call <2 x i16> @llvm.vp.sub.v2i16(<2 x i16> %vb, <2 x i16> %va, <2 x i1> %m, i32 %evl)
260  ret <2 x i16> %v
261}
262
263define <2 x i16> @vrsub_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {
264; CHECK-LABEL: vrsub_vi_v2i16_unmasked:
265; CHECK:       # %bb.0:
266; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, mu
267; CHECK-NEXT:    vrsub.vi v8, v8, 2
268; CHECK-NEXT:    ret
269  %elt.head = insertelement <2 x i16> undef, i16 2, i32 0
270  %vb = shufflevector <2 x i16> %elt.head, <2 x i16> undef, <2 x i32> zeroinitializer
271  %head = insertelement <2 x i1> undef, i1 true, i32 0
272  %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer
273  %v = call <2 x i16> @llvm.vp.sub.v2i16(<2 x i16> %vb, <2 x i16> %va, <2 x i1> %m, i32 %evl)
274  ret <2 x i16> %v
275}
276
277declare <4 x i16> @llvm.vp.sub.v4i16(<4 x i16>, <4 x i16>, <4 x i1>, i32)
278
279define <4 x i16> @vrsub_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext %evl) {
280; CHECK-LABEL: vrsub_vx_v4i16:
281; CHECK:       # %bb.0:
282; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu
283; CHECK-NEXT:    vrsub.vx v8, v8, a0, v0.t
284; CHECK-NEXT:    ret
285  %elt.head = insertelement <4 x i16> undef, i16 %b, i32 0
286  %vb = shufflevector <4 x i16> %elt.head, <4 x i16> undef, <4 x i32> zeroinitializer
287  %v = call <4 x i16> @llvm.vp.sub.v4i16(<4 x i16> %vb, <4 x i16> %va, <4 x i1> %m, i32 %evl)
288  ret <4 x i16> %v
289}
290
291define <4 x i16> @vrsub_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl) {
292; CHECK-LABEL: vrsub_vx_v4i16_unmasked:
293; CHECK:       # %bb.0:
294; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu
295; CHECK-NEXT:    vrsub.vx v8, v8, a0
296; CHECK-NEXT:    ret
297  %elt.head = insertelement <4 x i16> undef, i16 %b, i32 0
298  %vb = shufflevector <4 x i16> %elt.head, <4 x i16> undef, <4 x i32> zeroinitializer
299  %head = insertelement <4 x i1> undef, i1 true, i32 0
300  %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer
301  %v = call <4 x i16> @llvm.vp.sub.v4i16(<4 x i16> %vb, <4 x i16> %va, <4 x i1> %m, i32 %evl)
302  ret <4 x i16> %v
303}
304
305define <4 x i16> @vrsub_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
306; CHECK-LABEL: vrsub_vi_v4i16:
307; CHECK:       # %bb.0:
308; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu
309; CHECK-NEXT:    vrsub.vi v8, v8, 2, v0.t
310; CHECK-NEXT:    ret
311  %elt.head = insertelement <4 x i16> undef, i16 2, i32 0
312  %vb = shufflevector <4 x i16> %elt.head, <4 x i16> undef, <4 x i32> zeroinitializer
313  %v = call <4 x i16> @llvm.vp.sub.v4i16(<4 x i16> %vb, <4 x i16> %va, <4 x i1> %m, i32 %evl)
314  ret <4 x i16> %v
315}
316
317define <4 x i16> @vrsub_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
318; CHECK-LABEL: vrsub_vi_v4i16_unmasked:
319; CHECK:       # %bb.0:
320; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu
321; CHECK-NEXT:    vrsub.vi v8, v8, 2
322; CHECK-NEXT:    ret
323  %elt.head = insertelement <4 x i16> undef, i16 2, i32 0
324  %vb = shufflevector <4 x i16> %elt.head, <4 x i16> undef, <4 x i32> zeroinitializer
325  %head = insertelement <4 x i1> undef, i1 true, i32 0
326  %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer
327  %v = call <4 x i16> @llvm.vp.sub.v4i16(<4 x i16> %vb, <4 x i16> %va, <4 x i1> %m, i32 %evl)
328  ret <4 x i16> %v
329}
330
331declare <8 x i16> @llvm.vp.sub.v8i16(<8 x i16>, <8 x i16>, <8 x i1>, i32)
332
333define <8 x i16> @vrsub_vx_v8i16(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroext %evl) {
334; CHECK-LABEL: vrsub_vx_v8i16:
335; CHECK:       # %bb.0:
336; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu
337; CHECK-NEXT:    vrsub.vx v8, v8, a0, v0.t
338; CHECK-NEXT:    ret
339  %elt.head = insertelement <8 x i16> undef, i16 %b, i32 0
340  %vb = shufflevector <8 x i16> %elt.head, <8 x i16> undef, <8 x i32> zeroinitializer
341  %v = call <8 x i16> @llvm.vp.sub.v8i16(<8 x i16> %vb, <8 x i16> %va, <8 x i1> %m, i32 %evl)
342  ret <8 x i16> %v
343}
344
345define <8 x i16> @vrsub_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl) {
346; CHECK-LABEL: vrsub_vx_v8i16_unmasked:
347; CHECK:       # %bb.0:
348; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu
349; CHECK-NEXT:    vrsub.vx v8, v8, a0
350; CHECK-NEXT:    ret
351  %elt.head = insertelement <8 x i16> undef, i16 %b, i32 0
352  %vb = shufflevector <8 x i16> %elt.head, <8 x i16> undef, <8 x i32> zeroinitializer
353  %head = insertelement <8 x i1> undef, i1 true, i32 0
354  %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer
355  %v = call <8 x i16> @llvm.vp.sub.v8i16(<8 x i16> %vb, <8 x i16> %va, <8 x i1> %m, i32 %evl)
356  ret <8 x i16> %v
357}
358
359define <8 x i16> @vrsub_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {
360; CHECK-LABEL: vrsub_vi_v8i16:
361; CHECK:       # %bb.0:
362; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu
363; CHECK-NEXT:    vrsub.vi v8, v8, 2, v0.t
364; CHECK-NEXT:    ret
365  %elt.head = insertelement <8 x i16> undef, i16 2, i32 0
366  %vb = shufflevector <8 x i16> %elt.head, <8 x i16> undef, <8 x i32> zeroinitializer
367  %v = call <8 x i16> @llvm.vp.sub.v8i16(<8 x i16> %vb, <8 x i16> %va, <8 x i1> %m, i32 %evl)
368  ret <8 x i16> %v
369}
370
371define <8 x i16> @vrsub_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {
372; CHECK-LABEL: vrsub_vi_v8i16_unmasked:
373; CHECK:       # %bb.0:
374; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu
375; CHECK-NEXT:    vrsub.vi v8, v8, 2
376; CHECK-NEXT:    ret
377  %elt.head = insertelement <8 x i16> undef, i16 2, i32 0
378  %vb = shufflevector <8 x i16> %elt.head, <8 x i16> undef, <8 x i32> zeroinitializer
379  %head = insertelement <8 x i1> undef, i1 true, i32 0
380  %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer
381  %v = call <8 x i16> @llvm.vp.sub.v8i16(<8 x i16> %vb, <8 x i16> %va, <8 x i1> %m, i32 %evl)
382  ret <8 x i16> %v
383}
384
385declare <16 x i16> @llvm.vp.sub.v16i16(<16 x i16>, <16 x i16>, <16 x i1>, i32)
386
387define <16 x i16> @vrsub_vx_v16i16(<16 x i16> %va, i16 %b, <16 x i1> %m, i32 zeroext %evl) {
388; CHECK-LABEL: vrsub_vx_v16i16:
389; CHECK:       # %bb.0:
390; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu
391; CHECK-NEXT:    vrsub.vx v8, v8, a0, v0.t
392; CHECK-NEXT:    ret
393  %elt.head = insertelement <16 x i16> undef, i16 %b, i32 0
394  %vb = shufflevector <16 x i16> %elt.head, <16 x i16> undef, <16 x i32> zeroinitializer
395  %v = call <16 x i16> @llvm.vp.sub.v16i16(<16 x i16> %vb, <16 x i16> %va, <16 x i1> %m, i32 %evl)
396  ret <16 x i16> %v
397}
398
399define <16 x i16> @vrsub_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext %evl) {
400; CHECK-LABEL: vrsub_vx_v16i16_unmasked:
401; CHECK:       # %bb.0:
402; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu
403; CHECK-NEXT:    vrsub.vx v8, v8, a0
404; CHECK-NEXT:    ret
405  %elt.head = insertelement <16 x i16> undef, i16 %b, i32 0
406  %vb = shufflevector <16 x i16> %elt.head, <16 x i16> undef, <16 x i32> zeroinitializer
407  %head = insertelement <16 x i1> undef, i1 true, i32 0
408  %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer
409  %v = call <16 x i16> @llvm.vp.sub.v16i16(<16 x i16> %vb, <16 x i16> %va, <16 x i1> %m, i32 %evl)
410  ret <16 x i16> %v
411}
412
413define <16 x i16> @vrsub_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {
414; CHECK-LABEL: vrsub_vi_v16i16:
415; CHECK:       # %bb.0:
416; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, mu
417; CHECK-NEXT:    vrsub.vi v8, v8, 2, v0.t
418; CHECK-NEXT:    ret
419  %elt.head = insertelement <16 x i16> undef, i16 2, i32 0
420  %vb = shufflevector <16 x i16> %elt.head, <16 x i16> undef, <16 x i32> zeroinitializer
421  %v = call <16 x i16> @llvm.vp.sub.v16i16(<16 x i16> %vb, <16 x i16> %va, <16 x i1> %m, i32 %evl)
422  ret <16 x i16> %v
423}
424
425define <16 x i16> @vrsub_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
426; CHECK-LABEL: vrsub_vi_v16i16_unmasked:
427; CHECK:       # %bb.0:
428; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, mu
429; CHECK-NEXT:    vrsub.vi v8, v8, 2
430; CHECK-NEXT:    ret
431  %elt.head = insertelement <16 x i16> undef, i16 2, i32 0
432  %vb = shufflevector <16 x i16> %elt.head, <16 x i16> undef, <16 x i32> zeroinitializer
433  %head = insertelement <16 x i1> undef, i1 true, i32 0
434  %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer
435  %v = call <16 x i16> @llvm.vp.sub.v16i16(<16 x i16> %vb, <16 x i16> %va, <16 x i1> %m, i32 %evl)
436  ret <16 x i16> %v
437}
438
439declare <2 x i32> @llvm.vp.sub.v2i32(<2 x i32>, <2 x i32>, <2 x i1>, i32)
440
441define <2 x i32> @vrsub_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext %evl) {
442; CHECK-LABEL: vrsub_vx_v2i32:
443; CHECK:       # %bb.0:
444; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu
445; CHECK-NEXT:    vrsub.vx v8, v8, a0, v0.t
446; CHECK-NEXT:    ret
447  %elt.head = insertelement <2 x i32> undef, i32 %b, i32 0
448  %vb = shufflevector <2 x i32> %elt.head, <2 x i32> undef, <2 x i32> zeroinitializer
449  %v = call <2 x i32> @llvm.vp.sub.v2i32(<2 x i32> %vb, <2 x i32> %va, <2 x i1> %m, i32 %evl)
450  ret <2 x i32> %v
451}
452
453define <2 x i32> @vrsub_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl) {
454; CHECK-LABEL: vrsub_vx_v2i32_unmasked:
455; CHECK:       # %bb.0:
456; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu
457; CHECK-NEXT:    vrsub.vx v8, v8, a0
458; CHECK-NEXT:    ret
459  %elt.head = insertelement <2 x i32> undef, i32 %b, i32 0
460  %vb = shufflevector <2 x i32> %elt.head, <2 x i32> undef, <2 x i32> zeroinitializer
461  %head = insertelement <2 x i1> undef, i1 true, i32 0
462  %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer
463  %v = call <2 x i32> @llvm.vp.sub.v2i32(<2 x i32> %vb, <2 x i32> %va, <2 x i1> %m, i32 %evl)
464  ret <2 x i32> %v
465}
466
467define <2 x i32> @vrsub_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {
468; CHECK-LABEL: vrsub_vi_v2i32:
469; CHECK:       # %bb.0:
470; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, mu
471; CHECK-NEXT:    vrsub.vi v8, v8, 2, v0.t
472; CHECK-NEXT:    ret
473  %elt.head = insertelement <2 x i32> undef, i32 2, i32 0
474  %vb = shufflevector <2 x i32> %elt.head, <2 x i32> undef, <2 x i32> zeroinitializer
475  %v = call <2 x i32> @llvm.vp.sub.v2i32(<2 x i32> %vb, <2 x i32> %va, <2 x i1> %m, i32 %evl)
476  ret <2 x i32> %v
477}
478
479define <2 x i32> @vrsub_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {
480; CHECK-LABEL: vrsub_vi_v2i32_unmasked:
481; CHECK:       # %bb.0:
482; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, mu
483; CHECK-NEXT:    vrsub.vi v8, v8, 2
484; CHECK-NEXT:    ret
485  %elt.head = insertelement <2 x i32> undef, i32 2, i32 0
486  %vb = shufflevector <2 x i32> %elt.head, <2 x i32> undef, <2 x i32> zeroinitializer
487  %head = insertelement <2 x i1> undef, i1 true, i32 0
488  %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer
489  %v = call <2 x i32> @llvm.vp.sub.v2i32(<2 x i32> %vb, <2 x i32> %va, <2 x i1> %m, i32 %evl)
490  ret <2 x i32> %v
491}
492
493declare <4 x i32> @llvm.vp.sub.v4i32(<4 x i32>, <4 x i32>, <4 x i1>, i32)
494
495define <4 x i32> @vrsub_vx_v4i32(<4 x i32> %va, i32 %b, <4 x i1> %m, i32 zeroext %evl) {
496; CHECK-LABEL: vrsub_vx_v4i32:
497; CHECK:       # %bb.0:
498; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu
499; CHECK-NEXT:    vrsub.vx v8, v8, a0, v0.t
500; CHECK-NEXT:    ret
501  %elt.head = insertelement <4 x i32> undef, i32 %b, i32 0
502  %vb = shufflevector <4 x i32> %elt.head, <4 x i32> undef, <4 x i32> zeroinitializer
503  %v = call <4 x i32> @llvm.vp.sub.v4i32(<4 x i32> %vb, <4 x i32> %va, <4 x i1> %m, i32 %evl)
504  ret <4 x i32> %v
505}
506
507define <4 x i32> @vrsub_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl) {
508; CHECK-LABEL: vrsub_vx_v4i32_unmasked:
509; CHECK:       # %bb.0:
510; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu
511; CHECK-NEXT:    vrsub.vx v8, v8, a0
512; CHECK-NEXT:    ret
513  %elt.head = insertelement <4 x i32> undef, i32 %b, i32 0
514  %vb = shufflevector <4 x i32> %elt.head, <4 x i32> undef, <4 x i32> zeroinitializer
515  %head = insertelement <4 x i1> undef, i1 true, i32 0
516  %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer
517  %v = call <4 x i32> @llvm.vp.sub.v4i32(<4 x i32> %vb, <4 x i32> %va, <4 x i1> %m, i32 %evl)
518  ret <4 x i32> %v
519}
520
521define <4 x i32> @vrsub_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
522; CHECK-LABEL: vrsub_vi_v4i32:
523; CHECK:       # %bb.0:
524; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, mu
525; CHECK-NEXT:    vrsub.vi v8, v8, 2, v0.t
526; CHECK-NEXT:    ret
527  %elt.head = insertelement <4 x i32> undef, i32 2, i32 0
528  %vb = shufflevector <4 x i32> %elt.head, <4 x i32> undef, <4 x i32> zeroinitializer
529  %v = call <4 x i32> @llvm.vp.sub.v4i32(<4 x i32> %vb, <4 x i32> %va, <4 x i1> %m, i32 %evl)
530  ret <4 x i32> %v
531}
532
533define <4 x i32> @vrsub_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
534; CHECK-LABEL: vrsub_vi_v4i32_unmasked:
535; CHECK:       # %bb.0:
536; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, mu
537; CHECK-NEXT:    vrsub.vi v8, v8, 2
538; CHECK-NEXT:    ret
539  %elt.head = insertelement <4 x i32> undef, i32 2, i32 0
540  %vb = shufflevector <4 x i32> %elt.head, <4 x i32> undef, <4 x i32> zeroinitializer
541  %head = insertelement <4 x i1> undef, i1 true, i32 0
542  %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer
543  %v = call <4 x i32> @llvm.vp.sub.v4i32(<4 x i32> %vb, <4 x i32> %va, <4 x i1> %m, i32 %evl)
544  ret <4 x i32> %v
545}
546
547declare <8 x i32> @llvm.vp.sub.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
548
549define <8 x i32> @vrsub_vx_v8i32(<8 x i32> %va, i32 %b, <8 x i1> %m, i32 zeroext %evl) {
550; CHECK-LABEL: vrsub_vx_v8i32:
551; CHECK:       # %bb.0:
552; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, mu
553; CHECK-NEXT:    vrsub.vx v8, v8, a0, v0.t
554; CHECK-NEXT:    ret
555  %elt.head = insertelement <8 x i32> undef, i32 %b, i32 0
556  %vb = shufflevector <8 x i32> %elt.head, <8 x i32> undef, <8 x i32> zeroinitializer
557  %v = call <8 x i32> @llvm.vp.sub.v8i32(<8 x i32> %vb, <8 x i32> %va, <8 x i1> %m, i32 %evl)
558  ret <8 x i32> %v
559}
560
561define <8 x i32> @vrsub_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl) {
562; CHECK-LABEL: vrsub_vx_v8i32_unmasked:
563; CHECK:       # %bb.0:
564; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, mu
565; CHECK-NEXT:    vrsub.vx v8, v8, a0
566; CHECK-NEXT:    ret
567  %elt.head = insertelement <8 x i32> undef, i32 %b, i32 0
568  %vb = shufflevector <8 x i32> %elt.head, <8 x i32> undef, <8 x i32> zeroinitializer
569  %head = insertelement <8 x i1> undef, i1 true, i32 0
570  %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer
571  %v = call <8 x i32> @llvm.vp.sub.v8i32(<8 x i32> %vb, <8 x i32> %va, <8 x i1> %m, i32 %evl)
572  ret <8 x i32> %v
573}
574
575define <8 x i32> @vrsub_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
576; CHECK-LABEL: vrsub_vi_v8i32:
577; CHECK:       # %bb.0:
578; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, mu
579; CHECK-NEXT:    vrsub.vi v8, v8, 2, v0.t
580; CHECK-NEXT:    ret
581  %elt.head = insertelement <8 x i32> undef, i32 2, i32 0
582  %vb = shufflevector <8 x i32> %elt.head, <8 x i32> undef, <8 x i32> zeroinitializer
583  %v = call <8 x i32> @llvm.vp.sub.v8i32(<8 x i32> %vb, <8 x i32> %va, <8 x i1> %m, i32 %evl)
584  ret <8 x i32> %v
585}
586
587define <8 x i32> @vrsub_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
588; CHECK-LABEL: vrsub_vi_v8i32_unmasked:
589; CHECK:       # %bb.0:
590; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, mu
591; CHECK-NEXT:    vrsub.vi v8, v8, 2
592; CHECK-NEXT:    ret
593  %elt.head = insertelement <8 x i32> undef, i32 2, i32 0
594  %vb = shufflevector <8 x i32> %elt.head, <8 x i32> undef, <8 x i32> zeroinitializer
595  %head = insertelement <8 x i1> undef, i1 true, i32 0
596  %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer
597  %v = call <8 x i32> @llvm.vp.sub.v8i32(<8 x i32> %vb, <8 x i32> %va, <8 x i1> %m, i32 %evl)
598  ret <8 x i32> %v
599}
600
601declare <16 x i32> @llvm.vp.sub.v16i32(<16 x i32>, <16 x i32>, <16 x i1>, i32)
602
603define <16 x i32> @vrsub_vx_v16i32(<16 x i32> %va, i32 %b, <16 x i1> %m, i32 zeroext %evl) {
604; CHECK-LABEL: vrsub_vx_v16i32:
605; CHECK:       # %bb.0:
606; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, mu
607; CHECK-NEXT:    vrsub.vx v8, v8, a0, v0.t
608; CHECK-NEXT:    ret
609  %elt.head = insertelement <16 x i32> undef, i32 %b, i32 0
610  %vb = shufflevector <16 x i32> %elt.head, <16 x i32> undef, <16 x i32> zeroinitializer
611  %v = call <16 x i32> @llvm.vp.sub.v16i32(<16 x i32> %vb, <16 x i32> %va, <16 x i1> %m, i32 %evl)
612  ret <16 x i32> %v
613}
614
615define <16 x i32> @vrsub_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext %evl) {
616; CHECK-LABEL: vrsub_vx_v16i32_unmasked:
617; CHECK:       # %bb.0:
618; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, mu
619; CHECK-NEXT:    vrsub.vx v8, v8, a0
620; CHECK-NEXT:    ret
621  %elt.head = insertelement <16 x i32> undef, i32 %b, i32 0
622  %vb = shufflevector <16 x i32> %elt.head, <16 x i32> undef, <16 x i32> zeroinitializer
623  %head = insertelement <16 x i1> undef, i1 true, i32 0
624  %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer
625  %v = call <16 x i32> @llvm.vp.sub.v16i32(<16 x i32> %vb, <16 x i32> %va, <16 x i1> %m, i32 %evl)
626  ret <16 x i32> %v
627}
628
629define <16 x i32> @vrsub_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {
630; CHECK-LABEL: vrsub_vi_v16i32:
631; CHECK:       # %bb.0:
632; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, mu
633; CHECK-NEXT:    vrsub.vi v8, v8, 2, v0.t
634; CHECK-NEXT:    ret
635  %elt.head = insertelement <16 x i32> undef, i32 2, i32 0
636  %vb = shufflevector <16 x i32> %elt.head, <16 x i32> undef, <16 x i32> zeroinitializer
637  %v = call <16 x i32> @llvm.vp.sub.v16i32(<16 x i32> %vb, <16 x i32> %va, <16 x i1> %m, i32 %evl)
638  ret <16 x i32> %v
639}
640
641define <16 x i32> @vrsub_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
642; CHECK-LABEL: vrsub_vi_v16i32_unmasked:
643; CHECK:       # %bb.0:
644; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, mu
645; CHECK-NEXT:    vrsub.vi v8, v8, 2
646; CHECK-NEXT:    ret
647  %elt.head = insertelement <16 x i32> undef, i32 2, i32 0
648  %vb = shufflevector <16 x i32> %elt.head, <16 x i32> undef, <16 x i32> zeroinitializer
649  %head = insertelement <16 x i1> undef, i1 true, i32 0
650  %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer
651  %v = call <16 x i32> @llvm.vp.sub.v16i32(<16 x i32> %vb, <16 x i32> %va, <16 x i1> %m, i32 %evl)
652  ret <16 x i32> %v
653}
654
655declare <2 x i64> @llvm.vp.sub.v2i64(<2 x i64>, <2 x i64>, <2 x i1>, i32)
656
657define <2 x i64> @vrsub_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {
658; RV32-LABEL: vrsub_vx_v2i64:
659; RV32:       # %bb.0:
660; RV32-NEXT:    addi sp, sp, -16
661; RV32-NEXT:    .cfi_def_cfa_offset 16
662; RV32-NEXT:    sw a1, 12(sp)
663; RV32-NEXT:    sw a0, 8(sp)
664; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
665; RV32-NEXT:    addi a0, sp, 8
666; RV32-NEXT:    vlse64.v v25, (a0), zero
667; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, mu
668; RV32-NEXT:    vsub.vv v8, v25, v8, v0.t
669; RV32-NEXT:    addi sp, sp, 16
670; RV32-NEXT:    ret
671;
672; RV64-LABEL: vrsub_vx_v2i64:
673; RV64:       # %bb.0:
674; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, mu
675; RV64-NEXT:    vrsub.vx v8, v8, a0, v0.t
676; RV64-NEXT:    ret
677  %elt.head = insertelement <2 x i64> undef, i64 %b, i32 0
678  %vb = shufflevector <2 x i64> %elt.head, <2 x i64> undef, <2 x i32> zeroinitializer
679  %v = call <2 x i64> @llvm.vp.sub.v2i64(<2 x i64> %vb, <2 x i64> %va, <2 x i1> %m, i32 %evl)
680  ret <2 x i64> %v
681}
682
683define <2 x i64> @vrsub_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {
684; RV32-LABEL: vrsub_vx_v2i64_unmasked:
685; RV32:       # %bb.0:
686; RV32-NEXT:    addi sp, sp, -16
687; RV32-NEXT:    .cfi_def_cfa_offset 16
688; RV32-NEXT:    sw a1, 12(sp)
689; RV32-NEXT:    sw a0, 8(sp)
690; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
691; RV32-NEXT:    addi a0, sp, 8
692; RV32-NEXT:    vlse64.v v25, (a0), zero
693; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, mu
694; RV32-NEXT:    vsub.vv v8, v25, v8
695; RV32-NEXT:    addi sp, sp, 16
696; RV32-NEXT:    ret
697;
698; RV64-LABEL: vrsub_vx_v2i64_unmasked:
699; RV64:       # %bb.0:
700; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, mu
701; RV64-NEXT:    vrsub.vx v8, v8, a0
702; RV64-NEXT:    ret
703  %elt.head = insertelement <2 x i64> undef, i64 %b, i32 0
704  %vb = shufflevector <2 x i64> %elt.head, <2 x i64> undef, <2 x i32> zeroinitializer
705  %head = insertelement <2 x i1> undef, i1 true, i32 0
706  %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer
707  %v = call <2 x i64> @llvm.vp.sub.v2i64(<2 x i64> %vb, <2 x i64> %va, <2 x i1> %m, i32 %evl)
708  ret <2 x i64> %v
709}
710
711define <2 x i64> @vrsub_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
712; CHECK-LABEL: vrsub_vi_v2i64:
713; CHECK:       # %bb.0:
714; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, mu
715; CHECK-NEXT:    vrsub.vi v8, v8, 2, v0.t
716; CHECK-NEXT:    ret
717  %elt.head = insertelement <2 x i64> undef, i64 2, i32 0
718  %vb = shufflevector <2 x i64> %elt.head, <2 x i64> undef, <2 x i32> zeroinitializer
719  %v = call <2 x i64> @llvm.vp.sub.v2i64(<2 x i64> %vb, <2 x i64> %va, <2 x i1> %m, i32 %evl)
720  ret <2 x i64> %v
721}
722
723define <2 x i64> @vrsub_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
724; CHECK-LABEL: vrsub_vi_v2i64_unmasked:
725; CHECK:       # %bb.0:
726; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, mu
727; CHECK-NEXT:    vrsub.vi v8, v8, 2
728; CHECK-NEXT:    ret
729  %elt.head = insertelement <2 x i64> undef, i64 2, i32 0
730  %vb = shufflevector <2 x i64> %elt.head, <2 x i64> undef, <2 x i32> zeroinitializer
731  %head = insertelement <2 x i1> undef, i1 true, i32 0
732  %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer
733  %v = call <2 x i64> @llvm.vp.sub.v2i64(<2 x i64> %vb, <2 x i64> %va, <2 x i1> %m, i32 %evl)
734  ret <2 x i64> %v
735}
736
737declare <4 x i64> @llvm.vp.sub.v4i64(<4 x i64>, <4 x i64>, <4 x i1>, i32)
738
739define <4 x i64> @vrsub_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {
740; RV32-LABEL: vrsub_vx_v4i64:
741; RV32:       # %bb.0:
742; RV32-NEXT:    addi sp, sp, -16
743; RV32-NEXT:    .cfi_def_cfa_offset 16
744; RV32-NEXT:    sw a1, 12(sp)
745; RV32-NEXT:    sw a0, 8(sp)
746; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
747; RV32-NEXT:    addi a0, sp, 8
748; RV32-NEXT:    vlse64.v v26, (a0), zero
749; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, mu
750; RV32-NEXT:    vsub.vv v8, v26, v8, v0.t
751; RV32-NEXT:    addi sp, sp, 16
752; RV32-NEXT:    ret
753;
754; RV64-LABEL: vrsub_vx_v4i64:
755; RV64:       # %bb.0:
756; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, mu
757; RV64-NEXT:    vrsub.vx v8, v8, a0, v0.t
758; RV64-NEXT:    ret
759  %elt.head = insertelement <4 x i64> undef, i64 %b, i32 0
760  %vb = shufflevector <4 x i64> %elt.head, <4 x i64> undef, <4 x i32> zeroinitializer
761  %v = call <4 x i64> @llvm.vp.sub.v4i64(<4 x i64> %vb, <4 x i64> %va, <4 x i1> %m, i32 %evl)
762  ret <4 x i64> %v
763}
764
765define <4 x i64> @vrsub_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {
766; RV32-LABEL: vrsub_vx_v4i64_unmasked:
767; RV32:       # %bb.0:
768; RV32-NEXT:    addi sp, sp, -16
769; RV32-NEXT:    .cfi_def_cfa_offset 16
770; RV32-NEXT:    sw a1, 12(sp)
771; RV32-NEXT:    sw a0, 8(sp)
772; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
773; RV32-NEXT:    addi a0, sp, 8
774; RV32-NEXT:    vlse64.v v26, (a0), zero
775; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, mu
776; RV32-NEXT:    vsub.vv v8, v26, v8
777; RV32-NEXT:    addi sp, sp, 16
778; RV32-NEXT:    ret
779;
780; RV64-LABEL: vrsub_vx_v4i64_unmasked:
781; RV64:       # %bb.0:
782; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, mu
783; RV64-NEXT:    vrsub.vx v8, v8, a0
784; RV64-NEXT:    ret
785  %elt.head = insertelement <4 x i64> undef, i64 %b, i32 0
786  %vb = shufflevector <4 x i64> %elt.head, <4 x i64> undef, <4 x i32> zeroinitializer
787  %head = insertelement <4 x i1> undef, i1 true, i32 0
788  %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer
789  %v = call <4 x i64> @llvm.vp.sub.v4i64(<4 x i64> %vb, <4 x i64> %va, <4 x i1> %m, i32 %evl)
790  ret <4 x i64> %v
791}
792
793define <4 x i64> @vrsub_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
794; CHECK-LABEL: vrsub_vi_v4i64:
795; CHECK:       # %bb.0:
796; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, mu
797; CHECK-NEXT:    vrsub.vi v8, v8, 2, v0.t
798; CHECK-NEXT:    ret
799  %elt.head = insertelement <4 x i64> undef, i64 2, i32 0
800  %vb = shufflevector <4 x i64> %elt.head, <4 x i64> undef, <4 x i32> zeroinitializer
801  %v = call <4 x i64> @llvm.vp.sub.v4i64(<4 x i64> %vb, <4 x i64> %va, <4 x i1> %m, i32 %evl)
802  ret <4 x i64> %v
803}
804
805define <4 x i64> @vrsub_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
806; CHECK-LABEL: vrsub_vi_v4i64_unmasked:
807; CHECK:       # %bb.0:
808; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, mu
809; CHECK-NEXT:    vrsub.vi v8, v8, 2
810; CHECK-NEXT:    ret
811  %elt.head = insertelement <4 x i64> undef, i64 2, i32 0
812  %vb = shufflevector <4 x i64> %elt.head, <4 x i64> undef, <4 x i32> zeroinitializer
813  %head = insertelement <4 x i1> undef, i1 true, i32 0
814  %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer
815  %v = call <4 x i64> @llvm.vp.sub.v4i64(<4 x i64> %vb, <4 x i64> %va, <4 x i1> %m, i32 %evl)
816  ret <4 x i64> %v
817}
818
819declare <8 x i64> @llvm.vp.sub.v8i64(<8 x i64>, <8 x i64>, <8 x i1>, i32)
820
821define <8 x i64> @vrsub_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
822; RV32-LABEL: vrsub_vx_v8i64:
823; RV32:       # %bb.0:
824; RV32-NEXT:    addi sp, sp, -16
825; RV32-NEXT:    .cfi_def_cfa_offset 16
826; RV32-NEXT:    sw a1, 12(sp)
827; RV32-NEXT:    sw a0, 8(sp)
828; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
829; RV32-NEXT:    addi a0, sp, 8
830; RV32-NEXT:    vlse64.v v28, (a0), zero
831; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, mu
832; RV32-NEXT:    vsub.vv v8, v28, v8, v0.t
833; RV32-NEXT:    addi sp, sp, 16
834; RV32-NEXT:    ret
835;
836; RV64-LABEL: vrsub_vx_v8i64:
837; RV64:       # %bb.0:
838; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, mu
839; RV64-NEXT:    vrsub.vx v8, v8, a0, v0.t
840; RV64-NEXT:    ret
841  %elt.head = insertelement <8 x i64> undef, i64 %b, i32 0
842  %vb = shufflevector <8 x i64> %elt.head, <8 x i64> undef, <8 x i32> zeroinitializer
843  %v = call <8 x i64> @llvm.vp.sub.v8i64(<8 x i64> %vb, <8 x i64> %va, <8 x i1> %m, i32 %evl)
844  ret <8 x i64> %v
845}
846
847define <8 x i64> @vrsub_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {
848; RV32-LABEL: vrsub_vx_v8i64_unmasked:
849; RV32:       # %bb.0:
850; RV32-NEXT:    addi sp, sp, -16
851; RV32-NEXT:    .cfi_def_cfa_offset 16
852; RV32-NEXT:    sw a1, 12(sp)
853; RV32-NEXT:    sw a0, 8(sp)
854; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
855; RV32-NEXT:    addi a0, sp, 8
856; RV32-NEXT:    vlse64.v v28, (a0), zero
857; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, mu
858; RV32-NEXT:    vsub.vv v8, v28, v8
859; RV32-NEXT:    addi sp, sp, 16
860; RV32-NEXT:    ret
861;
862; RV64-LABEL: vrsub_vx_v8i64_unmasked:
863; RV64:       # %bb.0:
864; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, mu
865; RV64-NEXT:    vrsub.vx v8, v8, a0
866; RV64-NEXT:    ret
867  %elt.head = insertelement <8 x i64> undef, i64 %b, i32 0
868  %vb = shufflevector <8 x i64> %elt.head, <8 x i64> undef, <8 x i32> zeroinitializer
869  %head = insertelement <8 x i1> undef, i1 true, i32 0
870  %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer
871  %v = call <8 x i64> @llvm.vp.sub.v8i64(<8 x i64> %vb, <8 x i64> %va, <8 x i1> %m, i32 %evl)
872  ret <8 x i64> %v
873}
874
875define <8 x i64> @vrsub_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
876; CHECK-LABEL: vrsub_vi_v8i64:
877; CHECK:       # %bb.0:
878; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, mu
879; CHECK-NEXT:    vrsub.vi v8, v8, 2, v0.t
880; CHECK-NEXT:    ret
881  %elt.head = insertelement <8 x i64> undef, i64 2, i32 0
882  %vb = shufflevector <8 x i64> %elt.head, <8 x i64> undef, <8 x i32> zeroinitializer
883  %v = call <8 x i64> @llvm.vp.sub.v8i64(<8 x i64> %vb, <8 x i64> %va, <8 x i1> %m, i32 %evl)
884  ret <8 x i64> %v
885}
886
887define <8 x i64> @vrsub_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
888; CHECK-LABEL: vrsub_vi_v8i64_unmasked:
889; CHECK:       # %bb.0:
890; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, mu
891; CHECK-NEXT:    vrsub.vi v8, v8, 2
892; CHECK-NEXT:    ret
893  %elt.head = insertelement <8 x i64> undef, i64 2, i32 0
894  %vb = shufflevector <8 x i64> %elt.head, <8 x i64> undef, <8 x i32> zeroinitializer
895  %head = insertelement <8 x i1> undef, i1 true, i32 0
896  %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer
897  %v = call <8 x i64> @llvm.vp.sub.v8i64(<8 x i64> %vb, <8 x i64> %va, <8 x i1> %m, i32 %evl)
898  ret <8 x i64> %v
899}
900
901declare <16 x i64> @llvm.vp.sub.v16i64(<16 x i64>, <16 x i64>, <16 x i1>, i32)
902
903define <16 x i64> @vrsub_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {
904; RV32-LABEL: vrsub_vx_v16i64:
905; RV32:       # %bb.0:
906; RV32-NEXT:    addi sp, sp, -16
907; RV32-NEXT:    .cfi_def_cfa_offset 16
908; RV32-NEXT:    sw a1, 12(sp)
909; RV32-NEXT:    sw a0, 8(sp)
910; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
911; RV32-NEXT:    addi a0, sp, 8
912; RV32-NEXT:    vlse64.v v16, (a0), zero
913; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
914; RV32-NEXT:    vsub.vv v8, v16, v8, v0.t
915; RV32-NEXT:    addi sp, sp, 16
916; RV32-NEXT:    ret
917;
918; RV64-LABEL: vrsub_vx_v16i64:
919; RV64:       # %bb.0:
920; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, mu
921; RV64-NEXT:    vrsub.vx v8, v8, a0, v0.t
922; RV64-NEXT:    ret
923  %elt.head = insertelement <16 x i64> undef, i64 %b, i32 0
924  %vb = shufflevector <16 x i64> %elt.head, <16 x i64> undef, <16 x i32> zeroinitializer
925  %v = call <16 x i64> @llvm.vp.sub.v16i64(<16 x i64> %vb, <16 x i64> %va, <16 x i1> %m, i32 %evl)
926  ret <16 x i64> %v
927}
928
929define <16 x i64> @vrsub_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {
930; RV32-LABEL: vrsub_vx_v16i64_unmasked:
931; RV32:       # %bb.0:
932; RV32-NEXT:    addi sp, sp, -16
933; RV32-NEXT:    .cfi_def_cfa_offset 16
934; RV32-NEXT:    sw a1, 12(sp)
935; RV32-NEXT:    sw a0, 8(sp)
936; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, mu
937; RV32-NEXT:    addi a0, sp, 8
938; RV32-NEXT:    vlse64.v v16, (a0), zero
939; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
940; RV32-NEXT:    vsub.vv v8, v16, v8
941; RV32-NEXT:    addi sp, sp, 16
942; RV32-NEXT:    ret
943;
944; RV64-LABEL: vrsub_vx_v16i64_unmasked:
945; RV64:       # %bb.0:
946; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, mu
947; RV64-NEXT:    vrsub.vx v8, v8, a0
948; RV64-NEXT:    ret
949  %elt.head = insertelement <16 x i64> undef, i64 %b, i32 0
950  %vb = shufflevector <16 x i64> %elt.head, <16 x i64> undef, <16 x i32> zeroinitializer
951  %head = insertelement <16 x i1> undef, i1 true, i32 0
952  %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer
953  %v = call <16 x i64> @llvm.vp.sub.v16i64(<16 x i64> %vb, <16 x i64> %va, <16 x i1> %m, i32 %evl)
954  ret <16 x i64> %v
955}
956
957define <16 x i64> @vrsub_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {
958; CHECK-LABEL: vrsub_vi_v16i64:
959; CHECK:       # %bb.0:
960; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, mu
961; CHECK-NEXT:    vrsub.vi v8, v8, 2, v0.t
962; CHECK-NEXT:    ret
963  %elt.head = insertelement <16 x i64> undef, i64 2, i32 0
964  %vb = shufflevector <16 x i64> %elt.head, <16 x i64> undef, <16 x i32> zeroinitializer
965  %v = call <16 x i64> @llvm.vp.sub.v16i64(<16 x i64> %vb, <16 x i64> %va, <16 x i1> %m, i32 %evl)
966  ret <16 x i64> %v
967}
968
969define <16 x i64> @vrsub_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
970; CHECK-LABEL: vrsub_vi_v16i64_unmasked:
971; CHECK:       # %bb.0:
972; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, mu
973; CHECK-NEXT:    vrsub.vi v8, v8, 2
974; CHECK-NEXT:    ret
975  %elt.head = insertelement <16 x i64> undef, i64 2, i32 0
976  %vb = shufflevector <16 x i64> %elt.head, <16 x i64> undef, <16 x i32> zeroinitializer
977  %head = insertelement <16 x i1> undef, i1 true, i32 0
978  %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer
979  %v = call <16 x i64> @llvm.vp.sub.v16i64(<16 x i64> %vb, <16 x i64> %va, <16 x i1> %m, i32 %evl)
980  ret <16 x i64> %v
981}
982