1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple riscv64 -mattr=+m,+experimental-v < %s \
3; RUN:    | FileCheck %s -check-prefix=RV64
4; RUN: llc -mtriple riscv32 -mattr=+m,+experimental-v < %s \
5; RUN:    | FileCheck %s -check-prefix=RV32
6
7
8define i64 @vscale_zero() nounwind {
9; RV64-LABEL: vscale_zero:
10; RV64:       # %bb.0: # %entry
11; RV64-NEXT:    mv a0, zero
12; RV64-NEXT:    ret
13;
14; RV32-LABEL: vscale_zero:
15; RV32:       # %bb.0: # %entry
16; RV32-NEXT:    mv a0, zero
17; RV32-NEXT:    mv a1, zero
18; RV32-NEXT:    ret
19entry:
20  %0 = call i64 @llvm.vscale.i64()
21  %1 = mul i64 %0, 0
22  ret i64 %1
23}
24
25define i64 @vscale_one() nounwind {
26; RV64-LABEL: vscale_one:
27; RV64:       # %bb.0: # %entry
28; RV64-NEXT:    csrr a0, vlenb
29; RV64-NEXT:    srli a0, a0, 3
30; RV64-NEXT:    ret
31;
32; RV32-LABEL: vscale_one:
33; RV32:       # %bb.0: # %entry
34; RV32-NEXT:    csrr a0, vlenb
35; RV32-NEXT:    srli a0, a0, 3
36; RV32-NEXT:    mv a1, zero
37; RV32-NEXT:    ret
38entry:
39  %0 = call i64 @llvm.vscale.i64()
40  %1 = mul i64 %0, 1
41  ret i64 %1
42}
43
44define i64 @vscale_uimmpow2xlen() nounwind {
45; RV64-LABEL: vscale_uimmpow2xlen:
46; RV64:       # %bb.0: # %entry
47; RV64-NEXT:    csrr a0, vlenb
48; RV64-NEXT:    slli a0, a0, 3
49; RV64-NEXT:    ret
50;
51; RV32-LABEL: vscale_uimmpow2xlen:
52; RV32:       # %bb.0: # %entry
53; RV32-NEXT:    csrr a0, vlenb
54; RV32-NEXT:    slli a0, a0, 3
55; RV32-NEXT:    mv a1, zero
56; RV32-NEXT:    ret
57entry:
58  %0 = call i64 @llvm.vscale.i64()
59  %1 = mul i64 %0, 64
60  ret i64 %1
61}
62
63define i64 @vscale_non_pow2() nounwind {
64; RV64-LABEL: vscale_non_pow2:
65; RV64:       # %bb.0: # %entry
66; RV64-NEXT:    csrr a0, vlenb
67; RV64-NEXT:    slli a1, a0, 1
68; RV64-NEXT:    add a0, a1, a0
69; RV64-NEXT:    ret
70;
71; RV32-LABEL: vscale_non_pow2:
72; RV32:       # %bb.0: # %entry
73; RV32-NEXT:    csrr a1, vlenb
74; RV32-NEXT:    slli a0, a1, 1
75; RV32-NEXT:    add a0, a0, a1
76; RV32-NEXT:    srli a1, a1, 3
77; RV32-NEXT:    addi a2, zero, 24
78; RV32-NEXT:    mulhu a1, a1, a2
79; RV32-NEXT:    ret
80entry:
81  %0 = call i64 @llvm.vscale.i64()
82  %1 = mul i64 %0, 24
83  ret i64 %1
84}
85
86declare i64 @llvm.vscale.i64()
87