1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32
3; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64
4
5; This test checks a regression in the select-to-sra transform, which was
6; asserting (without a precondition) when the vector constants implicitly
7; truncated their inputs, as we do on RV64.
8define <4 x i32> @vselect_of_consts(<4 x i1> %cc) {
9; RV32-LABEL: vselect_of_consts:
10; RV32:       # %bb.0:
11; RV32-NEXT:    lui a0, 284280
12; RV32-NEXT:    addi a0, a0, 291
13; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
14; RV32-NEXT:    vmv.v.x v25, a0
15; RV32-NEXT:    lui a0, 214376
16; RV32-NEXT:    addi a0, a0, -2030
17; RV32-NEXT:    vmerge.vxm v8, v25, a0, v0
18; RV32-NEXT:    ret
19;
20; RV64-LABEL: vselect_of_consts:
21; RV64:       # %bb.0:
22; RV64-NEXT:    lui a0, 284280
23; RV64-NEXT:    addiw a0, a0, 291
24; RV64-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
25; RV64-NEXT:    vmv.v.x v25, a0
26; RV64-NEXT:    lui a0, 214376
27; RV64-NEXT:    addiw a0, a0, -2030
28; RV64-NEXT:    vmerge.vxm v8, v25, a0, v0
29; RV64-NEXT:    ret
30  %v = select <4 x i1> %cc, <4 x i32> <i32 878082066, i32 878082066, i32 878082066, i32 878082066>, <4 x i32> <i32 1164411171, i32 1164411171, i32 1164411171, i32 1164411171>
31  ret <4 x i32> %v
32}
33