1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
3
4define <vscale x 1 x i8> @vadd_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
5; CHECK-LABEL: vadd_vx_nxv1i8:
6; CHECK:       # %bb.0:
7; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
8; CHECK-NEXT:    vadd.vx v8, v8, a0
9; CHECK-NEXT:    ret
10  %head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
11  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
12  %vc = add <vscale x 1 x i8> %va, %splat
13  ret <vscale x 1 x i8> %vc
14}
15
16define <vscale x 1 x i8> @vadd_vx_nxv1i8_0(<vscale x 1 x i8> %va) {
17; CHECK-LABEL: vadd_vx_nxv1i8_0:
18; CHECK:       # %bb.0:
19; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
20; CHECK-NEXT:    vadd.vi v8, v8, -1
21; CHECK-NEXT:    ret
22  %head = insertelement <vscale x 1 x i8> undef, i8 -1, i32 0
23  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
24  %vc = add <vscale x 1 x i8> %va, %splat
25  ret <vscale x 1 x i8> %vc
26}
27
28define <vscale x 1 x i8> @vadd_vx_nxv1i8_1(<vscale x 1 x i8> %va) {
29; CHECK-LABEL: vadd_vx_nxv1i8_1:
30; CHECK:       # %bb.0:
31; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
32; CHECK-NEXT:    vadd.vi v8, v8, 2
33; CHECK-NEXT:    ret
34  %head = insertelement <vscale x 1 x i8> undef, i8 2, i32 0
35  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
36  %vc = add <vscale x 1 x i8> %va, %splat
37  ret <vscale x 1 x i8> %vc
38}
39
40; Test constant adds to see if we can optimize them away for scalable vectors.
41define <vscale x 1 x i8> @vadd_ii_nxv1i8_1() {
42; CHECK-LABEL: vadd_ii_nxv1i8_1:
43; CHECK:       # %bb.0:
44; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
45; CHECK-NEXT:    vmv.v.i v8, 5
46; CHECK-NEXT:    ret
47  %heada = insertelement <vscale x 1 x i8> undef, i8 2, i32 0
48  %splata = shufflevector <vscale x 1 x i8> %heada, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
49  %headb = insertelement <vscale x 1 x i8> undef, i8 3, i32 0
50  %splatb = shufflevector <vscale x 1 x i8> %headb, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
51  %vc = add <vscale x 1 x i8> %splata, %splatb
52  ret <vscale x 1 x i8> %vc
53}
54
55define <vscale x 2 x i8> @vadd_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
56; CHECK-LABEL: vadd_vx_nxv2i8:
57; CHECK:       # %bb.0:
58; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
59; CHECK-NEXT:    vadd.vx v8, v8, a0
60; CHECK-NEXT:    ret
61  %head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
62  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
63  %vc = add <vscale x 2 x i8> %va, %splat
64  ret <vscale x 2 x i8> %vc
65}
66
67define <vscale x 2 x i8> @vadd_vx_nxv2i8_0(<vscale x 2 x i8> %va) {
68; CHECK-LABEL: vadd_vx_nxv2i8_0:
69; CHECK:       # %bb.0:
70; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
71; CHECK-NEXT:    vadd.vi v8, v8, -1
72; CHECK-NEXT:    ret
73  %head = insertelement <vscale x 2 x i8> undef, i8 -1, i32 0
74  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
75  %vc = add <vscale x 2 x i8> %va, %splat
76  ret <vscale x 2 x i8> %vc
77}
78
79define <vscale x 2 x i8> @vadd_vx_nxv2i8_1(<vscale x 2 x i8> %va) {
80; CHECK-LABEL: vadd_vx_nxv2i8_1:
81; CHECK:       # %bb.0:
82; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
83; CHECK-NEXT:    vadd.vi v8, v8, 2
84; CHECK-NEXT:    ret
85  %head = insertelement <vscale x 2 x i8> undef, i8 2, i32 0
86  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
87  %vc = add <vscale x 2 x i8> %va, %splat
88  ret <vscale x 2 x i8> %vc
89}
90
91define <vscale x 4 x i8> @vadd_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
92; CHECK-LABEL: vadd_vx_nxv4i8:
93; CHECK:       # %bb.0:
94; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
95; CHECK-NEXT:    vadd.vx v8, v8, a0
96; CHECK-NEXT:    ret
97  %head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
98  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
99  %vc = add <vscale x 4 x i8> %va, %splat
100  ret <vscale x 4 x i8> %vc
101}
102
103define <vscale x 4 x i8> @vadd_vx_nxv4i8_0(<vscale x 4 x i8> %va) {
104; CHECK-LABEL: vadd_vx_nxv4i8_0:
105; CHECK:       # %bb.0:
106; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
107; CHECK-NEXT:    vadd.vi v8, v8, -1
108; CHECK-NEXT:    ret
109  %head = insertelement <vscale x 4 x i8> undef, i8 -1, i32 0
110  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
111  %vc = add <vscale x 4 x i8> %va, %splat
112  ret <vscale x 4 x i8> %vc
113}
114
115define <vscale x 4 x i8> @vadd_vx_nxv4i8_1(<vscale x 4 x i8> %va) {
116; CHECK-LABEL: vadd_vx_nxv4i8_1:
117; CHECK:       # %bb.0:
118; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
119; CHECK-NEXT:    vadd.vi v8, v8, 2
120; CHECK-NEXT:    ret
121  %head = insertelement <vscale x 4 x i8> undef, i8 2, i32 0
122  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
123  %vc = add <vscale x 4 x i8> %va, %splat
124  ret <vscale x 4 x i8> %vc
125}
126
127define <vscale x 8 x i8> @vadd_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
128; CHECK-LABEL: vadd_vx_nxv8i8:
129; CHECK:       # %bb.0:
130; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
131; CHECK-NEXT:    vadd.vx v8, v8, a0
132; CHECK-NEXT:    ret
133  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
134  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
135  %vc = add <vscale x 8 x i8> %va, %splat
136  ret <vscale x 8 x i8> %vc
137}
138
139define <vscale x 8 x i8> @vadd_vx_nxv8i8_0(<vscale x 8 x i8> %va) {
140; CHECK-LABEL: vadd_vx_nxv8i8_0:
141; CHECK:       # %bb.0:
142; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
143; CHECK-NEXT:    vadd.vi v8, v8, -1
144; CHECK-NEXT:    ret
145  %head = insertelement <vscale x 8 x i8> undef, i8 -1, i32 0
146  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
147  %vc = add <vscale x 8 x i8> %va, %splat
148  ret <vscale x 8 x i8> %vc
149}
150
151define <vscale x 8 x i8> @vadd_vx_nxv8i8_1(<vscale x 8 x i8> %va) {
152; CHECK-LABEL: vadd_vx_nxv8i8_1:
153; CHECK:       # %bb.0:
154; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
155; CHECK-NEXT:    vadd.vi v8, v8, 2
156; CHECK-NEXT:    ret
157  %head = insertelement <vscale x 8 x i8> undef, i8 2, i32 0
158  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
159  %vc = add <vscale x 8 x i8> %va, %splat
160  ret <vscale x 8 x i8> %vc
161}
162
163define <vscale x 16 x i8> @vadd_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
164; CHECK-LABEL: vadd_vx_nxv16i8:
165; CHECK:       # %bb.0:
166; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
167; CHECK-NEXT:    vadd.vx v8, v8, a0
168; CHECK-NEXT:    ret
169  %head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
170  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
171  %vc = add <vscale x 16 x i8> %va, %splat
172  ret <vscale x 16 x i8> %vc
173}
174
175define <vscale x 16 x i8> @vadd_vx_nxv16i8_0(<vscale x 16 x i8> %va) {
176; CHECK-LABEL: vadd_vx_nxv16i8_0:
177; CHECK:       # %bb.0:
178; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
179; CHECK-NEXT:    vadd.vi v8, v8, -1
180; CHECK-NEXT:    ret
181  %head = insertelement <vscale x 16 x i8> undef, i8 -1, i32 0
182  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
183  %vc = add <vscale x 16 x i8> %va, %splat
184  ret <vscale x 16 x i8> %vc
185}
186
187define <vscale x 16 x i8> @vadd_vx_nxv16i8_1(<vscale x 16 x i8> %va) {
188; CHECK-LABEL: vadd_vx_nxv16i8_1:
189; CHECK:       # %bb.0:
190; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
191; CHECK-NEXT:    vadd.vi v8, v8, 2
192; CHECK-NEXT:    ret
193  %head = insertelement <vscale x 16 x i8> undef, i8 2, i32 0
194  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
195  %vc = add <vscale x 16 x i8> %va, %splat
196  ret <vscale x 16 x i8> %vc
197}
198
199define <vscale x 32 x i8> @vadd_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
200; CHECK-LABEL: vadd_vx_nxv32i8:
201; CHECK:       # %bb.0:
202; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
203; CHECK-NEXT:    vadd.vx v8, v8, a0
204; CHECK-NEXT:    ret
205  %head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
206  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
207  %vc = add <vscale x 32 x i8> %va, %splat
208  ret <vscale x 32 x i8> %vc
209}
210
211define <vscale x 32 x i8> @vadd_vx_nxv32i8_0(<vscale x 32 x i8> %va) {
212; CHECK-LABEL: vadd_vx_nxv32i8_0:
213; CHECK:       # %bb.0:
214; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, mu
215; CHECK-NEXT:    vadd.vi v8, v8, -1
216; CHECK-NEXT:    ret
217  %head = insertelement <vscale x 32 x i8> undef, i8 -1, i32 0
218  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
219  %vc = add <vscale x 32 x i8> %va, %splat
220  ret <vscale x 32 x i8> %vc
221}
222
223define <vscale x 32 x i8> @vadd_vx_nxv32i8_1(<vscale x 32 x i8> %va) {
224; CHECK-LABEL: vadd_vx_nxv32i8_1:
225; CHECK:       # %bb.0:
226; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, mu
227; CHECK-NEXT:    vadd.vi v8, v8, 2
228; CHECK-NEXT:    ret
229  %head = insertelement <vscale x 32 x i8> undef, i8 2, i32 0
230  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
231  %vc = add <vscale x 32 x i8> %va, %splat
232  ret <vscale x 32 x i8> %vc
233}
234
235define <vscale x 64 x i8> @vadd_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
236; CHECK-LABEL: vadd_vx_nxv64i8:
237; CHECK:       # %bb.0:
238; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, mu
239; CHECK-NEXT:    vadd.vx v8, v8, a0
240; CHECK-NEXT:    ret
241  %head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
242  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
243  %vc = add <vscale x 64 x i8> %va, %splat
244  ret <vscale x 64 x i8> %vc
245}
246
247define <vscale x 64 x i8> @vadd_vx_nxv64i8_0(<vscale x 64 x i8> %va) {
248; CHECK-LABEL: vadd_vx_nxv64i8_0:
249; CHECK:       # %bb.0:
250; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, mu
251; CHECK-NEXT:    vadd.vi v8, v8, -1
252; CHECK-NEXT:    ret
253  %head = insertelement <vscale x 64 x i8> undef, i8 -1, i32 0
254  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
255  %vc = add <vscale x 64 x i8> %va, %splat
256  ret <vscale x 64 x i8> %vc
257}
258
259define <vscale x 64 x i8> @vadd_vx_nxv64i8_1(<vscale x 64 x i8> %va) {
260; CHECK-LABEL: vadd_vx_nxv64i8_1:
261; CHECK:       # %bb.0:
262; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, mu
263; CHECK-NEXT:    vadd.vi v8, v8, 2
264; CHECK-NEXT:    ret
265  %head = insertelement <vscale x 64 x i8> undef, i8 2, i32 0
266  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
267  %vc = add <vscale x 64 x i8> %va, %splat
268  ret <vscale x 64 x i8> %vc
269}
270
271define <vscale x 1 x i16> @vadd_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
272; CHECK-LABEL: vadd_vx_nxv1i16:
273; CHECK:       # %bb.0:
274; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
275; CHECK-NEXT:    vadd.vx v8, v8, a0
276; CHECK-NEXT:    ret
277  %head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
278  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
279  %vc = add <vscale x 1 x i16> %va, %splat
280  ret <vscale x 1 x i16> %vc
281}
282
283define <vscale x 1 x i16> @vadd_vx_nxv1i16_0(<vscale x 1 x i16> %va) {
284; CHECK-LABEL: vadd_vx_nxv1i16_0:
285; CHECK:       # %bb.0:
286; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
287; CHECK-NEXT:    vadd.vi v8, v8, -1
288; CHECK-NEXT:    ret
289  %head = insertelement <vscale x 1 x i16> undef, i16 -1, i32 0
290  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
291  %vc = add <vscale x 1 x i16> %va, %splat
292  ret <vscale x 1 x i16> %vc
293}
294
295define <vscale x 1 x i16> @vadd_vx_nxv1i16_1(<vscale x 1 x i16> %va) {
296; CHECK-LABEL: vadd_vx_nxv1i16_1:
297; CHECK:       # %bb.0:
298; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
299; CHECK-NEXT:    vadd.vi v8, v8, 2
300; CHECK-NEXT:    ret
301  %head = insertelement <vscale x 1 x i16> undef, i16 2, i32 0
302  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
303  %vc = add <vscale x 1 x i16> %va, %splat
304  ret <vscale x 1 x i16> %vc
305}
306
307define <vscale x 2 x i16> @vadd_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
308; CHECK-LABEL: vadd_vx_nxv2i16:
309; CHECK:       # %bb.0:
310; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
311; CHECK-NEXT:    vadd.vx v8, v8, a0
312; CHECK-NEXT:    ret
313  %head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
314  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
315  %vc = add <vscale x 2 x i16> %va, %splat
316  ret <vscale x 2 x i16> %vc
317}
318
319define <vscale x 2 x i16> @vadd_vx_nxv2i16_0(<vscale x 2 x i16> %va) {
320; CHECK-LABEL: vadd_vx_nxv2i16_0:
321; CHECK:       # %bb.0:
322; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
323; CHECK-NEXT:    vadd.vi v8, v8, -1
324; CHECK-NEXT:    ret
325  %head = insertelement <vscale x 2 x i16> undef, i16 -1, i32 0
326  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
327  %vc = add <vscale x 2 x i16> %va, %splat
328  ret <vscale x 2 x i16> %vc
329}
330
331define <vscale x 2 x i16> @vadd_vx_nxv2i16_1(<vscale x 2 x i16> %va) {
332; CHECK-LABEL: vadd_vx_nxv2i16_1:
333; CHECK:       # %bb.0:
334; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
335; CHECK-NEXT:    vadd.vi v8, v8, 2
336; CHECK-NEXT:    ret
337  %head = insertelement <vscale x 2 x i16> undef, i16 2, i32 0
338  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
339  %vc = add <vscale x 2 x i16> %va, %splat
340  ret <vscale x 2 x i16> %vc
341}
342
343define <vscale x 4 x i16> @vadd_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
344; CHECK-LABEL: vadd_vx_nxv4i16:
345; CHECK:       # %bb.0:
346; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
347; CHECK-NEXT:    vadd.vx v8, v8, a0
348; CHECK-NEXT:    ret
349  %head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
350  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
351  %vc = add <vscale x 4 x i16> %va, %splat
352  ret <vscale x 4 x i16> %vc
353}
354
355define <vscale x 4 x i16> @vadd_vx_nxv4i16_0(<vscale x 4 x i16> %va) {
356; CHECK-LABEL: vadd_vx_nxv4i16_0:
357; CHECK:       # %bb.0:
358; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
359; CHECK-NEXT:    vadd.vi v8, v8, -1
360; CHECK-NEXT:    ret
361  %head = insertelement <vscale x 4 x i16> undef, i16 -1, i32 0
362  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
363  %vc = add <vscale x 4 x i16> %va, %splat
364  ret <vscale x 4 x i16> %vc
365}
366
367define <vscale x 4 x i16> @vadd_vx_nxv4i16_1(<vscale x 4 x i16> %va) {
368; CHECK-LABEL: vadd_vx_nxv4i16_1:
369; CHECK:       # %bb.0:
370; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
371; CHECK-NEXT:    vadd.vi v8, v8, 2
372; CHECK-NEXT:    ret
373  %head = insertelement <vscale x 4 x i16> undef, i16 2, i32 0
374  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
375  %vc = add <vscale x 4 x i16> %va, %splat
376  ret <vscale x 4 x i16> %vc
377}
378
379define <vscale x 8 x i16> @vadd_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
380; CHECK-LABEL: vadd_vx_nxv8i16:
381; CHECK:       # %bb.0:
382; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
383; CHECK-NEXT:    vadd.vx v8, v8, a0
384; CHECK-NEXT:    ret
385  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
386  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
387  %vc = add <vscale x 8 x i16> %va, %splat
388  ret <vscale x 8 x i16> %vc
389}
390
391define <vscale x 8 x i16> @vadd_vx_nxv8i16_0(<vscale x 8 x i16> %va) {
392; CHECK-LABEL: vadd_vx_nxv8i16_0:
393; CHECK:       # %bb.0:
394; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
395; CHECK-NEXT:    vadd.vi v8, v8, -1
396; CHECK-NEXT:    ret
397  %head = insertelement <vscale x 8 x i16> undef, i16 -1, i32 0
398  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
399  %vc = add <vscale x 8 x i16> %va, %splat
400  ret <vscale x 8 x i16> %vc
401}
402
403define <vscale x 8 x i16> @vadd_vx_nxv8i16_1(<vscale x 8 x i16> %va) {
404; CHECK-LABEL: vadd_vx_nxv8i16_1:
405; CHECK:       # %bb.0:
406; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
407; CHECK-NEXT:    vadd.vi v8, v8, 2
408; CHECK-NEXT:    ret
409  %head = insertelement <vscale x 8 x i16> undef, i16 2, i32 0
410  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
411  %vc = add <vscale x 8 x i16> %va, %splat
412  ret <vscale x 8 x i16> %vc
413}
414
415define <vscale x 16 x i16> @vadd_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
416; CHECK-LABEL: vadd_vx_nxv16i16:
417; CHECK:       # %bb.0:
418; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
419; CHECK-NEXT:    vadd.vx v8, v8, a0
420; CHECK-NEXT:    ret
421  %head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
422  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
423  %vc = add <vscale x 16 x i16> %va, %splat
424  ret <vscale x 16 x i16> %vc
425}
426
427define <vscale x 16 x i16> @vadd_vx_nxv16i16_0(<vscale x 16 x i16> %va) {
428; CHECK-LABEL: vadd_vx_nxv16i16_0:
429; CHECK:       # %bb.0:
430; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
431; CHECK-NEXT:    vadd.vi v8, v8, -1
432; CHECK-NEXT:    ret
433  %head = insertelement <vscale x 16 x i16> undef, i16 -1, i32 0
434  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
435  %vc = add <vscale x 16 x i16> %va, %splat
436  ret <vscale x 16 x i16> %vc
437}
438
439define <vscale x 16 x i16> @vadd_vx_nxv16i16_1(<vscale x 16 x i16> %va) {
440; CHECK-LABEL: vadd_vx_nxv16i16_1:
441; CHECK:       # %bb.0:
442; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
443; CHECK-NEXT:    vadd.vi v8, v8, 2
444; CHECK-NEXT:    ret
445  %head = insertelement <vscale x 16 x i16> undef, i16 2, i32 0
446  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
447  %vc = add <vscale x 16 x i16> %va, %splat
448  ret <vscale x 16 x i16> %vc
449}
450
451define <vscale x 32 x i16> @vadd_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
452; CHECK-LABEL: vadd_vx_nxv32i16:
453; CHECK:       # %bb.0:
454; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
455; CHECK-NEXT:    vadd.vx v8, v8, a0
456; CHECK-NEXT:    ret
457  %head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
458  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
459  %vc = add <vscale x 32 x i16> %va, %splat
460  ret <vscale x 32 x i16> %vc
461}
462
463define <vscale x 32 x i16> @vadd_vx_nxv32i16_0(<vscale x 32 x i16> %va) {
464; CHECK-LABEL: vadd_vx_nxv32i16_0:
465; CHECK:       # %bb.0:
466; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
467; CHECK-NEXT:    vadd.vi v8, v8, -1
468; CHECK-NEXT:    ret
469  %head = insertelement <vscale x 32 x i16> undef, i16 -1, i32 0
470  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
471  %vc = add <vscale x 32 x i16> %va, %splat
472  ret <vscale x 32 x i16> %vc
473}
474
475define <vscale x 32 x i16> @vadd_vx_nxv32i16_1(<vscale x 32 x i16> %va) {
476; CHECK-LABEL: vadd_vx_nxv32i16_1:
477; CHECK:       # %bb.0:
478; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
479; CHECK-NEXT:    vadd.vi v8, v8, 2
480; CHECK-NEXT:    ret
481  %head = insertelement <vscale x 32 x i16> undef, i16 2, i32 0
482  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
483  %vc = add <vscale x 32 x i16> %va, %splat
484  ret <vscale x 32 x i16> %vc
485}
486
487define <vscale x 1 x i32> @vadd_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {
488; CHECK-LABEL: vadd_vx_nxv1i32:
489; CHECK:       # %bb.0:
490; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
491; CHECK-NEXT:    vadd.vx v8, v8, a0
492; CHECK-NEXT:    ret
493  %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
494  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
495  %vc = add <vscale x 1 x i32> %va, %splat
496  ret <vscale x 1 x i32> %vc
497}
498
499define <vscale x 1 x i32> @vadd_vx_nxv1i32_0(<vscale x 1 x i32> %va) {
500; CHECK-LABEL: vadd_vx_nxv1i32_0:
501; CHECK:       # %bb.0:
502; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
503; CHECK-NEXT:    vadd.vi v8, v8, -1
504; CHECK-NEXT:    ret
505  %head = insertelement <vscale x 1 x i32> undef, i32 -1, i32 0
506  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
507  %vc = add <vscale x 1 x i32> %va, %splat
508  ret <vscale x 1 x i32> %vc
509}
510
511define <vscale x 1 x i32> @vadd_vx_nxv1i32_1(<vscale x 1 x i32> %va) {
512; CHECK-LABEL: vadd_vx_nxv1i32_1:
513; CHECK:       # %bb.0:
514; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
515; CHECK-NEXT:    vadd.vi v8, v8, 2
516; CHECK-NEXT:    ret
517  %head = insertelement <vscale x 1 x i32> undef, i32 2, i32 0
518  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
519  %vc = add <vscale x 1 x i32> %va, %splat
520  ret <vscale x 1 x i32> %vc
521}
522
523define <vscale x 2 x i32> @vadd_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
524; CHECK-LABEL: vadd_vx_nxv2i32:
525; CHECK:       # %bb.0:
526; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
527; CHECK-NEXT:    vadd.vx v8, v8, a0
528; CHECK-NEXT:    ret
529  %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
530  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
531  %vc = add <vscale x 2 x i32> %va, %splat
532  ret <vscale x 2 x i32> %vc
533}
534
535define <vscale x 2 x i32> @vadd_vx_nxv2i32_0(<vscale x 2 x i32> %va) {
536; CHECK-LABEL: vadd_vx_nxv2i32_0:
537; CHECK:       # %bb.0:
538; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
539; CHECK-NEXT:    vadd.vi v8, v8, -1
540; CHECK-NEXT:    ret
541  %head = insertelement <vscale x 2 x i32> undef, i32 -1, i32 0
542  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
543  %vc = add <vscale x 2 x i32> %va, %splat
544  ret <vscale x 2 x i32> %vc
545}
546
547define <vscale x 2 x i32> @vadd_vx_nxv2i32_1(<vscale x 2 x i32> %va) {
548; CHECK-LABEL: vadd_vx_nxv2i32_1:
549; CHECK:       # %bb.0:
550; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
551; CHECK-NEXT:    vadd.vi v8, v8, 2
552; CHECK-NEXT:    ret
553  %head = insertelement <vscale x 2 x i32> undef, i32 2, i32 0
554  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
555  %vc = add <vscale x 2 x i32> %va, %splat
556  ret <vscale x 2 x i32> %vc
557}
558
559define <vscale x 4 x i32> @vadd_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
560; CHECK-LABEL: vadd_vx_nxv4i32:
561; CHECK:       # %bb.0:
562; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
563; CHECK-NEXT:    vadd.vx v8, v8, a0
564; CHECK-NEXT:    ret
565  %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
566  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
567  %vc = add <vscale x 4 x i32> %va, %splat
568  ret <vscale x 4 x i32> %vc
569}
570
571define <vscale x 4 x i32> @vadd_vx_nxv4i32_0(<vscale x 4 x i32> %va) {
572; CHECK-LABEL: vadd_vx_nxv4i32_0:
573; CHECK:       # %bb.0:
574; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
575; CHECK-NEXT:    vadd.vi v8, v8, -1
576; CHECK-NEXT:    ret
577  %head = insertelement <vscale x 4 x i32> undef, i32 -1, i32 0
578  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
579  %vc = add <vscale x 4 x i32> %va, %splat
580  ret <vscale x 4 x i32> %vc
581}
582
583define <vscale x 4 x i32> @vadd_vx_nxv4i32_1(<vscale x 4 x i32> %va) {
584; CHECK-LABEL: vadd_vx_nxv4i32_1:
585; CHECK:       # %bb.0:
586; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
587; CHECK-NEXT:    vadd.vi v8, v8, 2
588; CHECK-NEXT:    ret
589  %head = insertelement <vscale x 4 x i32> undef, i32 2, i32 0
590  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
591  %vc = add <vscale x 4 x i32> %va, %splat
592  ret <vscale x 4 x i32> %vc
593}
594
595define <vscale x 8 x i32> @vadd_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
596; CHECK-LABEL: vadd_vx_nxv8i32:
597; CHECK:       # %bb.0:
598; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
599; CHECK-NEXT:    vadd.vx v8, v8, a0
600; CHECK-NEXT:    ret
601  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
602  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
603  %vc = add <vscale x 8 x i32> %va, %splat
604  ret <vscale x 8 x i32> %vc
605}
606
607define <vscale x 8 x i32> @vadd_vx_nxv8i32_0(<vscale x 8 x i32> %va) {
608; CHECK-LABEL: vadd_vx_nxv8i32_0:
609; CHECK:       # %bb.0:
610; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
611; CHECK-NEXT:    vadd.vi v8, v8, -1
612; CHECK-NEXT:    ret
613  %head = insertelement <vscale x 8 x i32> undef, i32 -1, i32 0
614  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
615  %vc = add <vscale x 8 x i32> %va, %splat
616  ret <vscale x 8 x i32> %vc
617}
618
619define <vscale x 8 x i32> @vadd_vx_nxv8i32_1(<vscale x 8 x i32> %va) {
620; CHECK-LABEL: vadd_vx_nxv8i32_1:
621; CHECK:       # %bb.0:
622; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
623; CHECK-NEXT:    vadd.vi v8, v8, 2
624; CHECK-NEXT:    ret
625  %head = insertelement <vscale x 8 x i32> undef, i32 2, i32 0
626  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
627  %vc = add <vscale x 8 x i32> %va, %splat
628  ret <vscale x 8 x i32> %vc
629}
630
631define <vscale x 16 x i32> @vadd_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
632; CHECK-LABEL: vadd_vx_nxv16i32:
633; CHECK:       # %bb.0:
634; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
635; CHECK-NEXT:    vadd.vx v8, v8, a0
636; CHECK-NEXT:    ret
637  %head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
638  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
639  %vc = add <vscale x 16 x i32> %va, %splat
640  ret <vscale x 16 x i32> %vc
641}
642
643define <vscale x 16 x i32> @vadd_vx_nxv16i32_0(<vscale x 16 x i32> %va) {
644; CHECK-LABEL: vadd_vx_nxv16i32_0:
645; CHECK:       # %bb.0:
646; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
647; CHECK-NEXT:    vadd.vi v8, v8, -1
648; CHECK-NEXT:    ret
649  %head = insertelement <vscale x 16 x i32> undef, i32 -1, i32 0
650  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
651  %vc = add <vscale x 16 x i32> %va, %splat
652  ret <vscale x 16 x i32> %vc
653}
654
655define <vscale x 16 x i32> @vadd_vx_nxv16i32_1(<vscale x 16 x i32> %va) {
656; CHECK-LABEL: vadd_vx_nxv16i32_1:
657; CHECK:       # %bb.0:
658; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
659; CHECK-NEXT:    vadd.vi v8, v8, 2
660; CHECK-NEXT:    ret
661  %head = insertelement <vscale x 16 x i32> undef, i32 2, i32 0
662  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
663  %vc = add <vscale x 16 x i32> %va, %splat
664  ret <vscale x 16 x i32> %vc
665}
666
667define <vscale x 1 x i64> @vadd_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
668; CHECK-LABEL: vadd_vx_nxv1i64:
669; CHECK:       # %bb.0:
670; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
671; CHECK-NEXT:    vadd.vx v8, v8, a0
672; CHECK-NEXT:    ret
673  %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
674  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
675  %vc = add <vscale x 1 x i64> %va, %splat
676  ret <vscale x 1 x i64> %vc
677}
678
679define <vscale x 1 x i64> @vadd_vx_nxv1i64_0(<vscale x 1 x i64> %va) {
680; CHECK-LABEL: vadd_vx_nxv1i64_0:
681; CHECK:       # %bb.0:
682; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
683; CHECK-NEXT:    vadd.vi v8, v8, -1
684; CHECK-NEXT:    ret
685  %head = insertelement <vscale x 1 x i64> undef, i64 -1, i32 0
686  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
687  %vc = add <vscale x 1 x i64> %va, %splat
688  ret <vscale x 1 x i64> %vc
689}
690
691define <vscale x 1 x i64> @vadd_vx_nxv1i64_1(<vscale x 1 x i64> %va) {
692; CHECK-LABEL: vadd_vx_nxv1i64_1:
693; CHECK:       # %bb.0:
694; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
695; CHECK-NEXT:    vadd.vi v8, v8, 2
696; CHECK-NEXT:    ret
697  %head = insertelement <vscale x 1 x i64> undef, i64 2, i32 0
698  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
699  %vc = add <vscale x 1 x i64> %va, %splat
700  ret <vscale x 1 x i64> %vc
701}
702
703define <vscale x 2 x i64> @vadd_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
704; CHECK-LABEL: vadd_vx_nxv2i64:
705; CHECK:       # %bb.0:
706; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
707; CHECK-NEXT:    vadd.vx v8, v8, a0
708; CHECK-NEXT:    ret
709  %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
710  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
711  %vc = add <vscale x 2 x i64> %va, %splat
712  ret <vscale x 2 x i64> %vc
713}
714
715define <vscale x 2 x i64> @vadd_vx_nxv2i64_0(<vscale x 2 x i64> %va) {
716; CHECK-LABEL: vadd_vx_nxv2i64_0:
717; CHECK:       # %bb.0:
718; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
719; CHECK-NEXT:    vadd.vi v8, v8, -1
720; CHECK-NEXT:    ret
721  %head = insertelement <vscale x 2 x i64> undef, i64 -1, i32 0
722  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
723  %vc = add <vscale x 2 x i64> %va, %splat
724  ret <vscale x 2 x i64> %vc
725}
726
727define <vscale x 2 x i64> @vadd_vx_nxv2i64_1(<vscale x 2 x i64> %va) {
728; CHECK-LABEL: vadd_vx_nxv2i64_1:
729; CHECK:       # %bb.0:
730; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
731; CHECK-NEXT:    vadd.vi v8, v8, 2
732; CHECK-NEXT:    ret
733  %head = insertelement <vscale x 2 x i64> undef, i64 2, i32 0
734  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
735  %vc = add <vscale x 2 x i64> %va, %splat
736  ret <vscale x 2 x i64> %vc
737}
738
739define <vscale x 4 x i64> @vadd_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
740; CHECK-LABEL: vadd_vx_nxv4i64:
741; CHECK:       # %bb.0:
742; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
743; CHECK-NEXT:    vadd.vx v8, v8, a0
744; CHECK-NEXT:    ret
745  %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
746  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
747  %vc = add <vscale x 4 x i64> %va, %splat
748  ret <vscale x 4 x i64> %vc
749}
750
751define <vscale x 4 x i64> @vadd_vx_nxv4i64_0(<vscale x 4 x i64> %va) {
752; CHECK-LABEL: vadd_vx_nxv4i64_0:
753; CHECK:       # %bb.0:
754; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
755; CHECK-NEXT:    vadd.vi v8, v8, -1
756; CHECK-NEXT:    ret
757  %head = insertelement <vscale x 4 x i64> undef, i64 -1, i32 0
758  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
759  %vc = add <vscale x 4 x i64> %va, %splat
760  ret <vscale x 4 x i64> %vc
761}
762
763define <vscale x 4 x i64> @vadd_vx_nxv4i64_1(<vscale x 4 x i64> %va) {
764; CHECK-LABEL: vadd_vx_nxv4i64_1:
765; CHECK:       # %bb.0:
766; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
767; CHECK-NEXT:    vadd.vi v8, v8, 2
768; CHECK-NEXT:    ret
769  %head = insertelement <vscale x 4 x i64> undef, i64 2, i32 0
770  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
771  %vc = add <vscale x 4 x i64> %va, %splat
772  ret <vscale x 4 x i64> %vc
773}
774
775define <vscale x 8 x i64> @vadd_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
776; CHECK-LABEL: vadd_vx_nxv8i64:
777; CHECK:       # %bb.0:
778; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
779; CHECK-NEXT:    vadd.vx v8, v8, a0
780; CHECK-NEXT:    ret
781  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
782  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
783  %vc = add <vscale x 8 x i64> %va, %splat
784  ret <vscale x 8 x i64> %vc
785}
786
787define <vscale x 8 x i64> @vadd_vx_nxv8i64_0(<vscale x 8 x i64> %va) {
788; CHECK-LABEL: vadd_vx_nxv8i64_0:
789; CHECK:       # %bb.0:
790; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
791; CHECK-NEXT:    vadd.vi v8, v8, -1
792; CHECK-NEXT:    ret
793  %head = insertelement <vscale x 8 x i64> undef, i64 -1, i32 0
794  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
795  %vc = add <vscale x 8 x i64> %va, %splat
796  ret <vscale x 8 x i64> %vc
797}
798
799define <vscale x 8 x i64> @vadd_vx_nxv8i64_1(<vscale x 8 x i64> %va) {
800; CHECK-LABEL: vadd_vx_nxv8i64_1:
801; CHECK:       # %bb.0:
802; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
803; CHECK-NEXT:    vadd.vi v8, v8, 2
804; CHECK-NEXT:    ret
805  %head = insertelement <vscale x 8 x i64> undef, i64 2, i32 0
806  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
807  %vc = add <vscale x 8 x i64> %va, %splat
808  ret <vscale x 8 x i64> %vc
809}
810