1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
3
4define <vscale x 1 x i8> @vsrl_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
5; CHECK-LABEL: vsrl_vx_nxv1i8:
6; CHECK:       # %bb.0:
7; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
8; CHECK-NEXT:    vsrl.vx v8, v8, a0
9; CHECK-NEXT:    ret
10  %head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
11  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
12  %vc = lshr <vscale x 1 x i8> %va, %splat
13  ret <vscale x 1 x i8> %vc
14}
15
16define <vscale x 1 x i8> @vsrl_vx_nxv1i8_0(<vscale x 1 x i8> %va) {
17; CHECK-LABEL: vsrl_vx_nxv1i8_0:
18; CHECK:       # %bb.0:
19; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
20; CHECK-NEXT:    vsrl.vi v8, v8, 6
21; CHECK-NEXT:    ret
22  %head = insertelement <vscale x 1 x i8> undef, i8 6, i32 0
23  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
24  %vc = lshr <vscale x 1 x i8> %va, %splat
25  ret <vscale x 1 x i8> %vc
26}
27
28define <vscale x 2 x i8> @vsrl_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
29; CHECK-LABEL: vsrl_vx_nxv2i8:
30; CHECK:       # %bb.0:
31; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
32; CHECK-NEXT:    vsrl.vx v8, v8, a0
33; CHECK-NEXT:    ret
34  %head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
35  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
36  %vc = lshr <vscale x 2 x i8> %va, %splat
37  ret <vscale x 2 x i8> %vc
38}
39
40define <vscale x 2 x i8> @vsrl_vx_nxv2i8_0(<vscale x 2 x i8> %va) {
41; CHECK-LABEL: vsrl_vx_nxv2i8_0:
42; CHECK:       # %bb.0:
43; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
44; CHECK-NEXT:    vsrl.vi v8, v8, 6
45; CHECK-NEXT:    ret
46  %head = insertelement <vscale x 2 x i8> undef, i8 6, i32 0
47  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
48  %vc = lshr <vscale x 2 x i8> %va, %splat
49  ret <vscale x 2 x i8> %vc
50}
51
52define <vscale x 4 x i8> @vsrl_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
53; CHECK-LABEL: vsrl_vx_nxv4i8:
54; CHECK:       # %bb.0:
55; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
56; CHECK-NEXT:    vsrl.vx v8, v8, a0
57; CHECK-NEXT:    ret
58  %head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
59  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
60  %vc = lshr <vscale x 4 x i8> %va, %splat
61  ret <vscale x 4 x i8> %vc
62}
63
64define <vscale x 4 x i8> @vsrl_vx_nxv4i8_0(<vscale x 4 x i8> %va) {
65; CHECK-LABEL: vsrl_vx_nxv4i8_0:
66; CHECK:       # %bb.0:
67; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
68; CHECK-NEXT:    vsrl.vi v8, v8, 6
69; CHECK-NEXT:    ret
70  %head = insertelement <vscale x 4 x i8> undef, i8 6, i32 0
71  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
72  %vc = lshr <vscale x 4 x i8> %va, %splat
73  ret <vscale x 4 x i8> %vc
74}
75
76define <vscale x 8 x i8> @vsrl_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
77; CHECK-LABEL: vsrl_vx_nxv8i8:
78; CHECK:       # %bb.0:
79; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
80; CHECK-NEXT:    vsrl.vx v8, v8, a0
81; CHECK-NEXT:    ret
82  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
83  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
84  %vc = lshr <vscale x 8 x i8> %va, %splat
85  ret <vscale x 8 x i8> %vc
86}
87
88define <vscale x 8 x i8> @vsrl_vx_nxv8i8_0(<vscale x 8 x i8> %va) {
89; CHECK-LABEL: vsrl_vx_nxv8i8_0:
90; CHECK:       # %bb.0:
91; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
92; CHECK-NEXT:    vsrl.vi v8, v8, 6
93; CHECK-NEXT:    ret
94  %head = insertelement <vscale x 8 x i8> undef, i8 6, i32 0
95  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
96  %vc = lshr <vscale x 8 x i8> %va, %splat
97  ret <vscale x 8 x i8> %vc
98}
99
100define <vscale x 16 x i8> @vsrl_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
101; CHECK-LABEL: vsrl_vx_nxv16i8:
102; CHECK:       # %bb.0:
103; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
104; CHECK-NEXT:    vsrl.vx v8, v8, a0
105; CHECK-NEXT:    ret
106  %head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
107  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
108  %vc = lshr <vscale x 16 x i8> %va, %splat
109  ret <vscale x 16 x i8> %vc
110}
111
112define <vscale x 16 x i8> @vsrl_vx_nxv16i8_0(<vscale x 16 x i8> %va) {
113; CHECK-LABEL: vsrl_vx_nxv16i8_0:
114; CHECK:       # %bb.0:
115; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
116; CHECK-NEXT:    vsrl.vi v8, v8, 6
117; CHECK-NEXT:    ret
118  %head = insertelement <vscale x 16 x i8> undef, i8 6, i32 0
119  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
120  %vc = lshr <vscale x 16 x i8> %va, %splat
121  ret <vscale x 16 x i8> %vc
122}
123
124define <vscale x 32 x i8> @vsrl_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
125; CHECK-LABEL: vsrl_vx_nxv32i8:
126; CHECK:       # %bb.0:
127; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
128; CHECK-NEXT:    vsrl.vx v8, v8, a0
129; CHECK-NEXT:    ret
130  %head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
131  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
132  %vc = lshr <vscale x 32 x i8> %va, %splat
133  ret <vscale x 32 x i8> %vc
134}
135
136define <vscale x 32 x i8> @vsrl_vx_nxv32i8_0(<vscale x 32 x i8> %va) {
137; CHECK-LABEL: vsrl_vx_nxv32i8_0:
138; CHECK:       # %bb.0:
139; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, mu
140; CHECK-NEXT:    vsrl.vi v8, v8, 6
141; CHECK-NEXT:    ret
142  %head = insertelement <vscale x 32 x i8> undef, i8 6, i32 0
143  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
144  %vc = lshr <vscale x 32 x i8> %va, %splat
145  ret <vscale x 32 x i8> %vc
146}
147
148define <vscale x 64 x i8> @vsrl_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
149; CHECK-LABEL: vsrl_vx_nxv64i8:
150; CHECK:       # %bb.0:
151; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, mu
152; CHECK-NEXT:    vsrl.vx v8, v8, a0
153; CHECK-NEXT:    ret
154  %head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
155  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
156  %vc = lshr <vscale x 64 x i8> %va, %splat
157  ret <vscale x 64 x i8> %vc
158}
159
160define <vscale x 64 x i8> @vsrl_vx_nxv64i8_0(<vscale x 64 x i8> %va) {
161; CHECK-LABEL: vsrl_vx_nxv64i8_0:
162; CHECK:       # %bb.0:
163; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, mu
164; CHECK-NEXT:    vsrl.vi v8, v8, 6
165; CHECK-NEXT:    ret
166  %head = insertelement <vscale x 64 x i8> undef, i8 6, i32 0
167  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
168  %vc = lshr <vscale x 64 x i8> %va, %splat
169  ret <vscale x 64 x i8> %vc
170}
171
172define <vscale x 1 x i16> @vsrl_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
173; CHECK-LABEL: vsrl_vx_nxv1i16:
174; CHECK:       # %bb.0:
175; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
176; CHECK-NEXT:    vsrl.vx v8, v8, a0
177; CHECK-NEXT:    ret
178  %head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
179  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
180  %vc = lshr <vscale x 1 x i16> %va, %splat
181  ret <vscale x 1 x i16> %vc
182}
183
184define <vscale x 1 x i16> @vsrl_vx_nxv1i16_0(<vscale x 1 x i16> %va) {
185; CHECK-LABEL: vsrl_vx_nxv1i16_0:
186; CHECK:       # %bb.0:
187; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
188; CHECK-NEXT:    vsrl.vi v8, v8, 6
189; CHECK-NEXT:    ret
190  %head = insertelement <vscale x 1 x i16> undef, i16 6, i32 0
191  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
192  %vc = lshr <vscale x 1 x i16> %va, %splat
193  ret <vscale x 1 x i16> %vc
194}
195
196define <vscale x 2 x i16> @vsrl_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
197; CHECK-LABEL: vsrl_vx_nxv2i16:
198; CHECK:       # %bb.0:
199; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
200; CHECK-NEXT:    vsrl.vx v8, v8, a0
201; CHECK-NEXT:    ret
202  %head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
203  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
204  %vc = lshr <vscale x 2 x i16> %va, %splat
205  ret <vscale x 2 x i16> %vc
206}
207
208define <vscale x 2 x i16> @vsrl_vx_nxv2i16_0(<vscale x 2 x i16> %va) {
209; CHECK-LABEL: vsrl_vx_nxv2i16_0:
210; CHECK:       # %bb.0:
211; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
212; CHECK-NEXT:    vsrl.vi v8, v8, 6
213; CHECK-NEXT:    ret
214  %head = insertelement <vscale x 2 x i16> undef, i16 6, i32 0
215  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
216  %vc = lshr <vscale x 2 x i16> %va, %splat
217  ret <vscale x 2 x i16> %vc
218}
219
220define <vscale x 4 x i16> @vsrl_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
221; CHECK-LABEL: vsrl_vx_nxv4i16:
222; CHECK:       # %bb.0:
223; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
224; CHECK-NEXT:    vsrl.vx v8, v8, a0
225; CHECK-NEXT:    ret
226  %head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
227  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
228  %vc = lshr <vscale x 4 x i16> %va, %splat
229  ret <vscale x 4 x i16> %vc
230}
231
232define <vscale x 4 x i16> @vsrl_vx_nxv4i16_0(<vscale x 4 x i16> %va) {
233; CHECK-LABEL: vsrl_vx_nxv4i16_0:
234; CHECK:       # %bb.0:
235; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
236; CHECK-NEXT:    vsrl.vi v8, v8, 6
237; CHECK-NEXT:    ret
238  %head = insertelement <vscale x 4 x i16> undef, i16 6, i32 0
239  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
240  %vc = lshr <vscale x 4 x i16> %va, %splat
241  ret <vscale x 4 x i16> %vc
242}
243
244define <vscale x 8 x i16> @vsrl_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
245; CHECK-LABEL: vsrl_vx_nxv8i16:
246; CHECK:       # %bb.0:
247; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
248; CHECK-NEXT:    vsrl.vx v8, v8, a0
249; CHECK-NEXT:    ret
250  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
251  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
252  %vc = lshr <vscale x 8 x i16> %va, %splat
253  ret <vscale x 8 x i16> %vc
254}
255
256define <vscale x 8 x i16> @vsrl_vx_nxv8i16_0(<vscale x 8 x i16> %va) {
257; CHECK-LABEL: vsrl_vx_nxv8i16_0:
258; CHECK:       # %bb.0:
259; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
260; CHECK-NEXT:    vsrl.vi v8, v8, 6
261; CHECK-NEXT:    ret
262  %head = insertelement <vscale x 8 x i16> undef, i16 6, i32 0
263  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
264  %vc = lshr <vscale x 8 x i16> %va, %splat
265  ret <vscale x 8 x i16> %vc
266}
267
268define <vscale x 16 x i16> @vsrl_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
269; CHECK-LABEL: vsrl_vx_nxv16i16:
270; CHECK:       # %bb.0:
271; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
272; CHECK-NEXT:    vsrl.vx v8, v8, a0
273; CHECK-NEXT:    ret
274  %head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
275  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
276  %vc = lshr <vscale x 16 x i16> %va, %splat
277  ret <vscale x 16 x i16> %vc
278}
279
280define <vscale x 16 x i16> @vsrl_vx_nxv16i16_0(<vscale x 16 x i16> %va) {
281; CHECK-LABEL: vsrl_vx_nxv16i16_0:
282; CHECK:       # %bb.0:
283; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
284; CHECK-NEXT:    vsrl.vi v8, v8, 6
285; CHECK-NEXT:    ret
286  %head = insertelement <vscale x 16 x i16> undef, i16 6, i32 0
287  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
288  %vc = lshr <vscale x 16 x i16> %va, %splat
289  ret <vscale x 16 x i16> %vc
290}
291
292define <vscale x 32 x i16> @vsrl_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
293; CHECK-LABEL: vsrl_vx_nxv32i16:
294; CHECK:       # %bb.0:
295; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
296; CHECK-NEXT:    vsrl.vx v8, v8, a0
297; CHECK-NEXT:    ret
298  %head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
299  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
300  %vc = lshr <vscale x 32 x i16> %va, %splat
301  ret <vscale x 32 x i16> %vc
302}
303
304define <vscale x 32 x i16> @vsrl_vx_nxv32i16_0(<vscale x 32 x i16> %va) {
305; CHECK-LABEL: vsrl_vx_nxv32i16_0:
306; CHECK:       # %bb.0:
307; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
308; CHECK-NEXT:    vsrl.vi v8, v8, 6
309; CHECK-NEXT:    ret
310  %head = insertelement <vscale x 32 x i16> undef, i16 6, i32 0
311  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
312  %vc = lshr <vscale x 32 x i16> %va, %splat
313  ret <vscale x 32 x i16> %vc
314}
315
316define <vscale x 1 x i32> @vsrl_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b) {
317; CHECK-LABEL: vsrl_vx_nxv1i32:
318; CHECK:       # %bb.0:
319; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
320; CHECK-NEXT:    vsrl.vx v8, v8, a0
321; CHECK-NEXT:    ret
322  %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
323  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
324  %vc = lshr <vscale x 1 x i32> %va, %splat
325  ret <vscale x 1 x i32> %vc
326}
327
328define <vscale x 1 x i32> @vsrl_vx_nxv1i32_0(<vscale x 1 x i32> %va) {
329; CHECK-LABEL: vsrl_vx_nxv1i32_0:
330; CHECK:       # %bb.0:
331; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
332; CHECK-NEXT:    vsrl.vi v8, v8, 31
333; CHECK-NEXT:    ret
334  %head = insertelement <vscale x 1 x i32> undef, i32 31, i32 0
335  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
336  %vc = lshr <vscale x 1 x i32> %va, %splat
337  ret <vscale x 1 x i32> %vc
338}
339
340define <vscale x 2 x i32> @vsrl_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b) {
341; CHECK-LABEL: vsrl_vx_nxv2i32:
342; CHECK:       # %bb.0:
343; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
344; CHECK-NEXT:    vsrl.vx v8, v8, a0
345; CHECK-NEXT:    ret
346  %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
347  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
348  %vc = lshr <vscale x 2 x i32> %va, %splat
349  ret <vscale x 2 x i32> %vc
350}
351
352define <vscale x 2 x i32> @vsrl_vx_nxv2i32_0(<vscale x 2 x i32> %va) {
353; CHECK-LABEL: vsrl_vx_nxv2i32_0:
354; CHECK:       # %bb.0:
355; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
356; CHECK-NEXT:    vsrl.vi v8, v8, 31
357; CHECK-NEXT:    ret
358  %head = insertelement <vscale x 2 x i32> undef, i32 31, i32 0
359  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
360  %vc = lshr <vscale x 2 x i32> %va, %splat
361  ret <vscale x 2 x i32> %vc
362}
363
364define <vscale x 4 x i32> @vsrl_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b) {
365; CHECK-LABEL: vsrl_vx_nxv4i32:
366; CHECK:       # %bb.0:
367; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
368; CHECK-NEXT:    vsrl.vx v8, v8, a0
369; CHECK-NEXT:    ret
370  %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
371  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
372  %vc = lshr <vscale x 4 x i32> %va, %splat
373  ret <vscale x 4 x i32> %vc
374}
375
376define <vscale x 4 x i32> @vsrl_vx_nxv4i32_0(<vscale x 4 x i32> %va) {
377; CHECK-LABEL: vsrl_vx_nxv4i32_0:
378; CHECK:       # %bb.0:
379; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
380; CHECK-NEXT:    vsrl.vi v8, v8, 31
381; CHECK-NEXT:    ret
382  %head = insertelement <vscale x 4 x i32> undef, i32 31, i32 0
383  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
384  %vc = lshr <vscale x 4 x i32> %va, %splat
385  ret <vscale x 4 x i32> %vc
386}
387
388define <vscale x 8 x i32> @vsrl_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
389; CHECK-LABEL: vsrl_vx_nxv8i32:
390; CHECK:       # %bb.0:
391; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
392; CHECK-NEXT:    vsrl.vx v8, v8, a0
393; CHECK-NEXT:    ret
394  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
395  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
396  %vc = lshr <vscale x 8 x i32> %va, %splat
397  ret <vscale x 8 x i32> %vc
398}
399
400define <vscale x 8 x i32> @vsrl_vx_nxv8i32_0(<vscale x 8 x i32> %va) {
401; CHECK-LABEL: vsrl_vx_nxv8i32_0:
402; CHECK:       # %bb.0:
403; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
404; CHECK-NEXT:    vsrl.vi v8, v8, 31
405; CHECK-NEXT:    ret
406  %head = insertelement <vscale x 8 x i32> undef, i32 31, i32 0
407  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
408  %vc = lshr <vscale x 8 x i32> %va, %splat
409  ret <vscale x 8 x i32> %vc
410}
411
412define <vscale x 16 x i32> @vsrl_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b) {
413; CHECK-LABEL: vsrl_vx_nxv16i32:
414; CHECK:       # %bb.0:
415; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
416; CHECK-NEXT:    vsrl.vx v8, v8, a0
417; CHECK-NEXT:    ret
418  %head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
419  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
420  %vc = lshr <vscale x 16 x i32> %va, %splat
421  ret <vscale x 16 x i32> %vc
422}
423
424define <vscale x 16 x i32> @vsrl_vx_nxv16i32_0(<vscale x 16 x i32> %va) {
425; CHECK-LABEL: vsrl_vx_nxv16i32_0:
426; CHECK:       # %bb.0:
427; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
428; CHECK-NEXT:    vsrl.vi v8, v8, 31
429; CHECK-NEXT:    ret
430  %head = insertelement <vscale x 16 x i32> undef, i32 31, i32 0
431  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
432  %vc = lshr <vscale x 16 x i32> %va, %splat
433  ret <vscale x 16 x i32> %vc
434}
435
436define <vscale x 1 x i64> @vsrl_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
437; CHECK-LABEL: vsrl_vx_nxv1i64:
438; CHECK:       # %bb.0:
439; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
440; CHECK-NEXT:    vsrl.vx v8, v8, a0
441; CHECK-NEXT:    ret
442  %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
443  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
444  %vc = lshr <vscale x 1 x i64> %va, %splat
445  ret <vscale x 1 x i64> %vc
446}
447
448define <vscale x 1 x i64> @vsrl_vx_nxv1i64_0(<vscale x 1 x i64> %va) {
449; CHECK-LABEL: vsrl_vx_nxv1i64_0:
450; CHECK:       # %bb.0:
451; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
452; CHECK-NEXT:    vsrl.vi v8, v8, 31
453; CHECK-NEXT:    ret
454  %head = insertelement <vscale x 1 x i64> undef, i64 31, i32 0
455  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
456  %vc = lshr <vscale x 1 x i64> %va, %splat
457  ret <vscale x 1 x i64> %vc
458}
459
460define <vscale x 1 x i64> @vsrl_vx_nxv1i64_1(<vscale x 1 x i64> %va) {
461; CHECK-LABEL: vsrl_vx_nxv1i64_1:
462; CHECK:       # %bb.0:
463; CHECK-NEXT:    addi a0, zero, 32
464; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
465; CHECK-NEXT:    vsrl.vx v8, v8, a0
466; CHECK-NEXT:    ret
467  %head = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
468  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
469  %vc = lshr <vscale x 1 x i64> %va, %splat
470  ret <vscale x 1 x i64> %vc
471}
472
473define <vscale x 2 x i64> @vsrl_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
474; CHECK-LABEL: vsrl_vx_nxv2i64:
475; CHECK:       # %bb.0:
476; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
477; CHECK-NEXT:    vsrl.vx v8, v8, a0
478; CHECK-NEXT:    ret
479  %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
480  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
481  %vc = lshr <vscale x 2 x i64> %va, %splat
482  ret <vscale x 2 x i64> %vc
483}
484
485define <vscale x 2 x i64> @vsrl_vx_nxv2i64_0(<vscale x 2 x i64> %va) {
486; CHECK-LABEL: vsrl_vx_nxv2i64_0:
487; CHECK:       # %bb.0:
488; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
489; CHECK-NEXT:    vsrl.vi v8, v8, 31
490; CHECK-NEXT:    ret
491  %head = insertelement <vscale x 2 x i64> undef, i64 31, i32 0
492  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
493  %vc = lshr <vscale x 2 x i64> %va, %splat
494  ret <vscale x 2 x i64> %vc
495}
496
497define <vscale x 2 x i64> @vsrl_vx_nxv2i64_1(<vscale x 2 x i64> %va) {
498; CHECK-LABEL: vsrl_vx_nxv2i64_1:
499; CHECK:       # %bb.0:
500; CHECK-NEXT:    addi a0, zero, 32
501; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
502; CHECK-NEXT:    vsrl.vx v8, v8, a0
503; CHECK-NEXT:    ret
504  %head = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
505  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
506  %vc = lshr <vscale x 2 x i64> %va, %splat
507  ret <vscale x 2 x i64> %vc
508}
509
510define <vscale x 4 x i64> @vsrl_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
511; CHECK-LABEL: vsrl_vx_nxv4i64:
512; CHECK:       # %bb.0:
513; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
514; CHECK-NEXT:    vsrl.vx v8, v8, a0
515; CHECK-NEXT:    ret
516  %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
517  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
518  %vc = lshr <vscale x 4 x i64> %va, %splat
519  ret <vscale x 4 x i64> %vc
520}
521
522define <vscale x 4 x i64> @vsrl_vx_nxv4i64_0(<vscale x 4 x i64> %va) {
523; CHECK-LABEL: vsrl_vx_nxv4i64_0:
524; CHECK:       # %bb.0:
525; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
526; CHECK-NEXT:    vsrl.vi v8, v8, 31
527; CHECK-NEXT:    ret
528  %head = insertelement <vscale x 4 x i64> undef, i64 31, i32 0
529  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
530  %vc = lshr <vscale x 4 x i64> %va, %splat
531  ret <vscale x 4 x i64> %vc
532}
533
534define <vscale x 4 x i64> @vsrl_vx_nxv4i64_1(<vscale x 4 x i64> %va) {
535; CHECK-LABEL: vsrl_vx_nxv4i64_1:
536; CHECK:       # %bb.0:
537; CHECK-NEXT:    addi a0, zero, 32
538; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
539; CHECK-NEXT:    vsrl.vx v8, v8, a0
540; CHECK-NEXT:    ret
541  %head = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
542  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
543  %vc = lshr <vscale x 4 x i64> %va, %splat
544  ret <vscale x 4 x i64> %vc
545}
546
547define <vscale x 8 x i64> @vsrl_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
548; CHECK-LABEL: vsrl_vx_nxv8i64:
549; CHECK:       # %bb.0:
550; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
551; CHECK-NEXT:    vsrl.vx v8, v8, a0
552; CHECK-NEXT:    ret
553  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
554  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
555  %vc = lshr <vscale x 8 x i64> %va, %splat
556  ret <vscale x 8 x i64> %vc
557}
558
559define <vscale x 8 x i64> @vsrl_vx_nxv8i64_0(<vscale x 8 x i64> %va) {
560; CHECK-LABEL: vsrl_vx_nxv8i64_0:
561; CHECK:       # %bb.0:
562; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
563; CHECK-NEXT:    vsrl.vi v8, v8, 31
564; CHECK-NEXT:    ret
565  %head = insertelement <vscale x 8 x i64> undef, i64 31, i32 0
566  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
567  %vc = lshr <vscale x 8 x i64> %va, %splat
568  ret <vscale x 8 x i64> %vc
569}
570
571define <vscale x 8 x i64> @vsrl_vx_nxv8i64_1(<vscale x 8 x i64> %va) {
572; CHECK-LABEL: vsrl_vx_nxv8i64_1:
573; CHECK:       # %bb.0:
574; CHECK-NEXT:    addi a0, zero, 32
575; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
576; CHECK-NEXT:    vsrl.vx v8, v8, a0
577; CHECK-NEXT:    ret
578  %head = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
579  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
580  %vc = lshr <vscale x 8 x i64> %va, %splat
581  ret <vscale x 8 x i64> %vc
582}
583
584