1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py 2# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M3 3# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M4 4# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m5 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M5 5 6ld2 {v0.s, v1.s}[0], [sp] 7ld2r {v0.2s, v1.2s}, [sp] 8ld2 {v0.2s, v1.2s}, [sp] 9 10ld2 {v0.d, v1.d}[0], [sp] 11ld2r {v0.2d, v1.2d}, [sp] 12ld2 {v0.2d, v1.2d}, [sp] 13 14ld2 {v0.s, v1.s}[0], [sp], #8 15ld2r {v0.2s, v1.2s}, [sp], #8 16ld2 {v0.2s, v1.2s}, [sp], #16 17 18ld2 {v0.d, v1.d}[0], [sp], #16 19ld2r {v0.2d, v1.2d}, [sp], #16 20ld2 {v0.2d, v1.2d}, [sp], #32 21 22ld2 {v0.s, v1.s}[0], [sp], x0 23ld2r {v0.2s, v1.2s}, [sp], x0 24ld2 {v0.2s, v1.2s}, [sp], x0 25 26ld2 {v0.d, v1.d}[0], [sp], x0 27ld2r {v0.2d, v1.2d}, [sp], x0 28ld2 {v0.2d, v1.2d}, [sp], x0 29 30# ALL: Iterations: 100 31# ALL-NEXT: Instructions: 1800 32 33# M3-NEXT: Total Cycles: 10003 34# M4-NEXT: Total Cycles: 9803 35# M5-NEXT: Total Cycles: 11103 36 37# ALL-NEXT: Total uOps: 5400 38 39# ALL: Dispatch Width: 6 40 41# M3-NEXT: uOps Per Cycle: 0.54 42# M3-NEXT: IPC: 0.18 43# M3-NEXT: Block RThroughput: 42.0 44 45# M4-NEXT: uOps Per Cycle: 0.55 46# M4-NEXT: IPC: 0.18 47# M4-NEXT: Block RThroughput: 30.0 48 49# M5-NEXT: uOps Per Cycle: 0.49 50# M5-NEXT: IPC: 0.16 51# M5-NEXT: Block RThroughput: 45.0 52 53# ALL: Instruction Info: 54# ALL-NEXT: [1]: #uOps 55# ALL-NEXT: [2]: Latency 56# ALL-NEXT: [3]: RThroughput 57# ALL-NEXT: [4]: MayLoad 58# ALL-NEXT: [5]: MayStore 59# ALL-NEXT: [6]: HasSideEffects (U) 60 61# ALL: [1] [2] [3] [4] [5] [6] Instructions: 62 63# M3-NEXT: 3 7 1.00 * ld2 { v0.s, v1.s }[0], [sp] 64# M3-NEXT: 2 5 1.00 * ld2r { v0.2s, v1.2s }, [sp] 65# M3-NEXT: 2 10 5.00 * ld2 { v0.2s, v1.2s }, [sp] 66# M3-NEXT: 3 6 1.00 * ld2 { v0.d, v1.d }[0], [sp] 67# M3-NEXT: 2 5 1.00 * ld2r { v0.2d, v1.2d }, [sp] 68# M3-NEXT: 2 10 5.00 * ld2 { v0.2d, v1.2d }, [sp] 69# M3-NEXT: 4 7 1.00 * ld2 { v0.s, v1.s }[0], [sp], #8 70# M3-NEXT: 3 5 1.00 * ld2r { v0.2s, v1.2s }, [sp], #8 71# M3-NEXT: 3 10 5.00 * ld2 { v0.2s, v1.2s }, [sp], #16 72# M3-NEXT: 4 6 1.00 * ld2 { v0.d, v1.d }[0], [sp], #16 73# M3-NEXT: 3 5 1.00 * ld2r { v0.2d, v1.2d }, [sp], #16 74# M3-NEXT: 3 10 5.00 * ld2 { v0.2d, v1.2d }, [sp], #32 75# M3-NEXT: 4 7 1.00 * ld2 { v0.s, v1.s }[0], [sp], x0 76# M3-NEXT: 3 5 1.00 * ld2r { v0.2s, v1.2s }, [sp], x0 77# M3-NEXT: 3 10 5.00 * ld2 { v0.2s, v1.2s }, [sp], x0 78# M3-NEXT: 4 6 1.00 * ld2 { v0.d, v1.d }[0], [sp], x0 79# M3-NEXT: 3 5 1.00 * ld2r { v0.2d, v1.2d }, [sp], x0 80# M3-NEXT: 3 10 5.00 * ld2 { v0.2d, v1.2d }, [sp], x0 81 82# M4-NEXT: 3 6 1.00 * ld2 { v0.s, v1.s }[0], [sp] 83# M4-NEXT: 2 5 1.00 * ld2r { v0.2s, v1.2s }, [sp] 84# M4-NEXT: 2 10 3.00 * ld2 { v0.2s, v1.2s }, [sp] 85# M4-NEXT: 3 6 1.00 * ld2 { v0.d, v1.d }[0], [sp] 86# M4-NEXT: 2 5 1.00 * ld2r { v0.2d, v1.2d }, [sp] 87# M4-NEXT: 2 10 3.00 * ld2 { v0.2d, v1.2d }, [sp] 88# M4-NEXT: 4 6 1.00 * ld2 { v0.s, v1.s }[0], [sp], #8 89# M4-NEXT: 3 5 1.00 * ld2r { v0.2s, v1.2s }, [sp], #8 90# M4-NEXT: 3 10 3.00 * ld2 { v0.2s, v1.2s }, [sp], #16 91# M4-NEXT: 4 6 1.00 * ld2 { v0.d, v1.d }[0], [sp], #16 92# M4-NEXT: 3 5 1.00 * ld2r { v0.2d, v1.2d }, [sp], #16 93# M4-NEXT: 3 10 3.00 * ld2 { v0.2d, v1.2d }, [sp], #32 94# M4-NEXT: 4 6 1.00 * ld2 { v0.s, v1.s }[0], [sp], x0 95# M4-NEXT: 3 5 1.00 * ld2r { v0.2s, v1.2s }, [sp], x0 96# M4-NEXT: 3 10 3.00 * ld2 { v0.2s, v1.2s }, [sp], x0 97# M4-NEXT: 4 6 1.00 * ld2 { v0.d, v1.d }[0], [sp], x0 98# M4-NEXT: 3 5 1.00 * ld2r { v0.2d, v1.2d }, [sp], x0 99# M4-NEXT: 3 10 3.00 * ld2 { v0.2d, v1.2d }, [sp], x0 100 101# M5-NEXT: 3 7 1.00 * ld2 { v0.s, v1.s }[0], [sp] 102# M5-NEXT: 2 6 1.00 * ld2r { v0.2s, v1.2s }, [sp] 103# M5-NEXT: 2 11 5.50 * ld2 { v0.2s, v1.2s }, [sp] 104# M5-NEXT: 3 7 1.00 * ld2 { v0.d, v1.d }[0], [sp] 105# M5-NEXT: 2 6 1.00 * ld2r { v0.2d, v1.2d }, [sp] 106# M5-NEXT: 2 11 5.50 * ld2 { v0.2d, v1.2d }, [sp] 107# M5-NEXT: 4 7 1.00 * ld2 { v0.s, v1.s }[0], [sp], #8 108# M5-NEXT: 3 6 1.00 * ld2r { v0.2s, v1.2s }, [sp], #8 109# M5-NEXT: 3 11 5.50 * ld2 { v0.2s, v1.2s }, [sp], #16 110# M5-NEXT: 4 7 1.00 * ld2 { v0.d, v1.d }[0], [sp], #16 111# M5-NEXT: 3 6 1.00 * ld2r { v0.2d, v1.2d }, [sp], #16 112# M5-NEXT: 3 11 5.50 * ld2 { v0.2d, v1.2d }, [sp], #32 113# M5-NEXT: 4 7 1.00 * ld2 { v0.s, v1.s }[0], [sp], x0 114# M5-NEXT: 3 6 1.00 * ld2r { v0.2s, v1.2s }, [sp], x0 115# M5-NEXT: 3 11 5.50 * ld2 { v0.2s, v1.2s }, [sp], x0 116# M5-NEXT: 4 7 1.00 * ld2 { v0.d, v1.d }[0], [sp], x0 117# M5-NEXT: 3 6 1.00 * ld2r { v0.2d, v1.2d }, [sp], x0 118# M5-NEXT: 3 11 5.50 * ld2 { v0.2d, v1.2d }, [sp], x0 119