1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py 2# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 -resource-pressure=false -noalias=false < %s | FileCheck %s -check-prefixes=ALL,M3 3# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m4 -resource-pressure=false -noalias=false < %s | FileCheck %s -check-prefixes=ALL,M4 4# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m5 -resource-pressure=false -noalias=false < %s | FileCheck %s -check-prefixes=ALL,M5 5 6st3 {v0.s, v1.s, v2.s}[0], [sp] 7st3 {v0.2s, v1.2s, v2.2s}, [sp] 8 9st3 {v0.d, v1.d, v2.d}[0], [sp] 10st3 {v0.2d, v1.2d, v2.2d}, [sp] 11 12st3 {v0.s, v1.s, v2.s}[0], [sp], #12 13st3 {v0.2s, v1.2s, v2.2s}, [sp], #24 14 15st3 {v0.d, v1.d, v2.d}[0], [sp], #24 16st3 {v0.2d, v1.2d, v2.2d}, [sp], #48 17 18st3 {v0.s, v1.s, v2.s}[0], [sp], x0 19st3 {v0.2s, v1.2s, v2.2s}, [sp], x0 20 21st3 {v0.d, v1.d, v2.d}[0], [sp], x0 22st3 {v0.2d, v1.2d, v2.2d}, [sp], x0 23 24# ALL: Iterations: 100 25# ALL-NEXT: Instructions: 1200 26 27# M3-NEXT: Total Cycles: 18003 28# M3-NEXT: Total uOps: 8400 29 30# M4-NEXT: Total Cycles: 3903 31# M4-NEXT: Total uOps: 5000 32 33# M5-NEXT: Total Cycles: 3603 34# M5-NEXT: Total uOps: 4400 35 36# ALL: Dispatch Width: 6 37 38# M3-NEXT: uOps Per Cycle: 0.47 39# M3-NEXT: IPC: 0.07 40# M3-NEXT: Block RThroughput: 72.0 41 42# M4-NEXT: uOps Per Cycle: 1.28 43# M4-NEXT: IPC: 0.31 44# M4-NEXT: Block RThroughput: 21.0 45 46# M5-NEXT: uOps Per Cycle: 1.22 47# M5-NEXT: IPC: 0.33 48# M5-NEXT: Block RThroughput: 10.5 49 50# ALL: Instruction Info: 51# ALL-NEXT: [1]: #uOps 52# ALL-NEXT: [2]: Latency 53# ALL-NEXT: [3]: RThroughput 54# ALL-NEXT: [4]: MayLoad 55# ALL-NEXT: [5]: MayStore 56# ALL-NEXT: [6]: HasSideEffects (U) 57 58# ALL: [1] [2] [3] [4] [5] [6] Instructions: 59 60# M3-NEXT: 5 14 4.50 * st3 { v0.s, v1.s, v2.s }[0], [sp] 61# M3-NEXT: 7 15 6.00 * st3 { v0.2s, v1.2s, v2.2s }, [sp] 62# M3-NEXT: 7 15 6.00 * st3 { v0.d, v1.d, v2.d }[0], [sp] 63# M3-NEXT: 9 16 7.50 * st3 { v0.2d, v1.2d, v2.2d }, [sp] 64# M3-NEXT: 5 14 4.50 * st3 { v0.s, v1.s, v2.s }[0], [sp], #12 65# M3-NEXT: 7 15 6.00 * st3 { v0.2s, v1.2s, v2.2s }, [sp], #24 66# M3-NEXT: 7 15 6.00 * st3 { v0.d, v1.d, v2.d }[0], [sp], #24 67# M3-NEXT: 9 16 7.50 * st3 { v0.2d, v1.2d, v2.2d }, [sp], #48 68# M3-NEXT: 5 14 4.50 * st3 { v0.s, v1.s, v2.s }[0], [sp], x0 69# M3-NEXT: 7 15 6.00 * st3 { v0.2s, v1.2s, v2.2s }, [sp], x0 70# M3-NEXT: 7 15 6.00 * st3 { v0.d, v1.d, v2.d }[0], [sp], x0 71# M3-NEXT: 9 16 7.50 * st3 { v0.2d, v1.2d, v2.2d }, [sp], x0 72 73# M4-NEXT: 2 2 1.00 * st3 { v0.s, v1.s, v2.s }[0], [sp] 74# M4-NEXT: 4 4 2.00 * st3 { v0.2s, v1.2s, v2.2s }, [sp] 75# M4-NEXT: 2 2 1.00 * st3 { v0.d, v1.d, v2.d }[0], [sp] 76# M4-NEXT: 6 5 3.00 * st3 { v0.2d, v1.2d, v2.2d }, [sp] 77# M4-NEXT: 3 2 1.00 * st3 { v0.s, v1.s, v2.s }[0], [sp], #12 78# M4-NEXT: 5 4 2.00 * st3 { v0.2s, v1.2s, v2.2s }, [sp], #24 79# M4-NEXT: 3 2 1.00 * st3 { v0.d, v1.d, v2.d }[0], [sp], #24 80# M4-NEXT: 7 5 3.00 * st3 { v0.2d, v1.2d, v2.2d }, [sp], #48 81# M4-NEXT: 3 2 1.00 * st3 { v0.s, v1.s, v2.s }[0], [sp], x0 82# M4-NEXT: 5 4 2.00 * st3 { v0.2s, v1.2s, v2.2s }, [sp], x0 83# M4-NEXT: 3 2 1.00 * st3 { v0.d, v1.d, v2.d }[0], [sp], x0 84# M4-NEXT: 7 5 3.00 * st3 { v0.2d, v1.2d, v2.2d }, [sp], x0 85 86# M5-NEXT: 2 2 1.00 * st3 { v0.s, v1.s, v2.s }[0], [sp] 87# M5-NEXT: 3 4 1.00 * st3 { v0.2s, v1.2s, v2.2s }, [sp] 88# M5-NEXT: 2 2 1.00 * st3 { v0.d, v1.d, v2.d }[0], [sp] 89# M5-NEXT: 5 4 1.50 * st3 { v0.2d, v1.2d, v2.2d }, [sp] 90# M5-NEXT: 3 2 1.00 * st3 { v0.s, v1.s, v2.s }[0], [sp], #12 91# M5-NEXT: 4 4 1.00 * st3 { v0.2s, v1.2s, v2.2s }, [sp], #24 92# M5-NEXT: 3 2 1.00 * st3 { v0.d, v1.d, v2.d }[0], [sp], #24 93# M5-NEXT: 6 4 1.50 * st3 { v0.2d, v1.2d, v2.2d }, [sp], #48 94# M5-NEXT: 3 2 1.00 * st3 { v0.s, v1.s, v2.s }[0], [sp], x0 95# M5-NEXT: 4 4 1.00 * st3 { v0.2s, v1.2s, v2.2s }, [sp], x0 96# M5-NEXT: 3 2 1.00 * st3 { v0.d, v1.d, v2.d }[0], [sp], x0 97# M5-NEXT: 6 4 1.50 * st3 { v0.2d, v1.2d, v2.2d }, [sp], x0 98