1 /* Opcode table header for m680[01234]0/m6888[12]/m68851. 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001, 3 2003 Free Software Foundation, Inc. 4 5 This file is part of GDB, GAS, and the GNU binutils. 6 7 GDB, GAS, and the GNU binutils are free software; you can redistribute 8 them and/or modify them under the terms of the GNU General Public 9 License as published by the Free Software Foundation; either version 10 1, or (at your option) any later version. 11 12 GDB, GAS, and the GNU binutils are distributed in the hope that they 13 will be useful, but WITHOUT ANY WARRANTY; without even the implied 14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 15 the GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this file; see the file COPYING. If not, write to the Free 19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 20 02111-1307, USA. */ 21 22 /* These are used as bit flags for the arch field in the m68k_opcode 23 structure. */ 24 #define _m68k_undef 0 25 #define m68000 0x001 26 #define m68008 m68000 /* Synonym for -m68000. otherwise unused. */ 27 #define m68010 0x002 28 #define m68020 0x004 29 #define m68030 0x008 30 #define m68ec030 m68030 /* Similar enough to -m68030 to ignore differences; 31 gas will deal with the few differences. */ 32 #define m68040 0x010 33 /* There is no 68050. */ 34 #define m68060 0x020 35 #define m68881 0x040 36 #define m68882 m68881 /* Synonym for -m68881. otherwise unused. */ 37 #define m68851 0x080 38 #define cpu32 0x100 /* e.g., 68332 */ 39 #define mcf5200 0x200 40 #define mcf5206e 0x400 41 #define mcf5307 0x800 42 #define mcf5407 0x1000 43 #define mcfv4e 0x2000 44 #define mcf528x 0x4000 45 46 /* Handy aliases. */ 47 #define m68040up (m68040 | m68060) 48 #define m68030up (m68030 | m68040up) 49 #define m68020up (m68020 | m68030up) 50 #define m68010up (m68010 | cpu32 | m68020up) 51 #define m68000up (m68000 | m68010up) 52 #define mcf (mcf5200 | mcf5206e | mcf528x | mcf5307 | mcf5407 | mcfv4e) 53 #define mcf5206eup (mcf5206e | mcf528x | mcf5307 | mcf5407 | mcfv4e) 54 #define mcf5307up (mcf5307 | mcf5407 | mcfv4e) 55 #define mcfv4up (mcf5407 | mcfv4e) 56 #define mcfv4eup (mcfv4e) 57 58 #define cfloat (mcfv4e) 59 #define mfloat (m68881 | m68882 | m68040 | m68060) 60 #define mmmu (m68851 | m68030 | m68040 | m68060) 61 62 /* The structure used to hold information for an opcode. */ 63 64 struct m68k_opcode 65 { 66 /* The opcode name. */ 67 const char *name; 68 /* The opcode itself. */ 69 unsigned long opcode; 70 /* The mask used by the disassembler. */ 71 unsigned long match; 72 /* The arguments. */ 73 const char *args; 74 /* The architectures which support this opcode. */ 75 unsigned int arch; 76 }; 77 78 /* The structure used to hold information for an opcode alias. */ 79 80 struct m68k_opcode_alias 81 { 82 /* The alias name. */ 83 const char *alias; 84 /* The instruction for which this is an alias. */ 85 const char *primary; 86 }; 87 88 /* We store four bytes of opcode for all opcodes because that is the 89 most any of them need. The actual length of an instruction is 90 always at least 2 bytes, and is as much longer as necessary to hold 91 the operands it has. 92 93 The match field is a mask saying which bits must match particular 94 opcode in order for an instruction to be an instance of that 95 opcode. 96 97 The args field is a string containing two characters for each 98 operand of the instruction. The first specifies the kind of 99 operand; the second, the place it is stored. */ 100 101 /* Kinds of operands: 102 Characters used: AaBbCcDdEFfGHIJkLlMmnOopQqRrSsTtU VvWwXxYyZz0123|*~%;@!&$?/<>#^+- 103 104 D data register only. Stored as 3 bits. 105 A address register only. Stored as 3 bits. 106 a address register indirect only. Stored as 3 bits. 107 R either kind of register. Stored as 4 bits. 108 r either kind of register indirect only. Stored as 4 bits. 109 At the moment, used only for cas2 instruction. 110 F floating point coprocessor register only. Stored as 3 bits. 111 O an offset (or width): immediate data 0-31 or data register. 112 Stored as 6 bits in special format for BF... insns. 113 + autoincrement only. Stored as 3 bits (number of the address register). 114 - autodecrement only. Stored as 3 bits (number of the address register). 115 Q quick immediate data. Stored as 3 bits. 116 This matches an immediate operand only when value is in range 1 .. 8. 117 M moveq immediate data. Stored as 8 bits. 118 This matches an immediate operand only when value is in range -128..127 119 T trap vector immediate data. Stored as 4 bits. 120 121 k K-factor for fmove.p instruction. Stored as a 7-bit constant or 122 a three bit register offset, depending on the field type. 123 124 # immediate data. Stored in special places (b, w or l) 125 which say how many bits to store. 126 ^ immediate data for floating point instructions. Special places 127 are offset by 2 bytes from '#'... 128 B pc-relative address, converted to an offset 129 that is treated as immediate data. 130 d displacement and register. Stores the register as 3 bits 131 and stores the displacement in the entire second word. 132 133 C the CCR. No need to store it; this is just for filtering validity. 134 S the SR. No need to store, just as with CCR. 135 U the USP. No need to store, just as with CCR. 136 E the ACC. No need to store, just as with CCR. 137 G the MACSR. No need to store, just as with CCR. 138 H the MASK. No need to store, just as with CCR. 139 140 I Coprocessor ID. Not printed if 1. The Coprocessor ID is always 141 extracted from the 'd' field of word one, which means that an extended 142 coprocessor opcode can be skipped using the 'i' place, if needed. 143 144 s System Control register for the floating point coprocessor. 145 146 J Misc register for movec instruction, stored in 'j' format. 147 Possible values: 148 0x000 SFC Source Function Code reg [60, 40, 30, 20, 10] 149 0x001 DFC Data Function Code reg [60, 40, 30, 20, 10] 150 0x002 CACR Cache Control Register [60, 40, 30, 20, mcf] 151 0x003 TC MMU Translation Control [60, 40] 152 0x004 ITT0 Instruction Transparent 153 Translation reg 0 [60, 40] 154 0x005 ITT1 Instruction Transparent 155 Translation reg 1 [60, 40] 156 0x006 DTT0 Data Transparent 157 Translation reg 0 [60, 40] 158 0x007 DTT1 Data Transparent 159 Translation reg 1 [60, 40] 160 0x008 BUSCR Bus Control Register [60] 161 0x800 USP User Stack Pointer [60, 40, 30, 20, 10] 162 0x801 VBR Vector Base reg [60, 40, 30, 20, 10, mcf] 163 0x802 CAAR Cache Address Register [ 30, 20] 164 0x803 MSP Master Stack Pointer [ 40, 30, 20] 165 0x804 ISP Interrupt Stack Pointer [ 40, 30, 20] 166 0x805 MMUSR MMU Status reg [ 40] 167 0x806 URP User Root Pointer [60, 40] 168 0x807 SRP Supervisor Root Pointer [60, 40] 169 0x808 PCR Processor Configuration reg [60] 170 0xC00 ROMBAR ROM Base Address Register [520X] 171 0xC04 RAMBAR0 RAM Base Address Register 0 [520X] 172 0xC05 RAMBAR1 RAM Base Address Register 0 [520X] 173 0xC0F MBAR0 RAM Base Address Register 0 [520X] 174 0xC04 FLASHBAR FLASH Base Address Register [mcf528x] 175 0xC05 RAMBAR Static RAM Base Address Register [mcf528x] 176 177 L Register list of the type d0-d7/a0-a7 etc. 178 (New! Improved! Can also hold fp0-fp7, as well!) 179 The assembler tries to see if the registers match the insn by 180 looking at where the insn wants them stored. 181 182 l Register list like L, but with all the bits reversed. 183 Used for going the other way. . . 184 185 c cache identifier which may be "nc" for no cache, "ic" 186 for instruction cache, "dc" for data cache, or "bc" 187 for both caches. Used in cinv and cpush. Always 188 stored in position "d". 189 190 u Any register, with ``upper'' or ``lower'' specification. Used 191 in the mac instructions with size word. 192 193 The remainder are all stored as 6 bits using an address mode and a 194 register number; they differ in which addressing modes they match. 195 196 * all (modes 0-6,7.0-4) 197 ~ alterable memory (modes 2-6,7.0,7.1) 198 (not 0,1,7.2-4) 199 % alterable (modes 0-6,7.0,7.1) 200 (not 7.2-4) 201 ; data (modes 0,2-6,7.0-4) 202 (not 1) 203 @ data, but not immediate (modes 0,2-6,7.0-3) 204 (not 1,7.4) 205 ! control (modes 2,5,6,7.0-3) 206 (not 0,1,3,4,7.4) 207 & alterable control (modes 2,5,6,7.0,7.1) 208 (not 0,1,7.2-4) 209 $ alterable data (modes 0,2-6,7.0,7.1) 210 (not 1,7.2-4) 211 ? alterable control, or data register (modes 0,2,5,6,7.0,7.1) 212 (not 1,3,4,7.2-4) 213 / control, or data register (modes 0,2,5,6,7.0-3) 214 (not 1,3,4,7.4) 215 > *save operands (modes 2,4,5,6,7.0,7.1) 216 (not 0,1,3,7.2-4) 217 < *restore operands (modes 2,3,5,6,7.0-3) 218 (not 0,1,4,7.4) 219 220 coldfire move operands: 221 m (modes 0-4) 222 n (modes 5,7.2) 223 o (modes 6,7.0,7.1,7.3,7.4) 224 p (modes 0-5) 225 226 coldfire bset/bclr/btst/mulsl/mulul operands: 227 q (modes 0,2-5) 228 v (modes 0,2-5,7.0,7.1) 229 b (modes 0,2-5,7.2) 230 w (modes 2-5,7.2) 231 y (modes 2,5) 232 z (modes 2,5,7.2) 233 x mov3q immediate operand. */ 234 235 /* For the 68851: */ 236 /* I didn't use much imagination in choosing the 237 following codes, so many of them aren't very 238 mnemonic. -rab 239 240 0 32 bit pmmu register 241 Possible values: 242 000 TC Translation Control Register (68030, 68851) 243 244 1 16 bit pmmu register 245 111 AC Access Control (68851) 246 247 2 8 bit pmmu register 248 100 CAL Current Access Level (68851) 249 101 VAL Validate Access Level (68851) 250 110 SCC Stack Change Control (68851) 251 252 3 68030-only pmmu registers (32 bit) 253 010 TT0 Transparent Translation reg 0 254 (aka Access Control reg 0 -- AC0 -- on 68ec030) 255 011 TT1 Transparent Translation reg 1 256 (aka Access Control reg 1 -- AC1 -- on 68ec030) 257 258 W wide pmmu registers 259 Possible values: 260 001 DRP Dma Root Pointer (68851) 261 010 SRP Supervisor Root Pointer (68030, 68851) 262 011 CRP Cpu Root Pointer (68030, 68851) 263 264 f function code register (68030, 68851) 265 0 SFC 266 1 DFC 267 268 V VAL register only (68851) 269 270 X BADx, BACx (16 bit) 271 100 BAD Breakpoint Acknowledge Data (68851) 272 101 BAC Breakpoint Acknowledge Control (68851) 273 274 Y PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030) 275 Z PCSR (68851) 276 277 | memory (modes 2-6, 7.*) 278 279 t address test level (68030 only) 280 Stored as 3 bits, range 0-7. 281 Also used for breakpoint instruction now. 282 283 */ 284 285 /* Places to put an operand, for non-general operands: 286 Characters used: BbCcDdghijkLlMmNnostWw123456789 287 288 s source, low bits of first word. 289 d dest, shifted 9 in first word 290 1 second word, shifted 12 291 2 second word, shifted 6 292 3 second word, shifted 0 293 4 third word, shifted 12 294 5 third word, shifted 6 295 6 third word, shifted 0 296 7 second word, shifted 7 297 8 second word, shifted 10 298 9 second word, shifted 5 299 D store in both place 1 and place 3; for divul and divsl. 300 B first word, low byte, for branch displacements 301 W second word (entire), for branch displacements 302 L second and third words (entire), for branch displacements 303 (also overloaded for move16) 304 b second word, low byte 305 w second word (entire) [variable word/long branch offset for dbra] 306 W second word (entire) (must be signed 16 bit value) 307 l second and third word (entire) 308 g variable branch offset for bra and similar instructions. 309 The place to store depends on the magnitude of offset. 310 t store in both place 7 and place 8; for floating point operations 311 c branch offset for cpBcc operations. 312 The place to store is word two if bit six of word one is zero, 313 and words two and three if bit six of word one is one. 314 i Increment by two, to skip over coprocessor extended operands. Only 315 works with the 'I' format. 316 k Dynamic K-factor field. Bits 6-4 of word 2, used as a register number. 317 Also used for dynamic fmovem instruction. 318 C floating point coprocessor constant - 7 bits. Also used for static 319 K-factors... 320 j Movec register #, stored in 12 low bits of second word. 321 m For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word 322 and remaining 3 bits of register shifted 9 bits in first word. 323 Indicate upper/lower in 1 bit shifted 7 bits in second word. 324 Use with `R' or `u' format. 325 n `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split 326 with MSB shifted 6 bits in first word and remaining 3 bits of 327 register shifted 9 bits in first word. No upper/lower 328 indication is done.) Use with `R' or `u' format. 329 o For M[S]ACw; 4 bits shifted 12 in second word (like `1'). 330 Indicate upper/lower in 1 bit shifted 7 bits in second word. 331 Use with `R' or `u' format. 332 M For M[S]ACw; 4 bits in low bits of first word. Indicate 333 upper/lower in 1 bit shifted 6 bits in second word. Use with 334 `R' or `u' format. 335 N For M[S]ACw; 4 bits in low bits of second word. Indicate 336 upper/lower in 1 bit shifted 6 bits in second word. Use with 337 `R' or `u' format. 338 h shift indicator (scale factor), 1 bit shifted 10 in second word 339 340 Places to put operand, for general operands: 341 d destination, shifted 6 bits in first word 342 b source, at low bit of first word, and immediate uses one byte 343 w source, at low bit of first word, and immediate uses two bytes 344 l source, at low bit of first word, and immediate uses four bytes 345 s source, at low bit of first word. 346 Used sometimes in contexts where immediate is not allowed anyway. 347 f single precision float, low bit of 1st word, immediate uses 4 bytes 348 F double precision float, low bit of 1st word, immediate uses 8 bytes 349 x extended precision float, low bit of 1st word, immediate uses 12 bytes 350 p packed float, low bit of 1st word, immediate uses 12 bytes 351 */ 352 353 extern const struct m68k_opcode m68k_opcodes[]; 354 extern const struct m68k_opcode_alias m68k_opcode_aliases[]; 355 356 extern const int m68k_numopcodes, m68k_numaliases; 357 358 /* end of m68k-opcode.h */ 359