1 /* Definitions of target machine for GNU compiler, for the HP Spectrum. 2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3 2001, 2002, 2003, 2004 Free Software Foundation, Inc. 4 Contributed by Michael Tiemann (tiemann@cygnus.com) of Cygnus Support 5 and Tim Moore (moore@defmacro.cs.utah.edu) of the Center for 6 Software Science at the University of Utah. 7 8 This file is part of GCC. 9 10 GCC is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 2, or (at your option) 13 any later version. 14 15 GCC is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with GCC; see the file COPYING. If not, write to 22 the Free Software Foundation, 59 Temple Place - Suite 330, 23 Boston, MA 02111-1307, USA. */ 24 25 enum cmp_type /* comparison type */ 26 { 27 CMP_SI, /* compare integers */ 28 CMP_SF, /* compare single precision floats */ 29 CMP_DF, /* compare double precision floats */ 30 CMP_MAX /* max comparison type */ 31 }; 32 33 /* For long call handling. */ 34 extern unsigned long total_code_bytes; 35 36 /* Which processor to schedule for. */ 37 38 enum processor_type 39 { 40 PROCESSOR_700, 41 PROCESSOR_7100, 42 PROCESSOR_7100LC, 43 PROCESSOR_7200, 44 PROCESSOR_7300, 45 PROCESSOR_8000 46 }; 47 48 /* For -mschedule= option. */ 49 extern const char *pa_cpu_string; 50 extern enum processor_type pa_cpu; 51 52 #define pa_cpu_attr ((enum attr_cpu)pa_cpu) 53 54 /* Which architecture to generate code for. */ 55 56 enum architecture_type 57 { 58 ARCHITECTURE_10, 59 ARCHITECTURE_11, 60 ARCHITECTURE_20 61 }; 62 63 struct rtx_def; 64 65 /* For -march= option. */ 66 extern const char *pa_arch_string; 67 extern enum architecture_type pa_arch; 68 69 /* Print subsidiary information on the compiler version in use. */ 70 71 #define TARGET_VERSION fputs (" (hppa)", stderr); 72 73 /* Run-time compilation parameters selecting different hardware subsets. */ 74 75 extern int target_flags; 76 77 /* compile code for HP-PA 1.1 ("Snake"). */ 78 79 #define MASK_PA_11 1 80 81 /* Disable all FP registers (they all become fixed). This may be necessary 82 for compiling kernels which perform lazy context switching of FP regs. 83 Note if you use this option and try to perform floating point operations 84 the compiler will abort! */ 85 86 #define MASK_DISABLE_FPREGS 2 87 #define TARGET_DISABLE_FPREGS (target_flags & MASK_DISABLE_FPREGS) 88 89 /* Generate code which assumes that all space register are equivalent. 90 Triggers aggressive unscaled index addressing and faster 91 builtin_return_address. */ 92 #define MASK_NO_SPACE_REGS 4 93 #define TARGET_NO_SPACE_REGS (target_flags & MASK_NO_SPACE_REGS) 94 95 /* Allow unconditional jumps in the delay slots of call instructions. */ 96 #define MASK_JUMP_IN_DELAY 8 97 #define TARGET_JUMP_IN_DELAY (target_flags & MASK_JUMP_IN_DELAY) 98 99 /* Disable indexed addressing modes. */ 100 #define MASK_DISABLE_INDEXING 32 101 #define TARGET_DISABLE_INDEXING (target_flags & MASK_DISABLE_INDEXING) 102 103 /* Emit code which follows the new portable runtime calling conventions 104 HP wants everyone to use for ELF objects. If at all possible you want 105 to avoid this since it's a performance loss for non-prototyped code. 106 107 Note TARGET_PORTABLE_RUNTIME also forces all calls to use inline 108 long-call stubs which is quite expensive. */ 109 #define MASK_PORTABLE_RUNTIME 64 110 #define TARGET_PORTABLE_RUNTIME (target_flags & MASK_PORTABLE_RUNTIME) 111 112 /* Emit directives only understood by GAS. This allows parameter 113 relocations to work for static functions. There is no way 114 to make them work the HP assembler at this time. */ 115 #define MASK_GAS 128 116 #define TARGET_GAS (target_flags & MASK_GAS) 117 118 /* Emit code for processors which do not have an FPU. */ 119 #define MASK_SOFT_FLOAT 256 120 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT) 121 122 /* Use 3-insn load/store sequences for access to large data segments 123 in shared libraries on hpux10. */ 124 #define MASK_LONG_LOAD_STORE 512 125 #define TARGET_LONG_LOAD_STORE (target_flags & MASK_LONG_LOAD_STORE) 126 127 /* Use a faster sequence for indirect calls. This assumes that calls 128 through function pointers will never cross a space boundary, and 129 that the executable is not dynamically linked. Such assumptions 130 are generally safe for building kernels and statically linked 131 executables. Code compiled with this option will fail miserably if 132 the executable is dynamically linked or uses nested functions! */ 133 #define MASK_FAST_INDIRECT_CALLS 1024 134 #define TARGET_FAST_INDIRECT_CALLS (target_flags & MASK_FAST_INDIRECT_CALLS) 135 136 /* Generate code with big switch statements to avoid out of range branches 137 occurring within the switch table. */ 138 #define MASK_BIG_SWITCH 2048 139 #define TARGET_BIG_SWITCH (target_flags & MASK_BIG_SWITCH) 140 141 /* Generate code for the HPPA 2.0 architecture. TARGET_PA_11 should also be 142 true when this is true. */ 143 #define MASK_PA_20 4096 144 145 /* Generate cpp defines for server I/O. */ 146 #define MASK_SIO 8192 147 #define TARGET_SIO (target_flags & MASK_SIO) 148 149 /* Assume GNU linker by default. */ 150 #define MASK_GNU_LD 16384 151 #ifndef TARGET_GNU_LD 152 #define TARGET_GNU_LD (target_flags & MASK_GNU_LD) 153 #endif 154 155 /* Force generation of long calls. */ 156 #define MASK_LONG_CALLS 32768 157 #ifndef TARGET_LONG_CALLS 158 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS) 159 #endif 160 161 #ifndef TARGET_PA_10 162 #define TARGET_PA_10 (target_flags & (MASK_PA_11 | MASK_PA_20) == 0) 163 #endif 164 165 #ifndef TARGET_PA_11 166 #define TARGET_PA_11 (target_flags & MASK_PA_11) 167 #endif 168 169 #ifndef TARGET_PA_20 170 #define TARGET_PA_20 (target_flags & MASK_PA_20) 171 #endif 172 173 /* Generate code for the HPPA 2.0 architecture in 64bit mode. */ 174 #ifndef TARGET_64BIT 175 #define TARGET_64BIT 0 176 #endif 177 178 /* Generate code for ELF32 ABI. */ 179 #ifndef TARGET_ELF32 180 #define TARGET_ELF32 0 181 #endif 182 183 /* Generate code for SOM 32bit ABI. */ 184 #ifndef TARGET_SOM 185 #define TARGET_SOM 0 186 #endif 187 188 /* The following three defines are potential target switches. The current 189 defines are optimal given the current capabilities of GAS and GNU ld. */ 190 191 /* Define to a C expression evaluating to true to use long absolute calls. 192 Currently, only the HP assembler and SOM linker support long absolute 193 calls. They are used only in non-pic code. */ 194 #define TARGET_LONG_ABS_CALL (TARGET_SOM && !TARGET_GAS) 195 196 /* Define to a C expression evaluating to true to use long pic symbol 197 difference calls. This is a call variant similar to the long pic 198 pc-relative call. Long pic symbol difference calls are only used with 199 the HP SOM linker. Currently, only the HP assembler supports these 200 calls. GAS doesn't allow an arbitrary difference of two symbols. */ 201 #define TARGET_LONG_PIC_SDIFF_CALL (!TARGET_GAS) 202 203 /* Define to a C expression evaluating to true to use long pic 204 pc-relative calls. Long pic pc-relative calls are only used with 205 GAS. Currently, they are usable for calls within a module but 206 not for external calls. */ 207 #define TARGET_LONG_PIC_PCREL_CALL 0 208 209 /* Define to a C expression evaluating to true to use SOM secondary 210 definition symbols for weak support. Linker support for secondary 211 definition symbols is buggy prior to HP-UX 11.X. */ 212 #define TARGET_SOM_SDEF 0 213 214 /* Define to a C expression evaluating to true to save the entry value 215 of SP in the current frame marker. This is normally unnecessary. 216 However, the HP-UX unwind library looks at the SAVE_SP callinfo flag. 217 HP compilers don't use this flag but it is supported by the assembler. 218 We set this flag to indicate that register %r3 has been saved at the 219 start of the frame. Thus, when the HP unwind library is used, we 220 need to generate additional code to save SP into the frame marker. */ 221 #define TARGET_HPUX_UNWIND_LIBRARY 0 222 223 /* Macro to define tables used to set the flags. This is a 224 list in braces of target switches with each switch being 225 { "NAME", VALUE, "HELP_STRING" }. VALUE is the bits to set, 226 or minus the bits to clear. An empty string NAME is used to 227 identify the default VALUE. Do not mark empty strings for 228 translation. */ 229 230 #define TARGET_SWITCHES \ 231 {{ "snake", MASK_PA_11, \ 232 N_("Generate PA1.1 code") }, \ 233 { "nosnake", -(MASK_PA_11 | MASK_PA_20), \ 234 N_("Generate PA1.0 code") }, \ 235 { "pa-risc-1-0", -(MASK_PA_11 | MASK_PA_20), \ 236 N_("Generate PA1.0 code") }, \ 237 { "pa-risc-1-1", MASK_PA_11, \ 238 N_("Generate PA1.1 code") }, \ 239 { "pa-risc-2-0", MASK_PA_20, \ 240 N_("Generate PA2.0 code (requires binutils 2.10 or later)") }, \ 241 { "disable-fpregs", MASK_DISABLE_FPREGS, \ 242 N_("Disable FP regs") }, \ 243 { "no-disable-fpregs", -MASK_DISABLE_FPREGS, \ 244 N_("Do not disable FP regs") }, \ 245 { "no-space-regs", MASK_NO_SPACE_REGS, \ 246 N_("Disable space regs") }, \ 247 { "space-regs", -MASK_NO_SPACE_REGS, \ 248 N_("Do not disable space regs") }, \ 249 { "jump-in-delay", MASK_JUMP_IN_DELAY, \ 250 N_("Put jumps in call delay slots") }, \ 251 { "no-jump-in-delay", -MASK_JUMP_IN_DELAY, \ 252 N_("Do not put jumps in call delay slots") }, \ 253 { "disable-indexing", MASK_DISABLE_INDEXING, \ 254 N_("Disable indexed addressing") }, \ 255 { "no-disable-indexing", -MASK_DISABLE_INDEXING, \ 256 N_("Do not disable indexed addressing") }, \ 257 { "portable-runtime", MASK_PORTABLE_RUNTIME, \ 258 N_("Use portable calling conventions") }, \ 259 { "no-portable-runtime", -MASK_PORTABLE_RUNTIME, \ 260 N_("Do not use portable calling conventions") }, \ 261 { "gas", MASK_GAS, \ 262 N_("Assume code will be assembled by GAS") }, \ 263 { "no-gas", -MASK_GAS, \ 264 N_("Do not assume code will be assembled by GAS") }, \ 265 { "soft-float", MASK_SOFT_FLOAT, \ 266 N_("Use software floating point") }, \ 267 { "no-soft-float", -MASK_SOFT_FLOAT, \ 268 N_("Do not use software floating point") }, \ 269 { "long-load-store", MASK_LONG_LOAD_STORE, \ 270 N_("Emit long load/store sequences") }, \ 271 { "no-long-load-store", -MASK_LONG_LOAD_STORE, \ 272 N_("Do not emit long load/store sequences") }, \ 273 { "fast-indirect-calls", MASK_FAST_INDIRECT_CALLS, \ 274 N_("Generate fast indirect calls") }, \ 275 { "no-fast-indirect-calls", -MASK_FAST_INDIRECT_CALLS, \ 276 N_("Do not generate fast indirect calls") }, \ 277 { "big-switch", MASK_BIG_SWITCH, \ 278 N_("Generate code for huge switch statements") }, \ 279 { "no-big-switch", -MASK_BIG_SWITCH, \ 280 N_("Do not generate code for huge switch statements") }, \ 281 { "long-calls", MASK_LONG_CALLS, \ 282 N_("Always generate long calls") }, \ 283 { "no-long-calls", -MASK_LONG_CALLS, \ 284 N_("Generate long calls only when needed") }, \ 285 { "linker-opt", 0, \ 286 N_("Enable linker optimizations") }, \ 287 SUBTARGET_SWITCHES \ 288 { "", TARGET_DEFAULT | TARGET_CPU_DEFAULT, \ 289 NULL }} 290 291 #ifndef TARGET_DEFAULT 292 #define TARGET_DEFAULT (MASK_GAS | MASK_JUMP_IN_DELAY) 293 #endif 294 295 #ifndef TARGET_CPU_DEFAULT 296 #define TARGET_CPU_DEFAULT 0 297 #endif 298 299 #ifndef SUBTARGET_SWITCHES 300 #define SUBTARGET_SWITCHES 301 #endif 302 303 #ifndef TARGET_SCHED_DEFAULT 304 #define TARGET_SCHED_DEFAULT "8000" 305 #endif 306 307 #define TARGET_OPTIONS \ 308 { \ 309 { "schedule=", &pa_cpu_string, \ 310 N_("Specify CPU for scheduling purposes"), 0}, \ 311 { "arch=", &pa_arch_string, \ 312 N_("Specify architecture for code generation. Values are 1.0, 1.1, and 2.0. 2.0 requires gas snapshot 19990413 or later."), 0}\ 313 } 314 315 /* Support for a compile-time default CPU, et cetera. The rules are: 316 --with-schedule is ignored if -mschedule is specified. 317 --with-arch is ignored if -march is specified. */ 318 #define OPTION_DEFAULT_SPECS \ 319 {"arch", "%{!march=*:-march=%(VALUE)}" }, \ 320 {"schedule", "%{!mschedule=*:-mschedule=%(VALUE)}" } 321 322 /* Specify the dialect of assembler to use. New mnemonics is dialect one 323 and the old mnemonics are dialect zero. */ 324 #define ASSEMBLER_DIALECT (TARGET_PA_20 ? 1 : 0) 325 326 #define OVERRIDE_OPTIONS override_options () 327 328 /* Override some settings from dbxelf.h. */ 329 330 /* We do not have to be compatible with dbx, so we enable gdb extensions 331 by default. */ 332 #define DEFAULT_GDB_EXTENSIONS 1 333 334 /* This used to be zero (no max length), but big enums and such can 335 cause huge strings which killed gas. 336 337 We also have to avoid lossage in dbxout.c -- it does not compute the 338 string size accurately, so we are real conservative here. */ 339 #undef DBX_CONTIN_LENGTH 340 #define DBX_CONTIN_LENGTH 3000 341 342 /* Only labels should ever begin in column zero. */ 343 #define ASM_STABS_OP "\t.stabs\t" 344 #define ASM_STABN_OP "\t.stabn\t" 345 346 /* GDB always assumes the current function's frame begins at the value 347 of the stack pointer upon entry to the current function. Accessing 348 local variables and parameters passed on the stack is done using the 349 base of the frame + an offset provided by GCC. 350 351 For functions which have frame pointers this method works fine; 352 the (frame pointer) == (stack pointer at function entry) and GCC provides 353 an offset relative to the frame pointer. 354 355 This loses for functions without a frame pointer; GCC provides an offset 356 which is relative to the stack pointer after adjusting for the function's 357 frame size. GDB would prefer the offset to be relative to the value of 358 the stack pointer at the function's entry. Yuk! */ 359 #define DEBUGGER_AUTO_OFFSET(X) \ 360 ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \ 361 + (frame_pointer_needed ? 0 : compute_frame_size (get_frame_size (), 0))) 362 363 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \ 364 ((GET_CODE (X) == PLUS ? OFFSET : 0) \ 365 + (frame_pointer_needed ? 0 : compute_frame_size (get_frame_size (), 0))) 366 367 #define TARGET_CPU_CPP_BUILTINS() \ 368 do { \ 369 builtin_assert("cpu=hppa"); \ 370 builtin_assert("machine=hppa"); \ 371 builtin_define("__hppa"); \ 372 builtin_define("__hppa__"); \ 373 if (TARGET_PA_20) \ 374 builtin_define("_PA_RISC2_0"); \ 375 else if (TARGET_PA_11) \ 376 builtin_define("_PA_RISC1_1"); \ 377 else \ 378 builtin_define("_PA_RISC1_0"); \ 379 } while (0) 380 381 /* An old set of OS defines for various BSD-like systems. */ 382 #define TARGET_OS_CPP_BUILTINS() \ 383 do \ 384 { \ 385 builtin_define_std ("REVARGV"); \ 386 builtin_define_std ("hp800"); \ 387 builtin_define_std ("hp9000"); \ 388 builtin_define_std ("hp9k8"); \ 389 if (!c_dialect_cxx () && !flag_iso) \ 390 builtin_define ("hppa"); \ 391 builtin_define_std ("spectrum"); \ 392 builtin_define_std ("unix"); \ 393 builtin_assert ("system=bsd"); \ 394 builtin_assert ("system=unix"); \ 395 } \ 396 while (0) 397 398 #define CC1_SPEC "%{pg:} %{p:}" 399 400 #define LINK_SPEC "%{mlinker-opt:-O} %{!shared:-u main} %{shared:-b}" 401 402 /* We don't want -lg. */ 403 #ifndef LIB_SPEC 404 #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}" 405 #endif 406 407 /* This macro defines command-line switches that modify the default 408 target name. 409 410 The definition is be an initializer for an array of structures. Each 411 array element has have three elements: the switch name, one of the 412 enumeration codes ADD or DELETE to indicate whether the string should be 413 inserted or deleted, and the string to be inserted or deleted. */ 414 #define MODIFY_TARGET_NAME {{"-32", DELETE, "64"}, {"-64", ADD, "64"}} 415 416 /* Make gcc agree with <machine/ansi.h> */ 417 418 #define SIZE_TYPE "unsigned int" 419 #define PTRDIFF_TYPE "int" 420 #define WCHAR_TYPE "unsigned int" 421 #define WCHAR_TYPE_SIZE 32 422 423 /* Show we can debug even without a frame pointer. */ 424 #define CAN_DEBUG_WITHOUT_FP 425 426 /* target machine storage layout */ 427 428 /* Define this macro if it is advisable to hold scalars in registers 429 in a wider mode than that declared by the program. In such cases, 430 the value is constrained to be within the bounds of the declared 431 type, but kept valid in the wider mode. The signedness of the 432 extension may differ from that of the type. */ 433 434 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 435 if (GET_MODE_CLASS (MODE) == MODE_INT \ 436 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 437 (MODE) = word_mode; 438 439 /* Define this if most significant bit is lowest numbered 440 in instructions that operate on numbered bit-fields. */ 441 #define BITS_BIG_ENDIAN 1 442 443 /* Define this if most significant byte of a word is the lowest numbered. */ 444 /* That is true on the HP-PA. */ 445 #define BYTES_BIG_ENDIAN 1 446 447 /* Define this if most significant word of a multiword number is lowest 448 numbered. */ 449 #define WORDS_BIG_ENDIAN 1 450 451 #define MAX_BITS_PER_WORD 64 452 #define MAX_LONG_TYPE_SIZE 32 453 454 /* Width of a word, in units (bytes). */ 455 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 456 #define MIN_UNITS_PER_WORD 4 457 458 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 459 #define PARM_BOUNDARY BITS_PER_WORD 460 461 /* Largest alignment required for any stack parameter, in bits. 462 Don't define this if it is equal to PARM_BOUNDARY */ 463 #define MAX_PARM_BOUNDARY BIGGEST_ALIGNMENT 464 465 /* Boundary (in *bits*) on which stack pointer is always aligned; 466 certain optimizations in combine depend on this. 467 468 The HP-UX runtime documents mandate 64-byte and 16-byte alignment for 469 the stack on the 32 and 64-bit ports, respectively. However, we 470 are only guaranteed that the stack is aligned to BIGGEST_ALIGNMENT 471 in main. Thus, we treat the former as the preferred alignment. */ 472 #define STACK_BOUNDARY BIGGEST_ALIGNMENT 473 #define PREFERRED_STACK_BOUNDARY (TARGET_64BIT ? 128 : 512) 474 475 /* Allocation boundary (in *bits*) for the code of a function. */ 476 #define FUNCTION_BOUNDARY BITS_PER_WORD 477 478 /* Alignment of field after `int : 0' in a structure. */ 479 #define EMPTY_FIELD_BOUNDARY 32 480 481 /* Every structure's size must be a multiple of this. */ 482 #define STRUCTURE_SIZE_BOUNDARY 8 483 484 /* A bit-field declared as `int' forces `int' alignment for the struct. */ 485 #define PCC_BITFIELD_TYPE_MATTERS 1 486 487 /* No data type wants to be aligned rounder than this. */ 488 #define BIGGEST_ALIGNMENT (2 * BITS_PER_WORD) 489 490 /* Get around hp-ux assembler bug, and make strcpy of constants fast. */ 491 #define CONSTANT_ALIGNMENT(CODE, TYPEALIGN) \ 492 ((TYPEALIGN) < 32 ? 32 : (TYPEALIGN)) 493 494 /* Make arrays of chars word-aligned for the same reasons. */ 495 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 496 (TREE_CODE (TYPE) == ARRAY_TYPE \ 497 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 498 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) 499 500 /* Set this nonzero if move instructions will actually fail to work 501 when given unaligned data. */ 502 #define STRICT_ALIGNMENT 1 503 504 /* Generate calls to memcpy, memcmp and memset. */ 505 #define TARGET_MEM_FUNCTIONS 506 507 /* Value is 1 if it is a good idea to tie two pseudo registers 508 when one has mode MODE1 and one has mode MODE2. 509 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 510 for any hard reg, then this must be 0 for correct output. */ 511 #define MODES_TIEABLE_P(MODE1, MODE2) \ 512 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) 513 514 /* Specify the registers used for certain standard purposes. 515 The values of these macros are register numbers. */ 516 517 /* The HP-PA pc isn't overloaded on a register that the compiler knows about. */ 518 /* #define PC_REGNUM */ 519 520 /* Register to use for pushing function arguments. */ 521 #define STACK_POINTER_REGNUM 30 522 523 /* Base register for access to local variables of the function. */ 524 #define FRAME_POINTER_REGNUM 3 525 526 /* Value should be nonzero if functions must have frame pointers. */ 527 #define FRAME_POINTER_REQUIRED \ 528 (current_function_calls_alloca) 529 530 /* C statement to store the difference between the frame pointer 531 and the stack pointer values immediately after the function prologue. 532 533 Note, we always pretend that this is a leaf function because if 534 it's not, there's no point in trying to eliminate the 535 frame pointer. If it is a leaf function, we guessed right! */ 536 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \ 537 do {(VAR) = - compute_frame_size (get_frame_size (), 0);} while (0) 538 539 /* Base register for access to arguments of the function. */ 540 #define ARG_POINTER_REGNUM 3 541 542 /* Register in which static-chain is passed to a function. */ 543 #define STATIC_CHAIN_REGNUM 29 544 545 /* Register used to address the offset table for position-independent 546 data references. */ 547 #define PIC_OFFSET_TABLE_REGNUM \ 548 (flag_pic ? (TARGET_64BIT ? 27 : 19) : INVALID_REGNUM) 549 550 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 1 551 552 /* Function to return the rtx used to save the pic offset table register 553 across function calls. */ 554 extern struct rtx_def *hppa_pic_save_rtx (void); 555 556 #define DEFAULT_PCC_STRUCT_RETURN 0 557 558 /* SOM ABI says that objects larger than 64 bits are returned in memory. 559 PA64 ABI says that objects larger than 128 bits are returned in memory. 560 Note, int_size_in_bytes can return -1 if the size of the object is 561 variable or larger than the maximum value that can be expressed as 562 a HOST_WIDE_INT. It can also return zero for an empty type. The 563 simplest way to handle variable and empty types is to pass them in 564 memory. This avoids problems in defining the boundaries of argument 565 slots, allocating registers, etc. */ 566 #define RETURN_IN_MEMORY(TYPE) \ 567 (int_size_in_bytes (TYPE) > (TARGET_64BIT ? 16 : 8) \ 568 || int_size_in_bytes (TYPE) <= 0) 569 570 /* Register in which address to store a structure value 571 is passed to a function. */ 572 #define STRUCT_VALUE_REGNUM 28 573 574 /* Describe how we implement __builtin_eh_return. */ 575 #define EH_RETURN_DATA_REGNO(N) \ 576 ((N) < 3 ? (N) + 20 : (N) == 3 ? 31 : INVALID_REGNUM) 577 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 29) 578 #define EH_RETURN_HANDLER_RTX \ 579 gen_rtx_MEM (word_mode, \ 580 gen_rtx_PLUS (word_mode, frame_pointer_rtx, \ 581 TARGET_64BIT ? GEN_INT (-16) : GEN_INT (-20))) 582 583 584 /* Offset from the argument pointer register value to the top of 585 stack. This is different from FIRST_PARM_OFFSET because of the 586 frame marker. */ 587 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 588 589 /* The letters I, J, K, L and M in a register constraint string 590 can be used to stand for particular ranges of immediate operands. 591 This macro defines what the ranges are. 592 C is the letter, and VALUE is a constant value. 593 Return 1 if VALUE is in the range specified by C. 594 595 `I' is used for the 11 bit constants. 596 `J' is used for the 14 bit constants. 597 `K' is used for values that can be moved with a zdepi insn. 598 `L' is used for the 5 bit constants. 599 `M' is used for 0. 600 `N' is used for values with the least significant 11 bits equal to zero 601 and when sign extended from 32 to 64 bits the 602 value does not change. 603 `O' is used for numbers n such that n+1 is a power of 2. 604 */ 605 606 #define CONST_OK_FOR_LETTER_P(VALUE, C) \ 607 ((C) == 'I' ? VAL_11_BITS_P (VALUE) \ 608 : (C) == 'J' ? VAL_14_BITS_P (VALUE) \ 609 : (C) == 'K' ? zdepi_cint_p (VALUE) \ 610 : (C) == 'L' ? VAL_5_BITS_P (VALUE) \ 611 : (C) == 'M' ? (VALUE) == 0 \ 612 : (C) == 'N' ? (((VALUE) & (((HOST_WIDE_INT) -1 << 31) | 0x7ff)) == 0 \ 613 || (((VALUE) & (((HOST_WIDE_INT) -1 << 31) | 0x7ff)) \ 614 == (HOST_WIDE_INT) -1 << 31)) \ 615 : (C) == 'O' ? (((VALUE) & ((VALUE) + 1)) == 0) \ 616 : (C) == 'P' ? and_mask_p (VALUE) \ 617 : 0) 618 619 /* Similar, but for floating or large integer constants, and defining letters 620 G and H. Here VALUE is the CONST_DOUBLE rtx itself. 621 622 For PA, `G' is the floating-point constant zero. `H' is undefined. */ 623 624 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 625 ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \ 626 && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \ 627 : 0) 628 629 /* The class value for index registers, and the one for base regs. */ 630 #define INDEX_REG_CLASS GENERAL_REGS 631 #define BASE_REG_CLASS GENERAL_REGS 632 633 #define FP_REG_CLASS_P(CLASS) \ 634 ((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS) 635 636 /* True if register is floating-point. */ 637 #define FP_REGNO_P(N) ((N) >= FP_REG_FIRST && (N) <= FP_REG_LAST) 638 639 /* Given an rtx X being reloaded into a reg required to be 640 in class CLASS, return the class of reg to actually use. 641 In general this is just CLASS; but on some machines 642 in some cases it is preferable to use a more restrictive class. */ 643 #define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS) 644 645 /* Return the register class of a scratch register needed to copy 646 IN into a register in CLASS in MODE, or a register in CLASS in MODE 647 to IN. If it can be done directly NO_REGS is returned. 648 649 Avoid doing any work for the common case calls. */ 650 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ 651 ((CLASS == BASE_REG_CLASS && GET_CODE (IN) == REG \ 652 && REGNO (IN) < FIRST_PSEUDO_REGISTER) \ 653 ? NO_REGS : secondary_reload_class (CLASS, MODE, IN)) 654 655 #define MAYBE_FP_REG_CLASS_P(CLASS) \ 656 reg_classes_intersect_p ((CLASS), FP_REGS) 657 658 /* On the PA it is not possible to directly move data between 659 GENERAL_REGS and FP_REGS. */ 660 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 661 (MAYBE_FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2) \ 662 || MAYBE_FP_REG_CLASS_P (CLASS2) != FP_REG_CLASS_P (CLASS1)) 663 664 /* Return the stack location to use for secondary memory needed reloads. */ 665 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \ 666 gen_rtx_MEM (MODE, gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-16))) 667 668 669 /* Stack layout; function entry, exit and calling. */ 670 671 /* Define this if pushing a word on the stack 672 makes the stack pointer a smaller address. */ 673 /* #define STACK_GROWS_DOWNWARD */ 674 675 /* Believe it or not. */ 676 #define ARGS_GROW_DOWNWARD 677 678 /* Define this if the nominal address of the stack frame 679 is at the high-address end of the local variables; 680 that is, each additional local variable allocated 681 goes at a more negative offset in the frame. */ 682 /* #define FRAME_GROWS_DOWNWARD */ 683 684 /* Offset within stack frame to start allocating local variables at. 685 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 686 first local allocated. Otherwise, it is the offset to the BEGINNING 687 of the first local allocated. 688 689 On the 32-bit ports, we reserve one slot for the previous frame 690 pointer and one fill slot. The fill slot is for compatibility 691 with HP compiled programs. On the 64-bit ports, we reserve one 692 slot for the previous frame pointer. */ 693 #define STARTING_FRAME_OFFSET 8 694 695 /* Define STACK_ALIGNMENT_NEEDED to zero to disable final alignment 696 of the stack. The default is to align it to STACK_BOUNDARY. */ 697 #define STACK_ALIGNMENT_NEEDED 0 698 699 /* If we generate an insn to push BYTES bytes, 700 this says how many the stack pointer really advances by. 701 On the HP-PA, don't define this because there are no push insns. */ 702 /* #define PUSH_ROUNDING(BYTES) */ 703 704 /* Offset of first parameter from the argument pointer register value. 705 This value will be negated because the arguments grow down. 706 Also note that on STACK_GROWS_UPWARD machines (such as this one) 707 this is the distance from the frame pointer to the end of the first 708 argument, not it's beginning. To get the real offset of the first 709 argument, the size of the argument must be added. */ 710 711 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_64BIT ? -64 : -32) 712 713 /* When a parameter is passed in a register, stack space is still 714 allocated for it. */ 715 #define REG_PARM_STACK_SPACE(DECL) (TARGET_64BIT ? 64 : 16) 716 717 /* Define this if the above stack space is to be considered part of the 718 space allocated by the caller. */ 719 #define OUTGOING_REG_PARM_STACK_SPACE 720 721 /* Keep the stack pointer constant throughout the function. 722 This is both an optimization and a necessity: longjmp 723 doesn't behave itself when the stack pointer moves within 724 the function! */ 725 #define ACCUMULATE_OUTGOING_ARGS 1 726 727 /* The weird HPPA calling conventions require a minimum of 48 bytes on 728 the stack: 16 bytes for register saves, and 32 bytes for magic. 729 This is the difference between the logical top of stack and the 730 actual sp. 731 732 On the 64-bit port, the HP C compiler allocates a 48-byte frame 733 marker, although the runtime documentation only describes a 16 734 byte marker. For compatibility, we allocate 48 bytes. */ 735 #define STACK_POINTER_OFFSET \ 736 (TARGET_64BIT ? -(current_function_outgoing_args_size + 48): -32) 737 738 #define STACK_DYNAMIC_OFFSET(FNDECL) \ 739 (TARGET_64BIT \ 740 ? (STACK_POINTER_OFFSET) \ 741 : ((STACK_POINTER_OFFSET) - current_function_outgoing_args_size)) 742 743 /* Value is 1 if returning from a function call automatically 744 pops the arguments described by the number-of-args field in the call. 745 FUNDECL is the declaration node of the function (as a tree), 746 FUNTYPE is the data type of the function (as a tree), 747 or for a library call it is an identifier node for the subroutine name. */ 748 749 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 750 751 /* Define how to find the value returned by a function. 752 VALTYPE is the data type of the value (as a tree). 753 If the precise function being called is known, FUNC is its FUNCTION_DECL; 754 otherwise, FUNC is 0. */ 755 756 #define FUNCTION_VALUE(VALTYPE, FUNC) function_value (VALTYPE, FUNC) 757 758 /* Define how to find the value returned by a library function 759 assuming the value has mode MODE. */ 760 761 #define LIBCALL_VALUE(MODE) \ 762 gen_rtx_REG (MODE, \ 763 (! TARGET_SOFT_FLOAT \ 764 && ((MODE) == SFmode || (MODE) == DFmode) ? 32 : 28)) 765 766 /* 1 if N is a possible register number for a function value 767 as seen by the caller. */ 768 769 #define FUNCTION_VALUE_REGNO_P(N) \ 770 ((N) == 28 || (! TARGET_SOFT_FLOAT && (N) == 32)) 771 772 773 /* Define a data type for recording info about an argument list 774 during the scan of that argument list. This data type should 775 hold all necessary information about the function itself 776 and about the args processed so far, enough to enable macros 777 such as FUNCTION_ARG to determine where the next arg should go. 778 779 On the HP-PA, the WORDS field holds the number of words 780 of arguments scanned so far (including the invisible argument, 781 if any, which holds the structure-value-address). Thus, 4 or 782 more means all following args should go on the stack. 783 784 The INCOMING field tracks whether this is an "incoming" or 785 "outgoing" argument. 786 787 The INDIRECT field indicates whether this is is an indirect 788 call or not. 789 790 The NARGS_PROTOTYPE field indicates that an argument does not 791 have a prototype when it less than or equal to 0. */ 792 793 struct hppa_args {int words, nargs_prototype, incoming, indirect; }; 794 795 #define CUMULATIVE_ARGS struct hppa_args 796 797 /* Initialize a variable CUM of type CUMULATIVE_ARGS 798 for a call to a function whose data type is FNTYPE. 799 For a library call, FNTYPE is 0. */ 800 801 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 802 (CUM).words = 0, \ 803 (CUM).incoming = 0, \ 804 (CUM).indirect = (FNTYPE) && !(FNDECL), \ 805 (CUM).nargs_prototype = (FNTYPE && TYPE_ARG_TYPES (FNTYPE) \ 806 ? (list_length (TYPE_ARG_TYPES (FNTYPE)) - 1 \ 807 + (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \ 808 || RETURN_IN_MEMORY (TREE_TYPE (FNTYPE)))) \ 809 : 0) 810 811 812 813 /* Similar, but when scanning the definition of a procedure. We always 814 set NARGS_PROTOTYPE large so we never return a PARALLEL. */ 815 816 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,IGNORE) \ 817 (CUM).words = 0, \ 818 (CUM).incoming = 1, \ 819 (CUM).indirect = 0, \ 820 (CUM).nargs_prototype = 1000 821 822 /* Figure out the size in words of the function argument. The size 823 returned by this macro should always be greater than zero because 824 we pass variable and zero sized objects by reference. */ 825 826 #define FUNCTION_ARG_SIZE(MODE, TYPE) \ 827 ((((MODE) != BLKmode \ 828 ? (HOST_WIDE_INT) GET_MODE_SIZE (MODE) \ 829 : int_size_in_bytes (TYPE)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 830 831 /* Update the data in CUM to advance over an argument 832 of mode MODE and data type TYPE. 833 (TYPE is null for libcalls where that information may not be available.) */ 834 835 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 836 { (CUM).nargs_prototype--; \ 837 (CUM).words += FUNCTION_ARG_SIZE(MODE, TYPE) \ 838 + (((CUM).words & 01) && (TYPE) != 0 \ 839 && FUNCTION_ARG_SIZE(MODE, TYPE) > 1); \ 840 } 841 842 /* Determine where to put an argument to a function. 843 Value is zero to push the argument on the stack, 844 or a hard register in which to store the argument. 845 846 MODE is the argument's machine mode. 847 TYPE is the data type of the argument (as a tree). 848 This is null for libcalls where that information may 849 not be available. 850 CUM is a variable of type CUMULATIVE_ARGS which gives info about 851 the preceding args and about the function being called. 852 NAMED is nonzero if this argument is a named parameter 853 (otherwise it is an extra parameter matching an ellipsis). 854 855 On the HP-PA the first four words of args are normally in registers 856 and the rest are pushed. But any arg that won't entirely fit in regs 857 is pushed. 858 859 Arguments passed in registers are either 1 or 2 words long. 860 861 The caller must make a distinction between calls to explicitly named 862 functions and calls through pointers to functions -- the conventions 863 are different! Calls through pointers to functions only use general 864 registers for the first four argument words. 865 866 Of course all this is different for the portable runtime model 867 HP wants everyone to use for ELF. Ugh. Here's a quick description 868 of how it's supposed to work. 869 870 1) callee side remains unchanged. It expects integer args to be 871 in the integer registers, float args in the float registers and 872 unnamed args in integer registers. 873 874 2) caller side now depends on if the function being called has 875 a prototype in scope (rather than if it's being called indirectly). 876 877 2a) If there is a prototype in scope, then arguments are passed 878 according to their type (ints in integer registers, floats in float 879 registers, unnamed args in integer registers. 880 881 2b) If there is no prototype in scope, then floating point arguments 882 are passed in both integer and float registers. egad. 883 884 FYI: The portable parameter passing conventions are almost exactly like 885 the standard parameter passing conventions on the RS6000. That's why 886 you'll see lots of similar code in rs6000.h. */ 887 888 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding ((MODE), (TYPE)) 889 890 /* Do not expect to understand this without reading it several times. I'm 891 tempted to try and simply it, but I worry about breaking something. */ 892 893 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 894 function_arg (&CUM, MODE, TYPE, NAMED) 895 896 /* Nonzero if we do not know how to pass TYPE solely in registers. */ 897 #define MUST_PASS_IN_STACK(MODE,TYPE) \ 898 ((TYPE) != 0 \ 899 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \ 900 || TREE_ADDRESSABLE (TYPE))) 901 902 /* For an arg passed partly in registers and partly in memory, 903 this is the number of registers used. 904 For args passed entirely in registers or entirely in memory, zero. */ 905 906 /* For PA32 there are never split arguments. PA64, on the other hand, can 907 pass arguments partially in registers and partially in memory. */ 908 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ 909 (TARGET_64BIT ? function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED) : 0) 910 911 /* If defined, a C expression that gives the alignment boundary, in 912 bits, of an argument with the specified mode and type. If it is 913 not defined, `PARM_BOUNDARY' is used for all arguments. */ 914 915 /* Arguments larger than one word are double word aligned. */ 916 917 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 918 (((TYPE) \ 919 ? (integer_zerop (TYPE_SIZE (TYPE)) \ 920 || !TREE_CONSTANT (TYPE_SIZE (TYPE)) \ 921 || int_size_in_bytes (TYPE) <= UNITS_PER_WORD) \ 922 : GET_MODE_SIZE(MODE) <= UNITS_PER_WORD) \ 923 ? PARM_BOUNDARY : MAX_PARM_BOUNDARY) 924 925 /* In the 32-bit runtime, arguments larger than eight bytes are passed 926 by invisible reference. As a GCC extension, we also pass anything 927 with a zero or variable size by reference. 928 929 The 64-bit runtime does not describe passing any types by invisible 930 reference. The internals of GCC can't currently handle passing 931 empty structures, and zero or variable length arrays when they are 932 not passed entirely on the stack or by reference. Thus, as a GCC 933 extension, we pass these types by reference. The HP compiler doesn't 934 support these types, so hopefully there shouldn't be any compatibility 935 issues. This may have to be revisited when HP releases a C99 compiler 936 or updates the ABI. */ 937 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ 938 (TARGET_64BIT \ 939 ? ((TYPE) && int_size_in_bytes (TYPE) <= 0) \ 940 : (((TYPE) && (int_size_in_bytes (TYPE) > 8 \ 941 || int_size_in_bytes (TYPE) <= 0)) \ 942 || ((MODE) && GET_MODE_SIZE (MODE) > 8))) 943 944 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \ 945 FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED) 946 947 948 extern GTY(()) rtx hppa_compare_op0; 949 extern GTY(()) rtx hppa_compare_op1; 950 extern enum cmp_type hppa_branch_type; 951 952 /* On HPPA, we emit profiling code as rtl via PROFILE_HOOK rather than 953 as assembly via FUNCTION_PROFILER. Just output a local label. 954 We can't use the function label because the GAS SOM target can't 955 handle the difference of a global symbol and a local symbol. */ 956 957 #ifndef FUNC_BEGIN_PROLOG_LABEL 958 #define FUNC_BEGIN_PROLOG_LABEL "LFBP" 959 #endif 960 961 #define FUNCTION_PROFILER(FILE, LABEL) \ 962 (*targetm.asm_out.internal_label) (FILE, FUNC_BEGIN_PROLOG_LABEL, LABEL) 963 964 #define PROFILE_HOOK(label_no) hppa_profile_hook (label_no) 965 void hppa_profile_hook (int label_no); 966 967 /* The profile counter if emitted must come before the prologue. */ 968 #define PROFILE_BEFORE_PROLOGUE 1 969 970 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 971 the stack pointer does not matter. The value is tested only in 972 functions that have frame pointers. 973 No definition is equivalent to always zero. */ 974 975 extern int may_call_alloca; 976 977 #define EXIT_IGNORE_STACK \ 978 (get_frame_size () != 0 \ 979 || current_function_calls_alloca || current_function_outgoing_args_size) 980 981 /* Output assembler code for a block containing the constant parts 982 of a trampoline, leaving space for the variable parts.\ 983 984 The trampoline sets the static chain pointer to STATIC_CHAIN_REGNUM 985 and then branches to the specified routine. 986 987 This code template is copied from text segment to stack location 988 and then patched with INITIALIZE_TRAMPOLINE to contain 989 valid values, and then entered as a subroutine. 990 991 It is best to keep this as small as possible to avoid having to 992 flush multiple lines in the cache. */ 993 994 #define TRAMPOLINE_TEMPLATE(FILE) \ 995 { \ 996 if (!TARGET_64BIT) \ 997 { \ 998 fputs ("\tldw 36(%r22),%r21\n", FILE); \ 999 fputs ("\tbb,>=,n %r21,30,.+16\n", FILE); \ 1000 if (ASSEMBLER_DIALECT == 0) \ 1001 fputs ("\tdepi 0,31,2,%r21\n", FILE); \ 1002 else \ 1003 fputs ("\tdepwi 0,31,2,%r21\n", FILE); \ 1004 fputs ("\tldw 4(%r21),%r19\n", FILE); \ 1005 fputs ("\tldw 0(%r21),%r21\n", FILE); \ 1006 if (TARGET_PA_20) \ 1007 { \ 1008 fputs ("\tbve (%r21)\n", FILE); \ 1009 fputs ("\tldw 40(%r22),%r29\n", FILE); \ 1010 fputs ("\t.word 0\n", FILE); \ 1011 fputs ("\t.word 0\n", FILE); \ 1012 } \ 1013 else \ 1014 { \ 1015 fputs ("\tldsid (%r21),%r1\n", FILE); \ 1016 fputs ("\tmtsp %r1,%sr0\n", FILE); \ 1017 fputs ("\tbe 0(%sr0,%r21)\n", FILE); \ 1018 fputs ("\tldw 40(%r22),%r29\n", FILE); \ 1019 } \ 1020 fputs ("\t.word 0\n", FILE); \ 1021 fputs ("\t.word 0\n", FILE); \ 1022 fputs ("\t.word 0\n", FILE); \ 1023 fputs ("\t.word 0\n", FILE); \ 1024 } \ 1025 else \ 1026 { \ 1027 fputs ("\t.dword 0\n", FILE); \ 1028 fputs ("\t.dword 0\n", FILE); \ 1029 fputs ("\t.dword 0\n", FILE); \ 1030 fputs ("\t.dword 0\n", FILE); \ 1031 fputs ("\tmfia %r31\n", FILE); \ 1032 fputs ("\tldd 24(%r31),%r1\n", FILE); \ 1033 fputs ("\tldd 24(%r1),%r27\n", FILE); \ 1034 fputs ("\tldd 16(%r1),%r1\n", FILE); \ 1035 fputs ("\tbve (%r1)\n", FILE); \ 1036 fputs ("\tldd 32(%r31),%r31\n", FILE); \ 1037 fputs ("\t.dword 0 ; fptr\n", FILE); \ 1038 fputs ("\t.dword 0 ; static link\n", FILE); \ 1039 } \ 1040 } 1041 1042 /* Length in units of the trampoline for entering a nested function. */ 1043 1044 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 72 : 52) 1045 1046 /* Length in units of the trampoline instruction code. */ 1047 1048 #define TRAMPOLINE_CODE_SIZE (TARGET_64BIT ? 24 : (TARGET_PA_20 ? 32 : 40)) 1049 1050 /* Minimum length of a cache line. A length of 16 will work on all 1051 PA-RISC processors. All PA 1.1 processors have a cache line of 1052 32 bytes. Most but not all PA 2.0 processors have a cache line 1053 of 64 bytes. As cache flushes are expensive and we don't support 1054 PA 1.0, we use a minimum length of 32. */ 1055 1056 #define MIN_CACHELINE_SIZE 32 1057 1058 /* Emit RTL insns to initialize the variable parts of a trampoline. 1059 FNADDR is an RTX for the address of the function's pure code. 1060 CXT is an RTX for the static chain value for the function. 1061 1062 Move the function address to the trampoline template at offset 36. 1063 Move the static chain value to trampoline template at offset 40. 1064 Move the trampoline address to trampoline template at offset 44. 1065 Move r19 to trampoline template at offset 48. The latter two 1066 words create a plabel for the indirect call to the trampoline. 1067 1068 A similar sequence is used for the 64-bit port but the plabel is 1069 at the beginning of the trampoline. 1070 1071 Finally, the cache entries for the trampoline code are flushed. 1072 This is necessary to ensure that the trampoline instruction sequence 1073 is written to memory prior to any attempts at prefetching the code 1074 sequence. */ 1075 1076 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1077 { \ 1078 rtx start_addr = gen_reg_rtx (Pmode); \ 1079 rtx end_addr = gen_reg_rtx (Pmode); \ 1080 rtx line_length = gen_reg_rtx (Pmode); \ 1081 rtx tmp; \ 1082 \ 1083 if (!TARGET_64BIT) \ 1084 { \ 1085 tmp = memory_address (Pmode, plus_constant ((TRAMP), 36)); \ 1086 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (FNADDR)); \ 1087 tmp = memory_address (Pmode, plus_constant ((TRAMP), 40)); \ 1088 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (CXT)); \ 1089 \ 1090 /* Create a fat pointer for the trampoline. */ \ 1091 tmp = memory_address (Pmode, plus_constant ((TRAMP), 44)); \ 1092 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (TRAMP)); \ 1093 tmp = memory_address (Pmode, plus_constant ((TRAMP), 48)); \ 1094 emit_move_insn (gen_rtx_MEM (Pmode, tmp), \ 1095 gen_rtx_REG (Pmode, 19)); \ 1096 \ 1097 /* fdc and fic only use registers for the address to flush, \ 1098 they do not accept integer displacements. We align the \ 1099 start and end addresses to the beginning of their respective \ 1100 cache lines to minimize the number of lines flushed. */ \ 1101 tmp = force_reg (Pmode, (TRAMP)); \ 1102 emit_insn (gen_andsi3 (start_addr, tmp, \ 1103 GEN_INT (-MIN_CACHELINE_SIZE))); \ 1104 tmp = force_reg (Pmode, \ 1105 plus_constant (tmp, TRAMPOLINE_CODE_SIZE - 1)); \ 1106 emit_insn (gen_andsi3 (end_addr, tmp, \ 1107 GEN_INT (-MIN_CACHELINE_SIZE))); \ 1108 emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE)); \ 1109 emit_insn (gen_dcacheflush (start_addr, end_addr, line_length)); \ 1110 emit_insn (gen_icacheflush (start_addr, end_addr, line_length, \ 1111 gen_reg_rtx (Pmode), \ 1112 gen_reg_rtx (Pmode))); \ 1113 } \ 1114 else \ 1115 { \ 1116 tmp = memory_address (Pmode, plus_constant ((TRAMP), 56)); \ 1117 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (FNADDR)); \ 1118 tmp = memory_address (Pmode, plus_constant ((TRAMP), 64)); \ 1119 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (CXT)); \ 1120 \ 1121 /* Create a fat pointer for the trampoline. */ \ 1122 tmp = memory_address (Pmode, plus_constant ((TRAMP), 16)); \ 1123 emit_move_insn (gen_rtx_MEM (Pmode, tmp), \ 1124 force_reg (Pmode, plus_constant ((TRAMP), 32))); \ 1125 tmp = memory_address (Pmode, plus_constant ((TRAMP), 24)); \ 1126 emit_move_insn (gen_rtx_MEM (Pmode, tmp), \ 1127 gen_rtx_REG (Pmode, 27)); \ 1128 \ 1129 /* fdc and fic only use registers for the address to flush, \ 1130 they do not accept integer displacements. We align the \ 1131 start and end addresses to the beginning of their respective \ 1132 cache lines to minimize the number of lines flushed. */ \ 1133 tmp = force_reg (Pmode, plus_constant ((TRAMP), 32)); \ 1134 emit_insn (gen_anddi3 (start_addr, tmp, \ 1135 GEN_INT (-MIN_CACHELINE_SIZE))); \ 1136 tmp = force_reg (Pmode, \ 1137 plus_constant (tmp, TRAMPOLINE_CODE_SIZE - 1)); \ 1138 emit_insn (gen_anddi3 (end_addr, tmp, \ 1139 GEN_INT (-MIN_CACHELINE_SIZE))); \ 1140 emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE)); \ 1141 emit_insn (gen_dcacheflush (start_addr, end_addr, line_length)); \ 1142 emit_insn (gen_icacheflush (start_addr, end_addr, line_length, \ 1143 gen_reg_rtx (Pmode), \ 1144 gen_reg_rtx (Pmode))); \ 1145 } \ 1146 } 1147 1148 /* Perform any machine-specific adjustment in the address of the trampoline. 1149 ADDR contains the address that was passed to INITIALIZE_TRAMPOLINE. 1150 Adjust the trampoline address to point to the plabel at offset 44. */ 1151 1152 #define TRAMPOLINE_ADJUST_ADDRESS(ADDR) \ 1153 if (!TARGET_64BIT) (ADDR) = memory_address (Pmode, plus_constant ((ADDR), 46)) 1154 1155 /* Emit code for a call to builtin_saveregs. We must emit USE insns which 1156 reference the 4 integer arg registers and 4 fp arg registers. 1157 Ordinarily they are not call used registers, but they are for 1158 _builtin_saveregs, so we must make this explicit. */ 1159 1160 #define EXPAND_BUILTIN_SAVEREGS() hppa_builtin_saveregs () 1161 1162 /* Implement `va_start' for varargs and stdarg. */ 1163 1164 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \ 1165 hppa_va_start (valist, nextarg) 1166 1167 /* Implement `va_arg'. */ 1168 1169 #define EXPAND_BUILTIN_VA_ARG(valist, type) \ 1170 hppa_va_arg (valist, type) 1171 1172 /* Addressing modes, and classification of registers for them. 1173 1174 Using autoincrement addressing modes on PA8000 class machines is 1175 not profitable. */ 1176 1177 #define HAVE_POST_INCREMENT (pa_cpu < PROCESSOR_8000) 1178 #define HAVE_POST_DECREMENT (pa_cpu < PROCESSOR_8000) 1179 1180 #define HAVE_PRE_DECREMENT (pa_cpu < PROCESSOR_8000) 1181 #define HAVE_PRE_INCREMENT (pa_cpu < PROCESSOR_8000) 1182 1183 /* Macros to check register numbers against specific register classes. */ 1184 1185 /* These assume that REGNO is a hard or pseudo reg number. 1186 They give nonzero only if REGNO is a hard reg of the suitable class 1187 or a pseudo reg currently allocated to a suitable hard reg. 1188 Since they use reg_renumber, they are safe only once reg_renumber 1189 has been allocated, which happens in local-alloc.c. */ 1190 1191 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1192 ((REGNO) && ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)) 1193 #define REGNO_OK_FOR_BASE_P(REGNO) \ 1194 ((REGNO) && ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)) 1195 #define REGNO_OK_FOR_FP_P(REGNO) \ 1196 (FP_REGNO_P (REGNO) || FP_REGNO_P (reg_renumber[REGNO])) 1197 1198 /* Now macros that check whether X is a register and also, 1199 strictly, whether it is in a specified class. 1200 1201 These macros are specific to the HP-PA, and may be used only 1202 in code for printing assembler insns and in conditions for 1203 define_optimization. */ 1204 1205 /* 1 if X is an fp register. */ 1206 1207 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) 1208 1209 /* Maximum number of registers that can appear in a valid memory address. */ 1210 1211 #define MAX_REGS_PER_ADDRESS 2 1212 1213 /* Recognize any constant value that is a valid address except 1214 for symbolic addresses. We get better CSE by rejecting them 1215 here and allowing hppa_legitimize_address to break them up. We 1216 use most of the constants accepted by CONSTANT_P, except CONST_DOUBLE. */ 1217 1218 #define CONSTANT_ADDRESS_P(X) \ 1219 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 1220 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ 1221 || GET_CODE (X) == HIGH) \ 1222 && (reload_in_progress || reload_completed || ! symbolic_expression_p (X))) 1223 1224 /* A C expression that is nonzero if we are using the new HP assembler. */ 1225 1226 #ifndef NEW_HP_ASSEMBLER 1227 #define NEW_HP_ASSEMBLER 0 1228 #endif 1229 1230 /* The macros below define the immediate range for CONST_INTS on 1231 the 64-bit port. Constants in this range can be loaded in three 1232 instructions using a ldil/ldo/depdi sequence. Constants outside 1233 this range are forced to the constant pool prior to reload. */ 1234 1235 #define MAX_LEGIT_64BIT_CONST_INT ((HOST_WIDE_INT) 32 << 31) 1236 #define MIN_LEGIT_64BIT_CONST_INT ((HOST_WIDE_INT) -32 << 31) 1237 #define LEGITIMATE_64BIT_CONST_INT_P(X) \ 1238 ((X) >= MIN_LEGIT_64BIT_CONST_INT && (X) < MAX_LEGIT_64BIT_CONST_INT) 1239 1240 /* A C expression that is nonzero if X is a legitimate constant for an 1241 immediate operand. 1242 1243 We include all constant integers and constant doubles, but not 1244 floating-point, except for floating-point zero. We reject LABEL_REFs 1245 if we're not using gas or the new HP assembler. 1246 1247 In 64-bit mode, we reject CONST_DOUBLES. We also reject CONST_INTS 1248 that need more than three instructions to load prior to reload. This 1249 limit is somewhat arbitrary. It takes three instructions to load a 1250 CONST_INT from memory but two are memory accesses. It may be better 1251 to increase the allowed range for CONST_INTS. We may also be able 1252 to handle CONST_DOUBLES. */ 1253 1254 #define LEGITIMATE_CONSTANT_P(X) \ 1255 ((GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \ 1256 || (X) == CONST0_RTX (GET_MODE (X))) \ 1257 && (NEW_HP_ASSEMBLER || TARGET_GAS || GET_CODE (X) != LABEL_REF) \ 1258 && !(TARGET_64BIT && GET_CODE (X) == CONST_DOUBLE) \ 1259 && !(TARGET_64BIT && GET_CODE (X) == CONST_INT \ 1260 && !(HOST_BITS_PER_WIDE_INT <= 32 \ 1261 || (reload_in_progress || reload_completed) \ 1262 || LEGITIMATE_64BIT_CONST_INT_P (INTVAL (X)) \ 1263 || cint_ok_for_move (INTVAL (X)))) \ 1264 && !function_label_operand (X, VOIDmode)) 1265 1266 /* Subroutines for EXTRA_CONSTRAINT. 1267 1268 Return 1 iff OP is a pseudo which did not get a hard register and 1269 we are running the reload pass. */ 1270 #define IS_RELOADING_PSEUDO_P(OP) \ 1271 ((reload_in_progress \ 1272 && GET_CODE (OP) == REG \ 1273 && REGNO (OP) >= FIRST_PSEUDO_REGISTER \ 1274 && reg_renumber [REGNO (OP)] < 0)) 1275 1276 /* Return 1 iff OP is a scaled or unscaled index address. */ 1277 #define IS_INDEX_ADDR_P(OP) \ 1278 (GET_CODE (OP) == PLUS \ 1279 && GET_MODE (OP) == Pmode \ 1280 && (GET_CODE (XEXP (OP, 0)) == MULT \ 1281 || GET_CODE (XEXP (OP, 1)) == MULT \ 1282 || (REG_P (XEXP (OP, 0)) \ 1283 && REG_P (XEXP (OP, 1))))) 1284 1285 /* Return 1 iff OP is a LO_SUM DLT address. */ 1286 #define IS_LO_SUM_DLT_ADDR_P(OP) \ 1287 (GET_CODE (OP) == LO_SUM \ 1288 && GET_MODE (OP) == Pmode \ 1289 && REG_P (XEXP (OP, 0)) \ 1290 && REG_OK_FOR_BASE_P (XEXP (OP, 0)) \ 1291 && GET_CODE (XEXP (OP, 1)) == UNSPEC) 1292 1293 /* Optional extra constraints for this machine. Borrowed from sparc.h. 1294 1295 `A' is a LO_SUM DLT memory operand. 1296 1297 `Q' is any memory operand that isn't a symbolic, indexed or lo_sum 1298 memory operand. Note that an unassigned pseudo register is such a 1299 memory operand. Needed because reload will generate these things 1300 and then not re-recognize the insn, causing constrain_operands to 1301 fail. 1302 1303 `R' is a scaled/unscaled indexed memory operand. 1304 1305 `S' is the constant 31. 1306 1307 `T' is for floating-point loads and stores. 1308 1309 `U' is the constant 63. */ 1310 1311 #define EXTRA_CONSTRAINT(OP, C) \ 1312 ((C) == 'Q' ? \ 1313 (IS_RELOADING_PSEUDO_P (OP) \ 1314 || (GET_CODE (OP) == MEM \ 1315 && (reload_in_progress \ 1316 || memory_address_p (GET_MODE (OP), XEXP (OP, 0))) \ 1317 && !symbolic_memory_operand (OP, VOIDmode) \ 1318 && !IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0)) \ 1319 && !IS_INDEX_ADDR_P (XEXP (OP, 0)))) \ 1320 : ((C) == 'A' ? \ 1321 (GET_CODE (OP) == MEM \ 1322 && IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0))) \ 1323 : ((C) == 'R' ? \ 1324 (GET_CODE (OP) == MEM \ 1325 && IS_INDEX_ADDR_P (XEXP (OP, 0))) \ 1326 : ((C) == 'T' ? \ 1327 (GET_CODE (OP) == MEM \ 1328 && !IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0)) \ 1329 && !IS_INDEX_ADDR_P (XEXP (OP, 0)) \ 1330 /* Floating-point loads and stores are used to load \ 1331 integer values as well as floating-point values. \ 1332 They don't have the same set of REG+D address modes \ 1333 as integer loads and stores. PA 1.x supports only \ 1334 short displacements. PA 2.0 supports long displacements \ 1335 but the base register needs to be aligned. \ 1336 \ 1337 The checks in GO_IF_LEGITIMATE_ADDRESS for SFmode and \ 1338 DFmode test the validity of an address for use in a \ 1339 floating point load or store. So, we use SFmode/DFmode \ 1340 to see if the address is valid for a floating-point \ 1341 load/store operation. */ \ 1342 && memory_address_p ((GET_MODE_SIZE (GET_MODE (OP)) == 4 \ 1343 ? SFmode \ 1344 : DFmode), \ 1345 XEXP (OP, 0))) \ 1346 : ((C) == 'S' ? \ 1347 (GET_CODE (OP) == CONST_INT && INTVAL (OP) == 31) \ 1348 : ((C) == 'U' ? \ 1349 (GET_CODE (OP) == CONST_INT && INTVAL (OP) == 63) : 0)))))) 1350 1351 1352 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1353 and check its validity for a certain class. 1354 We have two alternate definitions for each of them. 1355 The usual definition accepts all pseudo regs; the other rejects 1356 them unless they have been allocated suitable hard regs. 1357 The symbol REG_OK_STRICT causes the latter definition to be used. 1358 1359 Most source files want to accept pseudo regs in the hope that 1360 they will get allocated to the class that the insn wants them to be in. 1361 Source files for reload pass need to be strict. 1362 After reload, it makes no difference, since pseudo regs have 1363 been eliminated by then. */ 1364 1365 #ifndef REG_OK_STRICT 1366 1367 /* Nonzero if X is a hard reg that can be used as an index 1368 or if it is a pseudo reg. */ 1369 #define REG_OK_FOR_INDEX_P(X) \ 1370 (REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER)) 1371 /* Nonzero if X is a hard reg that can be used as a base reg 1372 or if it is a pseudo reg. */ 1373 #define REG_OK_FOR_BASE_P(X) \ 1374 (REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER)) 1375 1376 #else 1377 1378 /* Nonzero if X is a hard reg that can be used as an index. */ 1379 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1380 /* Nonzero if X is a hard reg that can be used as a base reg. */ 1381 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1382 1383 #endif 1384 1385 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a 1386 valid memory address for an instruction. The MODE argument is the 1387 machine mode for the MEM expression that wants to use this address. 1388 1389 On HP PA-RISC, the legitimate address forms are REG+SMALLINT, 1390 REG+REG, and REG+(REG*SCALE). The indexed address forms are only 1391 available with floating point loads and stores, and integer loads. 1392 We get better code by allowing indexed addresses in the initial 1393 RTL generation. 1394 1395 The acceptance of indexed addresses as legitimate implies that we 1396 must provide patterns for doing indexed integer stores, or the move 1397 expanders must force the address of an indexed store to a register. 1398 We have adopted the latter approach. 1399 1400 Another function of GO_IF_LEGITIMATE_ADDRESS is to ensure that 1401 the base register is a valid pointer for indexed instructions. 1402 On targets that have non-equivalent space registers, we have to 1403 know at the time of assembler output which register in a REG+REG 1404 pair is the base register. The REG_POINTER flag is sometimes lost 1405 in reload and the following passes, so it can't be relied on during 1406 code generation. Thus, we either have to canonicalize the order 1407 of the registers in REG+REG indexed addresses, or treat REG+REG 1408 addresses separately and provide patterns for both permutations. 1409 1410 The latter approach requires several hundred additional lines of 1411 code in pa.md. The downside to canonicalizing is that a PLUS 1412 in the wrong order can't combine to form to make a scaled indexed 1413 memory operand. As we won't need to canonicalize the operands if 1414 the REG_POINTER lossage can be fixed, it seems better canonicalize. 1415 1416 We initially break out scaled indexed addresses in canonical order 1417 in emit_move_sequence. LEGITIMIZE_ADDRESS also canonicalizes 1418 scaled indexed addresses during RTL generation. However, fold_rtx 1419 has its own opinion on how the operands of a PLUS should be ordered. 1420 If one of the operands is equivalent to a constant, it will make 1421 that operand the second operand. As the base register is likely to 1422 be equivalent to a SYMBOL_REF, we have made it the second operand. 1423 1424 GO_IF_LEGITIMATE_ADDRESS accepts REG+REG as legitimate when the 1425 operands are in the order INDEX+BASE on targets with non-equivalent 1426 space registers, and in any order on targets with equivalent space 1427 registers. It accepts both MULT+BASE and BASE+MULT for scaled indexing. 1428 1429 We treat a SYMBOL_REF as legitimate if it is part of the current 1430 function's constant-pool, because such addresses can actually be 1431 output as REG+SMALLINT. 1432 1433 Note we only allow 5 bit immediates for access to a constant address; 1434 doing so avoids losing for loading/storing a FP register at an address 1435 which will not fit in 5 bits. */ 1436 1437 #define VAL_5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x10 < 0x20) 1438 #define INT_5_BITS(X) VAL_5_BITS_P (INTVAL (X)) 1439 1440 #define VAL_U5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) < 0x20) 1441 #define INT_U5_BITS(X) VAL_U5_BITS_P (INTVAL (X)) 1442 1443 #define VAL_11_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x400 < 0x800) 1444 #define INT_11_BITS(X) VAL_11_BITS_P (INTVAL (X)) 1445 1446 #define VAL_14_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x2000 < 0x4000) 1447 #define INT_14_BITS(X) VAL_14_BITS_P (INTVAL (X)) 1448 1449 #if HOST_BITS_PER_WIDE_INT > 32 1450 #define VAL_32_BITS_P(X) \ 1451 ((unsigned HOST_WIDE_INT)(X) + ((unsigned HOST_WIDE_INT) 1 << 31) \ 1452 < (unsigned HOST_WIDE_INT) 2 << 31) 1453 #else 1454 #define VAL_32_BITS_P(X) 1 1455 #endif 1456 #define INT_32_BITS(X) VAL_32_BITS_P (INTVAL (X)) 1457 1458 /* These are the modes that we allow for scaled indexing. */ 1459 #define MODE_OK_FOR_SCALED_INDEXING_P(MODE) \ 1460 ((TARGET_64BIT && (MODE) == DImode) \ 1461 || (MODE) == SImode \ 1462 || (MODE) == HImode \ 1463 || (!TARGET_SOFT_FLOAT && ((MODE) == DFmode || (MODE) == SFmode))) 1464 1465 /* These are the modes that we allow for unscaled indexing. */ 1466 #define MODE_OK_FOR_UNSCALED_INDEXING_P(MODE) \ 1467 ((TARGET_64BIT && (MODE) == DImode) \ 1468 || (MODE) == SImode \ 1469 || (MODE) == HImode \ 1470 || (MODE) == QImode \ 1471 || (!TARGET_SOFT_FLOAT && ((MODE) == DFmode || (MODE) == SFmode))) 1472 1473 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1474 { \ 1475 if ((REG_P (X) && REG_OK_FOR_BASE_P (X)) \ 1476 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC \ 1477 || GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC) \ 1478 && REG_P (XEXP (X, 0)) \ 1479 && REG_OK_FOR_BASE_P (XEXP (X, 0)))) \ 1480 goto ADDR; \ 1481 else if (GET_CODE (X) == PLUS) \ 1482 { \ 1483 rtx base = 0, index = 0; \ 1484 if (REG_P (XEXP (X, 1)) \ 1485 && REG_OK_FOR_BASE_P (XEXP (X, 1))) \ 1486 base = XEXP (X, 1), index = XEXP (X, 0); \ 1487 else if (REG_P (XEXP (X, 0)) \ 1488 && REG_OK_FOR_BASE_P (XEXP (X, 0))) \ 1489 base = XEXP (X, 0), index = XEXP (X, 1); \ 1490 if (base \ 1491 && GET_CODE (index) == CONST_INT \ 1492 && ((INT_14_BITS (index) \ 1493 && (((MODE) != DImode \ 1494 && (MODE) != SFmode \ 1495 && (MODE) != DFmode) \ 1496 /* The base register for DImode loads and stores \ 1497 with long displacements must be aligned because \ 1498 the lower three bits in the displacement are \ 1499 assumed to be zero. */ \ 1500 || ((MODE) == DImode \ 1501 && (!TARGET_64BIT \ 1502 || (INTVAL (index) % 8) == 0)) \ 1503 /* Similarly, the base register for SFmode/DFmode \ 1504 loads and stores with long displacements must \ 1505 be aligned. \ 1506 \ 1507 FIXME: the ELF32 linker clobbers the LSB of \ 1508 the FP register number in PA 2.0 floating-point \ 1509 insns with long displacements. This is because \ 1510 R_PARISC_DPREL14WR and other relocations like \ 1511 it are not supported. For now, we reject long \ 1512 displacements on this target. */ \ 1513 || (((MODE) == SFmode || (MODE) == DFmode) \ 1514 && (TARGET_SOFT_FLOAT \ 1515 || (TARGET_PA_20 \ 1516 && !TARGET_ELF32 \ 1517 && (INTVAL (index) \ 1518 % GET_MODE_SIZE (MODE)) == 0))))) \ 1519 || INT_5_BITS (index))) \ 1520 goto ADDR; \ 1521 if (!TARGET_DISABLE_INDEXING \ 1522 /* Only accept the "canonical" INDEX+BASE operand order \ 1523 on targets with non-equivalent space registers. */ \ 1524 && (TARGET_NO_SPACE_REGS \ 1525 ? (base && REG_P (index)) \ 1526 : (base == XEXP (X, 1) && REG_P (index) \ 1527 && REG_POINTER (base) && !REG_POINTER (index))) \ 1528 && MODE_OK_FOR_UNSCALED_INDEXING_P (MODE) \ 1529 && REG_OK_FOR_INDEX_P (index) \ 1530 && borx_reg_operand (base, Pmode) \ 1531 && borx_reg_operand (index, Pmode)) \ 1532 goto ADDR; \ 1533 if (!TARGET_DISABLE_INDEXING \ 1534 && base \ 1535 && GET_CODE (index) == MULT \ 1536 && MODE_OK_FOR_SCALED_INDEXING_P (MODE) \ 1537 && REG_P (XEXP (index, 0)) \ 1538 && GET_MODE (XEXP (index, 0)) == Pmode \ 1539 && REG_OK_FOR_INDEX_P (XEXP (index, 0)) \ 1540 && GET_CODE (XEXP (index, 1)) == CONST_INT \ 1541 && INTVAL (XEXP (index, 1)) \ 1542 == (HOST_WIDE_INT) GET_MODE_SIZE (MODE) \ 1543 && borx_reg_operand (base, Pmode)) \ 1544 goto ADDR; \ 1545 } \ 1546 else if (GET_CODE (X) == LO_SUM \ 1547 && GET_CODE (XEXP (X, 0)) == REG \ 1548 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \ 1549 && CONSTANT_P (XEXP (X, 1)) \ 1550 && (TARGET_SOFT_FLOAT \ 1551 /* We can allow symbolic LO_SUM addresses for PA2.0. */ \ 1552 || (TARGET_PA_20 \ 1553 && !TARGET_ELF32 \ 1554 && GET_CODE (XEXP (X, 1)) != CONST_INT) \ 1555 || ((MODE) != SFmode \ 1556 && (MODE) != DFmode))) \ 1557 goto ADDR; \ 1558 else if (GET_CODE (X) == LO_SUM \ 1559 && GET_CODE (XEXP (X, 0)) == SUBREG \ 1560 && GET_CODE (SUBREG_REG (XEXP (X, 0))) == REG \ 1561 && REG_OK_FOR_BASE_P (SUBREG_REG (XEXP (X, 0))) \ 1562 && CONSTANT_P (XEXP (X, 1)) \ 1563 && (TARGET_SOFT_FLOAT \ 1564 /* We can allow symbolic LO_SUM addresses for PA2.0. */ \ 1565 || (TARGET_PA_20 \ 1566 && !TARGET_ELF32 \ 1567 && GET_CODE (XEXP (X, 1)) != CONST_INT) \ 1568 || ((MODE) != SFmode \ 1569 && (MODE) != DFmode))) \ 1570 goto ADDR; \ 1571 else if (GET_CODE (X) == LABEL_REF \ 1572 || (GET_CODE (X) == CONST_INT \ 1573 && INT_5_BITS (X))) \ 1574 goto ADDR; \ 1575 /* Needed for -fPIC */ \ 1576 else if (GET_CODE (X) == LO_SUM \ 1577 && GET_CODE (XEXP (X, 0)) == REG \ 1578 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \ 1579 && GET_CODE (XEXP (X, 1)) == UNSPEC \ 1580 && (TARGET_SOFT_FLOAT \ 1581 || (TARGET_PA_20 && !TARGET_ELF32) \ 1582 || ((MODE) != SFmode \ 1583 && (MODE) != DFmode))) \ 1584 goto ADDR; \ 1585 } 1586 1587 /* Look for machine dependent ways to make the invalid address AD a 1588 valid address. 1589 1590 For the PA, transform: 1591 1592 memory(X + <large int>) 1593 1594 into: 1595 1596 if (<large int> & mask) >= 16 1597 Y = (<large int> & ~mask) + mask + 1 Round up. 1598 else 1599 Y = (<large int> & ~mask) Round down. 1600 Z = X + Y 1601 memory (Z + (<large int> - Y)); 1602 1603 This makes reload inheritance and reload_cse work better since Z 1604 can be reused. 1605 1606 There may be more opportunities to improve code with this hook. */ 1607 #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \ 1608 do { \ 1609 long offset, newoffset, mask; \ 1610 rtx new, temp = NULL_RTX; \ 1611 \ 1612 mask = (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1613 ? (TARGET_PA_20 && !TARGET_ELF32 ? 0x3fff : 0x1f) : 0x3fff); \ 1614 \ 1615 if (optimize && GET_CODE (AD) == PLUS) \ 1616 temp = simplify_binary_operation (PLUS, Pmode, \ 1617 XEXP (AD, 0), XEXP (AD, 1)); \ 1618 \ 1619 new = temp ? temp : AD; \ 1620 \ 1621 if (optimize \ 1622 && GET_CODE (new) == PLUS \ 1623 && GET_CODE (XEXP (new, 0)) == REG \ 1624 && GET_CODE (XEXP (new, 1)) == CONST_INT) \ 1625 { \ 1626 offset = INTVAL (XEXP ((new), 1)); \ 1627 \ 1628 /* Choose rounding direction. Round up if we are >= halfway. */ \ 1629 if ((offset & mask) >= ((mask + 1) / 2)) \ 1630 newoffset = (offset & ~mask) + mask + 1; \ 1631 else \ 1632 newoffset = offset & ~mask; \ 1633 \ 1634 /* Ensure that long displacements are aligned. */ \ 1635 if (!VAL_5_BITS_P (newoffset) \ 1636 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \ 1637 newoffset &= ~(GET_MODE_SIZE (MODE) -1); \ 1638 \ 1639 if (newoffset != 0 && VAL_14_BITS_P (newoffset)) \ 1640 { \ 1641 temp = gen_rtx_PLUS (Pmode, XEXP (new, 0), \ 1642 GEN_INT (newoffset)); \ 1643 AD = gen_rtx_PLUS (Pmode, temp, GEN_INT (offset - newoffset));\ 1644 push_reload (XEXP (AD, 0), 0, &XEXP (AD, 0), 0, \ 1645 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, \ 1646 (OPNUM), (TYPE)); \ 1647 goto WIN; \ 1648 } \ 1649 } \ 1650 } while (0) 1651 1652 1653 1654 1655 /* Try machine-dependent ways of modifying an illegitimate address 1656 to be legitimate. If we find one, return the new, valid address. 1657 This macro is used in only one place: `memory_address' in explow.c. 1658 1659 OLDX is the address as it was before break_out_memory_refs was called. 1660 In some cases it is useful to look at this to decide what needs to be done. 1661 1662 MODE and WIN are passed so that this macro can use 1663 GO_IF_LEGITIMATE_ADDRESS. 1664 1665 It is always safe for this macro to do nothing. It exists to recognize 1666 opportunities to optimize the output. */ 1667 1668 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 1669 { rtx orig_x = (X); \ 1670 (X) = hppa_legitimize_address (X, OLDX, MODE); \ 1671 if ((X) != orig_x && memory_address_p (MODE, X)) \ 1672 goto WIN; } 1673 1674 /* Go to LABEL if ADDR (a legitimate address expression) 1675 has an effect that depends on the machine mode it is used for. */ 1676 1677 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ 1678 if (GET_CODE (ADDR) == PRE_DEC \ 1679 || GET_CODE (ADDR) == POST_DEC \ 1680 || GET_CODE (ADDR) == PRE_INC \ 1681 || GET_CODE (ADDR) == POST_INC) \ 1682 goto LABEL 1683 1684 #define TARGET_ASM_SELECT_SECTION pa_select_section 1685 1686 /* Return a nonzero value if DECL has a section attribute. */ 1687 #define IN_NAMED_SECTION_P(DECL) \ 1688 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \ 1689 && DECL_SECTION_NAME (DECL) != NULL_TREE) 1690 1691 /* Define this macro if references to a symbol must be treated 1692 differently depending on something about the variable or 1693 function named by the symbol (such as what section it is in). 1694 1695 The macro definition, if any, is executed immediately after the 1696 rtl for DECL or other node is created. 1697 The value of the rtl will be a `mem' whose address is a 1698 `symbol_ref'. 1699 1700 The usual thing for this macro to do is to a flag in the 1701 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified 1702 name string in the `symbol_ref' (if one bit is not enough 1703 information). 1704 1705 On the HP-PA we use this to indicate if a symbol is in text or 1706 data space. Also, function labels need special treatment. */ 1707 1708 #define TEXT_SPACE_P(DECL)\ 1709 (TREE_CODE (DECL) == FUNCTION_DECL \ 1710 || (TREE_CODE (DECL) == VAR_DECL \ 1711 && TREE_READONLY (DECL) && ! TREE_SIDE_EFFECTS (DECL) \ 1712 && (! DECL_INITIAL (DECL) || ! reloc_needed (DECL_INITIAL (DECL))) \ 1713 && !flag_pic) \ 1714 || (TREE_CODE_CLASS (TREE_CODE (DECL)) == 'c' \ 1715 && !(TREE_CODE (DECL) == STRING_CST && flag_writable_strings))) 1716 1717 #define FUNCTION_NAME_P(NAME) (*(NAME) == '@') 1718 1719 /* Specify the machine mode that this machine uses for the index in the 1720 tablejump instruction. For small tables, an element consists of a 1721 ia-relative branch and its delay slot. When -mbig-switch is specified, 1722 we use a 32-bit absolute address for non-pic code, and a 32-bit offset 1723 for both 32 and 64-bit pic code. */ 1724 #define CASE_VECTOR_MODE (TARGET_BIG_SWITCH ? SImode : DImode) 1725 1726 /* Jump tables must be 32-bit aligned, no matter the size of the element. */ 1727 #define ADDR_VEC_ALIGN(ADDR_VEC) 2 1728 1729 /* Define this as 1 if `char' should by default be signed; else as 0. */ 1730 #define DEFAULT_SIGNED_CHAR 1 1731 1732 /* Max number of bytes we can move from memory to memory 1733 in one reasonably fast instruction. */ 1734 #define MOVE_MAX 8 1735 1736 /* Higher than the default as we prefer to use simple move insns 1737 (better scheduling and delay slot filling) and because our 1738 built-in block move is really a 2X unrolled loop. 1739 1740 Believe it or not, this has to be big enough to allow for copying all 1741 arguments passed in registers to avoid infinite recursion during argument 1742 setup for a function call. Why? Consider how we copy the stack slots 1743 reserved for parameters when they may be trashed by a call. */ 1744 #define MOVE_RATIO (TARGET_64BIT ? 8 : 4) 1745 1746 /* Define if operations between registers always perform the operation 1747 on the full register even if a narrower mode is specified. */ 1748 #define WORD_REGISTER_OPERATIONS 1749 1750 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1751 will either zero-extend or sign-extend. The value of this macro should 1752 be the code that says which one of the two operations is implicitly 1753 done, NIL if none. */ 1754 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1755 1756 /* Nonzero if access to memory by bytes is slow and undesirable. */ 1757 #define SLOW_BYTE_ACCESS 1 1758 1759 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1760 is done just by pretending it is already truncated. */ 1761 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1762 1763 /* When a prototype says `char' or `short', really pass an `int'. */ 1764 #define PROMOTE_PROTOTYPES 1 1765 #define PROMOTE_FUNCTION_RETURN 1 1766 1767 /* Specify the machine mode that pointers have. 1768 After generation of rtl, the compiler makes no further distinction 1769 between pointers and any other objects of this machine mode. */ 1770 #define Pmode word_mode 1771 1772 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 1773 return the mode to be used for the comparison. For floating-point, CCFPmode 1774 should be used. CC_NOOVmode should be used when the first operand is a 1775 PLUS, MINUS, or NEG. CCmode should be used when no special processing is 1776 needed. */ 1777 #define SELECT_CC_MODE(OP,X,Y) \ 1778 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode : CCmode) \ 1779 1780 /* A function address in a call instruction 1781 is a byte address (for indexing purposes) 1782 so give the MEM rtx a byte's mode. */ 1783 #define FUNCTION_MODE SImode 1784 1785 /* Define this if addresses of constant functions 1786 shouldn't be put through pseudo regs where they can be cse'd. 1787 Desirable on machines where ordinary constants are expensive 1788 but a CALL with constant address is cheap. */ 1789 #define NO_FUNCTION_CSE 1790 1791 /* Define this to be nonzero if shift instructions ignore all but the low-order 1792 few bits. */ 1793 #define SHIFT_COUNT_TRUNCATED 1 1794 1795 /* Compute extra cost of moving data between one register class 1796 and another. 1797 1798 Make moves from SAR so expensive they should never happen. We used to 1799 have 0xffff here, but that generates overflow in rare cases. 1800 1801 Copies involving a FP register and a non-FP register are relatively 1802 expensive because they must go through memory. 1803 1804 Other copies are reasonably cheap. */ 1805 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 1806 (CLASS1 == SHIFT_REGS ? 0x100 \ 1807 : FP_REG_CLASS_P (CLASS1) && ! FP_REG_CLASS_P (CLASS2) ? 16 \ 1808 : FP_REG_CLASS_P (CLASS2) && ! FP_REG_CLASS_P (CLASS1) ? 16 \ 1809 : 2) 1810 1811 /* Adjust the cost of branches. */ 1812 #define BRANCH_COST (pa_cpu == PROCESSOR_8000 ? 2 : 1) 1813 1814 /* Handling the special cases is going to get too complicated for a macro, 1815 just call `pa_adjust_insn_length' to do the real work. */ 1816 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \ 1817 LENGTH += pa_adjust_insn_length (INSN, LENGTH); 1818 1819 /* Millicode insns are actually function calls with some special 1820 constraints on arguments and register usage. 1821 1822 Millicode calls always expect their arguments in the integer argument 1823 registers, and always return their result in %r29 (ret1). They 1824 are expected to clobber their arguments, %r1, %r29, and the return 1825 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else. 1826 1827 This macro tells reorg that the references to arguments and 1828 millicode calls do not appear to happen until after the millicode call. 1829 This allows reorg to put insns which set the argument registers into the 1830 delay slot of the millicode call -- thus they act more like traditional 1831 CALL_INSNs. 1832 1833 Note we can not consider side effects of the insn to be delayed because 1834 the branch and link insn will clobber the return pointer. If we happened 1835 to use the return pointer in the delay slot of the call, then we lose. 1836 1837 get_attr_type will try to recognize the given insn, so make sure to 1838 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns 1839 in particular. */ 1840 #define INSN_REFERENCES_ARE_DELAYED(X) (insn_refs_are_delayed (X)) 1841 1842 1843 /* Control the assembler format that we output. */ 1844 1845 /* A C string constant describing how to begin a comment in the target 1846 assembler language. The compiler assumes that the comment will end at 1847 the end of the line. */ 1848 1849 #define ASM_COMMENT_START ";" 1850 1851 /* Output to assembler file text saying following lines 1852 may contain character constants, extra white space, comments, etc. */ 1853 1854 #define ASM_APP_ON "" 1855 1856 /* Output to assembler file text saying following lines 1857 no longer contain unusual constructs. */ 1858 1859 #define ASM_APP_OFF "" 1860 1861 /* This is how to output the definition of a user-level label named NAME, 1862 such as the label on a static function or variable NAME. */ 1863 1864 #define ASM_OUTPUT_LABEL(FILE, NAME) \ 1865 do { assemble_name (FILE, NAME); \ 1866 fputc ('\n', FILE); } while (0) 1867 1868 /* This is how to output a reference to a user-level label named NAME. 1869 `assemble_name' uses this. */ 1870 1871 #define ASM_OUTPUT_LABELREF(FILE,NAME) \ 1872 do { \ 1873 const char *xname = (NAME); \ 1874 if (FUNCTION_NAME_P (NAME)) \ 1875 xname += 1; \ 1876 if (xname[0] == '*') \ 1877 xname += 1; \ 1878 else \ 1879 fputs (user_label_prefix, FILE); \ 1880 fputs (xname, FILE); \ 1881 } while (0) 1882 1883 /* This is how to store into the string LABEL 1884 the symbol_ref name of an internal numbered label where 1885 PREFIX is the class of label and NUM is the number within the class. 1886 This is suitable for output with `assemble_name'. */ 1887 1888 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 1889 sprintf (LABEL, "*%c$%s%04ld", (PREFIX)[0], (PREFIX) + 1, (long)(NUM)) 1890 1891 #define TARGET_ASM_GLOBALIZE_LABEL pa_globalize_label 1892 1893 #define ASM_OUTPUT_ASCII(FILE, P, SIZE) \ 1894 output_ascii ((FILE), (P), (SIZE)) 1895 1896 /* Jump tables are always placed in the text section. Technically, it 1897 is possible to put them in the readonly data section when -mbig-switch 1898 is specified. This has the benefit of getting the table out of .text 1899 and reducing branch lengths as a result. The downside is that an 1900 additional insn (addil) is needed to access the table when generating 1901 PIC code. The address difference table also has to use 32-bit 1902 pc-relative relocations. Currently, GAS does not support these 1903 relocations, although it is easily modified to do this operation. 1904 The table entries need to look like "$L1+(.+8-$L0)-$PIC_pcrel$0" 1905 when using ELF GAS. A simple difference can be used when using 1906 SOM GAS or the HP assembler. The final downside is GDB complains 1907 about the nesting of the label for the table when debugging. */ 1908 1909 #define JUMP_TABLES_IN_TEXT_SECTION 1 1910 1911 /* This is how to output an element of a case-vector that is absolute. */ 1912 1913 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1914 if (TARGET_BIG_SWITCH) \ 1915 fprintf (FILE, "\t.word L$%04d\n", VALUE); \ 1916 else \ 1917 fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE) 1918 1919 /* This is how to output an element of a case-vector that is relative. 1920 Since we always place jump tables in the text section, the difference 1921 is absolute and requires no relocation. */ 1922 1923 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 1924 if (TARGET_BIG_SWITCH) \ 1925 fprintf (FILE, "\t.word L$%04d-L$%04d\n", VALUE, REL); \ 1926 else \ 1927 fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE) 1928 1929 /* This is how to output an assembler line that says to advance the 1930 location counter to a multiple of 2**LOG bytes. */ 1931 1932 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1933 fprintf (FILE, "\t.align %d\n", (1<<(LOG))) 1934 1935 #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 1936 fprintf (FILE, "\t.blockz "HOST_WIDE_INT_PRINT_UNSIGNED"\n", \ 1937 (unsigned HOST_WIDE_INT)(SIZE)) 1938 1939 /* This says how to output an assembler line to define a global common symbol 1940 with size SIZE (in bytes) and alignment ALIGN (in bits). */ 1941 1942 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGNED) \ 1943 { bss_section (); \ 1944 assemble_name ((FILE), (NAME)); \ 1945 fprintf ((FILE), "\t.comm "HOST_WIDE_INT_PRINT_UNSIGNED"\n", \ 1946 MAX ((unsigned HOST_WIDE_INT)(SIZE), \ 1947 ((unsigned HOST_WIDE_INT)(ALIGNED) / BITS_PER_UNIT)));} 1948 1949 /* This says how to output an assembler line to define a local common symbol 1950 with size SIZE (in bytes) and alignment ALIGN (in bits). */ 1951 1952 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \ 1953 { bss_section (); \ 1954 fprintf ((FILE), "\t.align %d\n", ((ALIGNED) / BITS_PER_UNIT)); \ 1955 assemble_name ((FILE), (NAME)); \ 1956 fprintf ((FILE), "\n\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", \ 1957 (unsigned HOST_WIDE_INT)(SIZE));} 1958 1959 #define ASM_PN_FORMAT "%s___%lu" 1960 1961 /* All HP assemblers use "!" to separate logical lines. */ 1962 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == '!') 1963 1964 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ 1965 ((CHAR) == '@' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^') 1966 1967 /* Print operand X (an rtx) in assembler syntax to file FILE. 1968 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 1969 For `%' followed by punctuation, CODE is the punctuation and X is null. 1970 1971 On the HP-PA, the CODE can be `r', meaning this is a register-only operand 1972 and an immediate zero should be represented as `r0'. 1973 1974 Several % codes are defined: 1975 O an operation 1976 C compare conditions 1977 N extract conditions 1978 M modifier to handle preincrement addressing for memory refs. 1979 F modifier to handle preincrement addressing for fp memory refs */ 1980 1981 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 1982 1983 1984 /* Print a memory address as an operand to reference that memory location. */ 1985 1986 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 1987 { register rtx addr = ADDR; \ 1988 register rtx base; \ 1989 int offset; \ 1990 switch (GET_CODE (addr)) \ 1991 { \ 1992 case REG: \ 1993 fprintf (FILE, "0(%s)", reg_names [REGNO (addr)]); \ 1994 break; \ 1995 case PLUS: \ 1996 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \ 1997 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1); \ 1998 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \ 1999 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0); \ 2000 else \ 2001 abort (); \ 2002 fprintf (FILE, "%d(%s)", offset, reg_names [REGNO (base)]); \ 2003 break; \ 2004 case LO_SUM: \ 2005 if (!symbolic_operand (XEXP (addr, 1), VOIDmode)) \ 2006 fputs ("R'", FILE); \ 2007 else if (flag_pic == 0) \ 2008 fputs ("RR'", FILE); \ 2009 else \ 2010 fputs ("RT'", FILE); \ 2011 output_global_address (FILE, XEXP (addr, 1), 0); \ 2012 fputs ("(", FILE); \ 2013 output_operand (XEXP (addr, 0), 0); \ 2014 fputs (")", FILE); \ 2015 break; \ 2016 case CONST_INT: \ 2017 fprintf (FILE, HOST_WIDE_INT_PRINT_DEC "(%%r0)", INTVAL (addr)); \ 2018 break; \ 2019 default: \ 2020 output_addr_const (FILE, addr); \ 2021 }} 2022 2023 2024 /* Find the return address associated with the frame given by 2025 FRAMEADDR. */ 2026 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \ 2027 (return_addr_rtx (COUNT, FRAMEADDR)) 2028 2029 /* Used to mask out junk bits from the return address, such as 2030 processor state, interrupt status, condition codes and the like. */ 2031 #define MASK_RETURN_ADDR \ 2032 /* The privilege level is in the two low order bits, mask em out \ 2033 of the return address. */ \ 2034 (GEN_INT (-4)) 2035 2036 /* The number of Pmode words for the setjmp buffer. */ 2037 #define JMP_BUF_SIZE 50 2038 2039 #define PREDICATE_CODES \ 2040 {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ 2041 {"call_operand_address", {LABEL_REF, SYMBOL_REF, CONST_INT, \ 2042 CONST_DOUBLE, CONST, HIGH, CONSTANT_P_RTX}}, \ 2043 {"indexed_memory_operand", {SUBREG, MEM}}, \ 2044 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \ 2045 {"symbolic_memory_operand", {SUBREG, MEM}}, \ 2046 {"reg_before_reload_operand", {REG, MEM}}, \ 2047 {"reg_or_0_or_nonsymb_mem_operand", {SUBREG, REG, MEM, CONST_INT, \ 2048 CONST_DOUBLE}}, \ 2049 {"move_dest_operand", {SUBREG, REG, MEM}}, \ 2050 {"move_src_operand", {SUBREG, REG, CONSTANT_P_RTX, CONST_INT, MEM}}, \ 2051 {"reg_or_cint_move_operand", {SUBREG, REG, CONST_INT}}, \ 2052 {"pic_label_operand", {LABEL_REF, CONST}}, \ 2053 {"fp_reg_operand", {REG}}, \ 2054 {"arith_operand", {SUBREG, REG, CONST_INT}}, \ 2055 {"arith11_operand", {SUBREG, REG, CONST_INT}}, \ 2056 {"pre_cint_operand", {CONST_INT}}, \ 2057 {"post_cint_operand", {CONST_INT}}, \ 2058 {"arith_double_operand", {SUBREG, REG, CONST_DOUBLE}}, \ 2059 {"ireg_or_int5_operand", {CONST_INT, REG}}, \ 2060 {"int5_operand", {CONST_INT}}, \ 2061 {"uint5_operand", {CONST_INT}}, \ 2062 {"int11_operand", {CONST_INT}}, \ 2063 {"uint32_operand", {CONST_INT, \ 2064 HOST_BITS_PER_WIDE_INT > 32 ? 0 : CONST_DOUBLE}}, \ 2065 {"arith5_operand", {SUBREG, REG, CONST_INT}}, \ 2066 {"and_operand", {SUBREG, REG, CONST_INT}}, \ 2067 {"ior_operand", {CONST_INT}}, \ 2068 {"lhs_lshift_cint_operand", {CONST_INT}}, \ 2069 {"lhs_lshift_operand", {SUBREG, REG, CONST_INT}}, \ 2070 {"arith32_operand", {SUBREG, REG, CONST_INT}}, \ 2071 {"pc_or_label_operand", {PC, LABEL_REF}}, \ 2072 {"plus_xor_ior_operator", {PLUS, XOR, IOR}}, \ 2073 {"shadd_operand", {CONST_INT}}, \ 2074 {"div_operand", {REG, CONST_INT}}, \ 2075 {"ireg_operand", {REG}}, \ 2076 {"cmpib_comparison_operator", {EQ, NE, LT, LE, LEU, \ 2077 GT, GTU, GE}}, \ 2078 {"movb_comparison_operator", {EQ, NE, LT, GE}}, 2079 2080 /* We need a libcall to canonicalize function pointers on TARGET_ELF32. */ 2081 #define CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL \ 2082 "__canonicalize_funcptr_for_compare" 2083