1 /* Definitions of target machine for GNU compiler for INMOS transputer family. 2 Copyright (C) 1992, 1993, 1994, 1995 Free Software Foundation, Inc. 3 4 Written by �yvind Harboe <oyvind.harboe@zylin.com> 5 6 This file is part of GNU CC. 7 8 GNU CC is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2, or (at your option) 11 any later version. 12 13 GNU CC is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GNU CC; see the file COPYING. If not, write to 20 the Free Software Foundation, 59 Temple Place - Suite 330, 21 Boston, MA 02111-1307, USA. */ 22 23 24 #undef LIB_SPEC 25 #define LIB_SPEC "--start-group -lc -lbcc --end-group" 26 27 28 #undef STARTFILE_SPEC 29 #define STARTFILE_SPEC "crt0.o%s crt_io.o%s crti%O%s crtbegin%O%s" 30 31 #undef ENDFILE_SPEC 32 #define ENDFILE_SPEC "crtend%O%s crtn%O%s" 33 34 35 /* just a shorthand for those hard-to-remember options */ 36 #define TARGET_OPTION_TRANSLATE_TABLE \ 37 { "-phi", "-mboard=phi" }, \ 38 { "-abel", "-mboard=abel" }, \ 39 { "-zeta", "-mboard=zeta" } 40 41 #define CC1_SPEC "" 42 43 #define ASM_SPEC "%{Os:--defsym OPTIMIZE_SIZE=1}" 44 45 #define LINK_SPEC "%{mboard=phi:--defsym ZPU_ID=2} %{mboard=zeta:--defsym ZPU_ID=1} %{mboard=abel:--defsym ZPU_ID=0}" 46 47 48 49 /* The ZPU architecture is stack/0-operand architecture, so omitting the 50 * frame pointer is fundamental to any sort of decent code quality. 51 * 52 * -fomit-frame-pointer will be enabled at all optimisation levels/options 53 * with CAN_DEBUG_WITHOUT_FP defined. 54 */ 55 #define CAN_DEBUG_WITHOUT_FP 1 56 57 58 59 60 extern int target_flags; 61 62 63 extern int target_flags; 64 65 66 67 #define ZPU_MULT (1<<0) 68 #define ZPU_DIV (1<<1) 69 #define ZPU_MOD (1<<2) 70 #define ZPU_NEG (1<<3) 71 #define ZPU_LOADSP (1<<4) 72 #define ZPU_STORESP (1<<5) 73 #define ZPU_PUSHSPADD (1<<6) 74 #define ZPU_CALLPCREL (1<<7) 75 #define ZPU_CALL (1<<8) 76 #define ZPU_ADDSP (1<<9) 77 #define ZPU_SUB (1<<10) 78 #define ZPU_XOR (1<<11) 79 #define ZPU_FLIP (1<<12) 80 #define ZPU_ASHIFTRT (1<<13) 81 #define ZPU_ASHIFTL (1<<14) 82 #define ZPU_SHIFTL (1<<15) 83 #define ZPU_NEQBRANCH (1<<16) 84 #define ZPU_LSHIFTRT (1<<17) 85 86 #define ZPU_BYTEOP (1<<18) 87 #define ZPU_SHORTOP (1<<19) 88 #define ZPU_EQ (1<<20) 89 #define ZPU_COMPARE (1<<21) 90 #define ZPU_POPPCREL (1<<22) 91 #define ZPU_BYTESBIG (1<<23) 92 #define ZPU_BITSBIG (1<<24) 93 #define ZPU_MEMREG (1<<25) 94 95 96 97 98 99 #define TARGET_SWITCHES_DEFAULT (0x7fffffff&~ZPU_BITSBIG) 100 101 102 103 104 #define TARGET_MULT ((target_flags & ZPU_MULT)!=0) 105 #define TARGET_DIV ((target_flags & ZPU_DIV)!=0) 106 #define TARGET_MOD ((target_flags & ZPU_MOD)!=0) 107 #define TARGET_NEG ((target_flags & ZPU_NEG)!=0) 108 #define TARGET_LOADSP ((target_flags & ZPU_LOADSP)!=0) 109 #define TARGET_STORESP ((target_flags & ZPU_STORESP)!=0) 110 #define TARGET_ADDSP ((target_flags & ZPU_ADDSP)!=0) 111 #define TARGET_PUSHSPADD ((target_flags & ZPU_PUSHSPADD)!=0) 112 #define TARGET_NEQBRANCH ((target_flags & ZPU_NEQBRANCH)!=0) 113 #define TARGET_ASHIFTRT ((target_flags & ZPU_ASHIFTRT)!=0) 114 #define TARGET_ASHIFTL ((target_flags & ZPU_ASHIFTL)!=0) 115 #define TARGET_LSHIFTRT ((target_flags & ZPU_LSHIFTRT)!=0) 116 #define TARGET_CALL ((target_flags & ZPU_CALL)!=0) 117 #define TARGET_CALLPCREL ((target_flags & ZPU_CALLPCREL)!=0) 118 #define TARGET_BYTEOP ((target_flags & ZPU_BYTEOP)!=0) 119 #define TARGET_SHORTOP ((target_flags & ZPU_SHORTOP)!=0) 120 #define TARGET_EQ ((target_flags & ZPU_EQ)!=0) 121 #define TARGET_COMPARE ((target_flags & ZPU_COMPARE)!=0) 122 #define TARGET_POPPCREL ((target_flags & ZPU_POPPCREL)!=0) 123 #define TARGET_BYTESBIG ((target_flags & ZPU_BYTESBIG)!=0) 124 #define TARGET_BITSBIG ((target_flags & ZPU_BITSBIG)!=0) 125 #define TARGET_MEMREG ((target_flags & ZPU_MEMREG)!=0) 126 127 128 #define TARGET_SWITCHES \ 129 { \ 130 { "mult", ZPU_MULT, "MULT instruction" },\ 131 { "no-mult", -ZPU_MULT, "MULT instruction" },\ 132 { "div", ZPU_DIV, "DIV instruction" },\ 133 { "no-div", -ZPU_DIV, "DIV instruction" },\ 134 { "mod", ZPU_MOD, "MOD instruction" },\ 135 { "no-mod", -ZPU_MOD, "MOD instruction" },\ 136 { "neg", ZPU_NEG, "NEG instruction" },\ 137 { "no-neg", -ZPU_NEG, "NEG instruction" },\ 138 { "loadsp", ZPU_LOADSP, "LOADSP instruction" },\ 139 { "no-loadsp", -ZPU_LOADSP, "LOADSP instruction" },\ 140 { "storesp", ZPU_STORESP, "STORESP instruction" },\ 141 { "no-storesp", -ZPU_STORESP, "STORESP instruction" },\ 142 { "pushspadd", ZPU_PUSHSPADD, "PUSHSPADD instruction" },\ 143 { "no-pushspadd", -ZPU_PUSHSPADD, "PUSHSPADD instruction" },\ 144 { "neqbranch", ZPU_NEQBRANCH, "NEQBRANCH instruction" },\ 145 { "no-neqbranch", -ZPU_NEQBRANCH, "NEQBRANCH instruction" },\ 146 { "addsp", ZPU_ADDSP, "ADDSP instruction" },\ 147 { "no-addsp", -ZPU_ADDSP, "ADDSP instruction" },\ 148 { "ashiftrt", ZPU_ASHIFTRT, "ASHIFTRIGHT instruction" },\ 149 { "no-ashiftrt", -ZPU_ASHIFTRT, "ASHIFTRIGHT instruction" },\ 150 { "ashiftl", ZPU_ASHIFTL, "ASHIFTLEFT instruction" },\ 151 { "no-ashiftl", -ZPU_ASHIFTL, "ASHIFTLEFT instruction" },\ 152 { "lshiftrt", ZPU_LSHIFTRT, "LSHIFTRIGHT instruction" },\ 153 { "no-lshiftrt", -ZPU_LSHIFTRT, "LSHIFTRIGHT instruction" },\ 154 { "call", ZPU_CALL, "CALL instruction" },\ 155 { "no-call", -ZPU_CALL, "CALL instruction" },\ 156 { "callpcrel", ZPU_CALLPCREL, "CALLPCREL instruction" },\ 157 { "no-callpcrel", -ZPU_CALLPCREL, "CALLPCREL instruction" },\ 158 { "shortop", ZPU_SHORTOP, "LOADH/STOREH instructions" },\ 159 { "no-shortop", -ZPU_SHORTOP, "LOADH/STOREH instructions" },\ 160 { "byteop", ZPU_BYTEOP, "LOADB/STOREB insructions" },\ 161 { "no-byteop", -ZPU_BYTEOP, "LOADB/STOREB insructions" },\ 162 { "eq", ZPU_EQ, "EQ insructions" },\ 163 { "no-eq", -ZPU_EQ, "EQ insructions" },\ 164 { "compare", ZPU_COMPARE, "COMPARE insructions" },\ 165 { "no-compare", -ZPU_COMPARE, "COMPARE insructions" },\ 166 { "poppcrel", ZPU_POPPCREL, "POPPCREL insructions" },\ 167 { "no-poppcrel", -ZPU_POPPCREL, "POPPCREL insructions" },\ 168 { "bytesbig", ZPU_BYTESBIG, "Bytes big endian" },\ 169 { "no-bytesbig", -ZPU_BYTESBIG, "Bytes big endian" },\ 170 { "bitsbig", ZPU_BITSBIG, "Bits big endian" },\ 171 { "no-bitsbig", -ZPU_BITSBIG, "Bits big endian" },\ 172 { "memreg", ZPU_MEMREG, "Store r0-r3 in memory location 0-15" },\ 173 { "no-memreg", -ZPU_MEMREG, "CALL _regpush and _regpop for r0-r3" },\ 174 { "", TARGET_SWITCHES_DEFAULT, "" }\ 175 } 176 177 extern const char *zpu_board_name; 178 179 #define TARGET_OPTIONS { \ 180 { "board=", &zpu_board_name, N_("Specify the ZPU board name"), 0} } 181 182 183 #define MULTILIB_DEFAULTS { "O0" } 184 185 186 #define TARGET_VERSION fprintf (stderr, " (ZPU syntax)"); 187 188 189 #define BITS_BIG_ENDIAN TARGET_BITSBIG 190 #define BYTES_BIG_ENDIAN TARGET_BYTESBIG 191 #define WORDS_BIG_ENDIAN TARGET_BYTESBIG 192 #define BITS_PER_UNIT 8 193 #define BITS_PER_WORD 32 194 #define UNITS_PER_WORD 4 195 196 /* Define this macro if it is advisable to hold scalars in registers 197 in a wider mode than that declared by the program. In such cases, 198 the value is constrained to be within the bounds of the declared 199 type, but kept valid in the wider mode. The signedness of the 200 extension may differ from that of the type. */ 201 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 202 if (GET_MODE_CLASS (MODE) == MODE_INT \ 203 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 204 { \ 205 (MODE) = word_mode; \ 206 } 207 #define PROMOTE_FUNCTION_ARGS 208 #define PROMOTE_FUNCTION_RETURN 209 210 211 #define POINTER_SIZE BITS_PER_WORD 212 213 #define PARM_BOUNDARY BITS_PER_WORD 214 #define STACK_BOUNDARY BITS_PER_WORD 215 #define FUNCTION_BOUNDARY BITS_PER_UNIT 216 #define BIGGEST_ALIGNMENT BITS_PER_WORD 217 #define BIGGEST_FIELD_ALIGNMENT BITS_PER_WORD 218 219 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD 220 221 #define CONSTANT_ALIGNMENT(EXP, ALIGN) BITS_PER_WORD 222 #define DATA_ALIGNMENT(TYPE, ALIGN) BITS_PER_WORD 223 #define LOCAL_ALIGNMENT(TYPE, ALIGN) BITS_PER_WORD 224 225 #define STRICT_ALIGNMENT 1 226 227 #define MAX_FIXED_MODE_SIZE 32 228 229 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT 230 231 232 #define SHORT_TYPE_SIZE 16 233 #define INT_TYPE_SIZE 32 234 #define FLOAT_TYPE_SIZE 32 235 #define LONG_TYPE_SIZE BITS_PER_WORD 236 #define MAX_WCHAR_TYPE_SIZE 32 237 #define DOUBLE_TYPE_SIZE 64 238 #define LONG_LONG_TYPE_SIZE 64 239 240 #define DEFAULT_SIGNED_CHAR 0 241 242 #define DEFAULT_SHORT_ENUMS 0 243 244 #define TARGET_BELL 007 245 #define TARGET_BS 010 246 #define TARGET_TAB 011 247 #define TARGET_NEWLINE 012 248 #define TARGET_VT 013 249 #define TARGET_FF 014 250 #define TARGET_CR 015 251 252 #define R_R0 (0) 253 #define R_R1 (1) 254 #define R_R2 (2) 255 #define R_R3 (3) 256 #define R_NUM (32) 257 258 259 #define FIRST_PSEUDO_REGISTER 36 260 261 #define FIXED_REGISTERS \ 262 /*0,1,2,3,4,5,6,7 SP,PC,fp,ap*/ \ 263 { 1,1,1,1,1,1,1,1, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 1, 1, 1, 1} 264 265 #define CALL_USED_REGISTERS \ 266 /*0,1,2,3,4,5,6,7, 0,1,2,3,4,5,6,7, 0,1,2,3,4,5,6,7, 0,1,2,3,4,5,6,7,SP,PC,fp,ap*/ \ 267 { 1,0,1,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 1, 1, 1, 1} 268 269 /* KLUDGE! 270 * 271 * We don't want GCC to use the memory mapped register r0-r7. Normally it 272 * won't unless it has to. 273 * 274 * However, somewhere in GCC there is a clever mechanism to make the hard frame 275 * register availble for general allocation even though it is marked as a 276 * fixed register. 277 * 278 * Using R3(memory mapped register) is harmless, but not optimal. 279 */ 280 #define REG_ALLOC_ORDER {\ 281 8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31, \ 282 0,1,2,3,4,5,6,7, \ 283 32, 33, 34, 35 } 284 285 286 #define HARD_REGNO_NREGS(REGNO, MODE) ((GET_MODE_SIZE(MODE) + UNITS_PER_WORD -1)/UNITS_PER_WORD) 287 288 /* we only allow >32 bits in non-memory mapped registers */ 289 #define HARD_REGNO_MODE_OK(REGNO, MODE) ((REGNO>=R_STACK_REG)||(GET_MODE_SIZE(MODE)<=UNITS_PER_WORD)) 290 291 #define MODES_TIEABLE_P(MODE1, MODE2) 1 292 293 #define AVOID_CCMODE_COPIES 294 295 enum reg_class 296 { 297 NO_REGS, 298 GENERAL_REGS, 299 ALL_REGS, 300 LIM_REG_CLASSES 301 }; 302 303 #define N_REG_CLASSES (int) LIM_REG_CLASSES 304 305 #define REG_CLASS_NAMES \ 306 { "NO_REGS", \ 307 "GENERAL_REGS", \ 308 "ALL_REGS" } 309 310 #define REG_CLASS_CONTENTS \ 311 {\ 312 {0, 0}, \ 313 {0xffffff0d, 0xf}, \ 314 {0xffffff0d, 0xf}, } 315 316 #define REGNO_REG_CLASS(REGNO) (((REGNO)<FIRST_PSEUDO_REGISTER)?GENERAL_REGS:ALL_REGS) 317 #define BASE_REG_CLASS GENERAL_REGS 318 #define INDEX_REG_CLASS GENERAL_REGS 319 #define REG_CLASS_FROM_LETTER(C) NO_REGS 320 321 #define REGNO_OK_FOR_INDEX_P(REGNO) 1 322 323 #define REGNO_OK_FOR_BASE_P(REGNO) 1 324 325 #define PREFERRED_RELOAD_CLASS(X,CLASS) GENERAL_REGS 326 327 /* #define SMALL_REGISTER_CLASSES 0 */ 328 329 /* #define CLASS_LIKELY_SPILLED_P(class) 1 */ 330 331 #define CLASS_MAX_NREGS(CLASS, MODE) HARD_REGNO_NREGS(CLASS, MODE) 332 333 #define CONST_OK_FOR_LETTER_P(VALUE, C) 0 334 335 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0 336 337 #define EXTRA_CONSTRAINT(X, C) 0 338 #define EXTRA_MEMORY_CONSTRAINT(C,STR) 0 339 #define EXTRA_ADDRESS_CONSTRAINT(C,STR) 0 340 341 #define STACK_GROWS_DOWNWARD 342 #undef ARGS_GROW_DOWNWARD 343 344 345 /* By letting the frame grow downwards, we'll have the 346 * final stack slot assignments, the pseudo registers, 347 * with the smallest offsets. This has a major impact 348 * on code size 349 */ 350 #define FRAME_GROWS_DOWNWARD 351 352 353 #define STARTING_FRAME_OFFSET 0 354 355 #define FIRST_PARM_OFFSET(FUNDECL) (0) 356 357 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) ((COUNT) == 0 \ 358 ? zpu_return_addr_rtx() \ 359 : NULL_RTX) 360 361 /* rtx for return address *before* prologue */ 362 #define INCOMING_RETURN_ADDR_RTX \ 363 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) 364 365 #define INCOMING_FRAME_SP_OFFSET 4 366 367 368 369 #define STACK_POINTER_REGNUM R_SP 370 371 /* this will be eliminated. The magic trick here is to use a "fake frame pointer" that 372 * is eliminated. 373 * 374 * Additional voodoo is to have the hard frame pointer late amongst the registers 375 * so it isn't allocated when it is impossible to replace the 376 * frame pointer with the stack pointer. 377 * 378 * It would be disaterous not to eliminate R_FAKE_FP, since it 379 * doesn't actually exist 380 */ 381 #define FRAME_POINTER_REGNUM R_FAKE_FP 382 #define HARD_FRAME_POINTER_REGNUM R_R3 383 384 /* this will be eliminated*/ 385 #define ARG_POINTER_REGNUM R_FAKE_AP 386 387 #define STATIC_CHAIN_REGNUM R_R2 388 389 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca || current_function_has_nonlocal_goto) 390 391 #define ELIMINABLE_REGS { \ 392 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 393 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 394 {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 395 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} \ 396 } 397 398 /* avoid reload happily eliminating the arg pointer when 399 * the frame pointer can't be eliminted. 400 */ 401 #define CAN_ELIMINATE(FROM, TO) \ 402 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1) 403 404 #define INITIAL_ELIMINATION_OFFSET(from_reg,to_reg,offset) {offset=zpu_initial_elimination_offset(from_reg, to_reg);} 405 406 #define HAVE_POST_INCREMENT 1 407 408 #define HAVE_PRE_DECREMENT 1 409 410 #define PROMOTE_PROTOTYPES 1 411 412 #define ACCUMULATE_OUTGOING_ARGS 1 413 414 /* What does GCC do differently if we tell it that these registers are part of a 415 * register window? 416 */ 417 #define LOCAL_REGNO(REGNO) (((REGNO) >= R_STACK_REG) && ((REGNO) <= R_STACK_REG_LAST)) 418 419 420 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 421 422 423 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0 424 425 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 426 427 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) 0 428 429 typedef struct { 430 /* The first arg_regno free after scanning the arguments so far. */ 431 int lst_free_reg; 432 433 /* The flag set by FUNCTION_ARG_PRESCAN saying we dont want to pass 434 anything in registers for current call. */ 435 int must_pass_in_stack; 436 } CUMULATIVE_ARGS; 437 438 439 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) 440 441 #define RESET_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME) 442 443 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) 444 445 #define FUNCTION_ARG_REGNO_P(REGNO) 0 446 447 #define FUNCTION_VALUE(VALTYPE, FUNC) gen_rtx (REG, TYPE_MODE (VALTYPE), R_R0) 448 449 #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, R_R0) 450 451 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == R_R0 ) 452 453 454 455 #define STRUCT_VALUE 0 456 #define STRUCT_VALUE_INCOMING 0 457 458 459 #define FUNCTION_PROFILER(FILE, LABELNO) 460 461 #define NO_PROFILE_COUNTERS 1 462 463 464 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) {} 465 466 467 /* Linktime relaxing is not an issue here w.r.t. making 468 * sure that the trampoline is of constant size. Firstly 469 * the trampoline template is placed in the read-only segment, so 470 * there is no link-time relaxing, secondly, the machine code 471 * below does not use any relaxable relocations. 472 * 473 * The fun part here is that we have to save & restore 474 * the static chain register without screwing up the stack frame. 475 * 476 * We poke the return address to return to the trampoline in order to 477 * restore the static chain register. 478 * 479 */ 480 #define TRAMPOLINE_TEMPLATE(FILE) \ 481 { \ 482 fprintf ((FILE), "; save return address\n"); \ 483 fprintf ((FILE), " nop\n"); \ 484 fprintf ((FILE), " nop\n"); \ 485 fprintf ((FILE), " nop\n"); \ 486 fprintf ((FILE), " nop\n"); \ 487 fprintf ((FILE), "; save static chain register\n"); \ 488 fprintf ((FILE), " nop\n"); \ 489 fprintf ((FILE), " nop\n"); \ 490 fprintf ((FILE), " nop\n"); \ 491 fprintf ((FILE), " nop\n"); \ 492 fprintf ((FILE), "; load static chain register\n"); \ 493 fprintf ((FILE), " pushpc ; 24 \n"); \ 494 fprintf ((FILE), " im 4+24\n"); \ 495 fprintf ((FILE), " add\n"); \ 496 fprintf ((FILE), " load\n"); \ 497 fprintf ((FILE), " im %d\n", STATIC_CHAIN_REGNUM*4); \ 498 fprintf ((FILE), " store\n"); \ 499 fprintf ((FILE), "; call function\n"); \ 500 fprintf ((FILE), " pushpc ; 18\n"); \ 501 fprintf ((FILE), " im 18\n"); \ 502 fprintf ((FILE), " add\n"); \ 503 fprintf ((FILE), " load\n"); \ 504 fprintf ((FILE), " poppc\n"); \ 505 fprintf ((FILE), "; restore static chain register\n"); \ 506 fprintf ((FILE), " nop\n"); \ 507 fprintf ((FILE), " nop\n"); \ 508 fprintf ((FILE), " nop\n"); \ 509 fprintf ((FILE), " nop\n"); \ 510 fprintf ((FILE), " nop\n"); \ 511 fprintf ((FILE), "; return to original caller\n"); \ 512 fprintf ((FILE), " nop\n"); \ 513 fprintf ((FILE), " nop\n"); \ 514 fprintf ((FILE), " nop\n"); \ 515 fprintf ((FILE), " nop\n"); \ 516 fprintf ((FILE), " nop\n"); \ 517 fprintf ((FILE), " nop\n"); \ 518 fprintf ((FILE), " nop\n"); \ 519 fprintf ((FILE), " nop\n"); \ 520 fprintf ((FILE), " .long 0 ; address\n"); \ 521 fprintf ((FILE), " .long 0 ; static chain value\n"); \ 522 fprintf ((FILE), " .long 0 ; save area for static chain register\n"); \ 523 fprintf ((FILE), " .long 0 ; saved return address\n"); \ 524 } 525 526 #define TRAMPOLINE_SIZE (32+16) 527 /* The alignment of a trampoline, in bits. */ 528 #define TRAMPOLINE_ALIGNMENT 32 529 530 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 531 { \ 532 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 32+4)), \ 533 (CXT)); \ 534 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 32+0)), \ 535 (FNADDR)); \ 536 } 537 538 539 #define TARGET_MEM_FUNCTIONS 540 541 #define CONSTANT_ADDRESS_P(X) CONSTANT_P(X) 542 543 /* reload can fail if we use more. This limit does not 544 * apply to PC/SP. Reducing this from 10 to 2 had no measureable 545 * impact on code size. 546 */ 547 #define MAX_REGS_PER_ADDRESS 2 548 549 550 #ifdef REG_OK_STRICT 551 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) {if (zpu_legitimate_address(MODE, X, 1)) goto LABEL;} 552 /* Nonzero if X is a hard reg that can be used as a base reg. */ 553 #define REG_OK_FOR_BASE_P(X) (REGNO(X)<FIRST_PSEUDO_REGISTER) 554 #else 555 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) {if (zpu_legitimate_address(MODE, X, 0)) goto LABEL;} 556 /* Nonzero if X is a hard reg that can be used as a base reg 557 or if it is a pseudo reg. */ 558 #define REG_OK_FOR_BASE_P(X) 1 559 #endif 560 561 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X) 562 563 564 #define LEGITIMIZE_ADDRESS(x, oldx, mode, win) 565 566 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ 567 if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL 568 569 570 #define LEGITIMATE_CONSTANT_P(X) 1 571 572 /* We need to print registers here as they are valid addresses 573 * that can be sent to __asm() blocks as arguments 574 */ 575 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \ 576 {\ 577 if (GET_CODE (X) == REG) \ 578 { \ 579 print_operand(STREAM, X, 0); \ 580 } \ 581 else \ 582 goto FAIL; \ 583 } 584 585 #define NOTICE_UPDATE_CC(exp, insn) CC_STATUS_INIT 586 587 588 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) 4 589 590 #define MEMORY_MOVE_COST(MODE,CLASS,IN) 1 591 592 #define BRANCH_COST 2 593 #define SLOW_BYTE_ACCESS 1 594 #define MOVE_RATIO (1+1) 595 #define NO_FUNCTION_CSE 1 596 #define NO_RECURSIVE_FUNCTION_CSE 1 597 598 599 #define TEXT_SECTION_ASM_OP ".text" 600 #define DATA_SECTION_ASM_OP ".data" 601 602 #define BSS_SECTION_ASM_OP ".bss" 603 604 605 #define ASM_COMMENT_START "//" 606 #define ASM_APP_ON "" 607 #define ASM_APP_OFF "" 608 609 #define REGISTER_NAMES \ 610 { "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \ 611 "R8", "R9", "R10","R11","R12","R13","R14","R15", \ 612 "R16","R17","R18","R19","R20","R21","R22","R23", \ 613 "R24","R25","R26","R27","R28","R29","R30","R31", \ 614 "SP","PC", "*FAKEFRAMEPOINTER", "*FAKEARGPOINTER"} 615 616 617 #define PRINT_OPERAND(STREAM, X, CODE) print_operand(STREAM, X, CODE) 618 619 #define PRINT_OPERAND_ADDRESS(STREAM, X) \ 620 output_addr_const (STREAM, X); 621 622 623 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) fprintf(STREAM, "im %d\nload\n", REGNO*4) 624 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) fprintf(STREAM, "im %d\nstore\n", REGNO*4) 625 626 /* This is how to output an element of a case-vector that is absolute. */ 627 628 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 629 fprintf (FILE, "\t.long .L%d\n", VALUE) 630 631 /* This is how to output an element of a case-vector that is relative. */ 632 633 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 634 fprintf (FILE, "\t.long .L%d-.L%d\n", VALUE, REL) 635 636 637 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \ 638 fprintf (STREAM, "\t.balign %u;\n", 1 << (POWER)); 639 640 #define DBX_REGISTER_NUMBER(REGNO) (REGNO) 641 642 643 #define CASE_VECTOR_MODE SImode 644 645 646 #define CASE_VECTOR_PC_RELATIVE 0 647 648 649 #define WORD_REGISTER_OPERATIONS 650 651 652 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 653 654 #define MOVE_MAX UNITS_PER_WORD 655 656 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 657 658 #define STORE_FLAG_VALUE 1 659 660 661 #define Pmode SImode 662 663 #define FUNCTION_MODE QImode 664 665 #define WORKSPACE_RESERVED_BYTES (7 * UNITS_PER_WORD) 666 667 #define IN_WORDS(SIZE_IN_BYTES) \ 668 (((SIZE_IN_BYTES) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 669 670 #define WORD_ROUND(VALUE) \ 671 (((VALUE) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD) 672 673 #define FLOAT_OPERAND(N) \ 674 (GET_MODE_CLASS (GET_MODE (operands[N])) == MODE_FLOAT) 675 676 extern 677 struct zpu_compare { 678 struct rtx_def *op[2]; /* comparison operands */ 679 int fp; /* floating comparison required */ 680 } zpu_compare; 681 682 /* Point that a function's arguments should be processed (in calls.c) 683 from last to first, so that the integer regstack will be in the 684 proper order before a call insn; no stack rearrangement will be needed. 685 It is not quite right to define this macro here as it was not 686 intended for user redefinition, but this yields the desired effect. */ 687 688 #define PUSH_ARGS_REVERSED 1 /* If it's last to first */ 689 690 691 692 /* This is called before generating rtl for every function. */ 693 694 #define INIT_EXPANDERS 695 696 697 698 699 #define TARGET_CPU_CPP_BUILTINS() \ 700 do \ 701 { \ 702 builtin_define_std ("zpu"); \ 703 } \ 704 while (0) 705 706 707 #define GLOBAL_ASM_OP "\t.globl\t" 708 709 710 /* we use setjmp/longjmp for C++ exception handling... */ 711 #define DWARF2_UNWIND_INFO 0 712 713 /* ZPU hack! We have modified GCC to allow -fomit-frame-pointer to be more powerful */ 714 #define ALLOW_REF_TO_SP_IN_CHANGE_SP_INSN 1 715 716 717 #undef DBX_OUTPUT_MAIN_SOURCE_FILE_END 718 #define DBX_OUTPUT_MAIN_SOURCE_FILE_END(FILE, FILENAME) \ 719 fprintf (FILE, \ 720 "\t.text\n.stabs \"\",%d,0,0,.Letext\n.Letext:\n", N_SO) 721 722 723 /* see config/mips/elf.h */ 724 725 /* Use __main method of constructor invocation. */ 726 #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section 727 /* On elf, we *do* have support for the .init and .fini sections, and we 728 can put stuff in there to be executed before and after `main'. We let 729 crtstuff.c and other files know this by defining the following symbols. 730 The definitions say how to change sections to the .init and .fini 731 sections. This is the same for all known elf assemblers. */ 732 733 #undef INIT_SECTION_ASM_OP 734 #define INIT_SECTION_ASM_OP "\t.section\t.init" 735 #undef FINI_SECTION_ASM_OP 736 #define FINI_SECTION_ASM_OP "\t.section\t.fini" 737 738 739 #undef ASM_APP_ON 740 #define ASM_APP_ON "#APP\n" 741 742 #undef ASM_APP_OFF 743 #define ASM_APP_OFF "#NO_APP\n" 744