1:option:::insn-bit-size:16
2:option:::hi-bit-nr:15
3
4
5:option:::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X
6:option:::format-names:XI,XII,XIII
7:option:::format-names:XIV,XV
8:option:::format-names:Z
9
10
11:model:::v850:v850:
12
13:option:::multi-sim:true
14:model:::v850e:v850e:
15:option:::multi-sim:true
16:model:::v850e1:v850e1:
17
18// Cache macros
19
20:cache:::unsigned:reg1:RRRRR:(RRRRR)
21:cache:::unsigned:reg2:rrrrr:(rrrrr)
22:cache:::unsigned:reg3:wwwww:(wwwww)
23
24:cache:::unsigned:disp4:dddd:(dddd)
25:cache:::unsigned:disp5:dddd:(dddd << 1)
26:cache:::unsigned:disp7:ddddddd:ddddddd
27:cache:::unsigned:disp8:ddddddd:(ddddddd << 1)
28:cache:::unsigned:disp8:dddddd:(dddddd << 2)
29:cache:::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
30:cache:::unsigned:disp16:dddddddddddddddd:EXTEND16 (dddddddddddddddd)
31:cache:::unsigned:disp16:ddddddddddddddd: EXTEND16 (ddddddddddddddd << 1)
32:cache:::unsigned:disp22:dddddd,ddddddddddddddd: SEXT32 ((dddddd << 16) + (ddddddddddddddd << 1), 22 - 1)
33
34:cache:::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
35:cache:::unsigned:imm6:iiiiii:iiiiii
36:cache:::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1)
37:cache:::unsigned:imm5:iiii:(32 - (iiii << 1))
38:cache:::unsigned:simm16:iiiiiiiiiiiiiiii:EXTEND16 (iiiiiiiiiiiiiiii)
39:cache:::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
40:cache:::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
41:cache:::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)
42
43:cache:::unsigned:vector:iiiii:iiiii
44
45:cache:::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL)
46:cache:::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL)
47
48:cache:::unsigned:bit3:bbb:bbb
49
50
51// What do we do with an illegal instruction?
52:internal::::illegal:
53{
54  sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
55		  (unsigned long) cia);
56  sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
57}
58
59
60
61// Add
62
63rrrrr,001110,RRRRR:I:::add
64"add r<reg1>, r<reg2>"
65{
66  COMPAT_1 (OP_1C0 ());
67}
68
69rrrrr,010010,iiiii:II:::add
70"add <imm5>,r<reg2>"
71{
72  COMPAT_1 (OP_240 ());
73}
74
75
76
77// ADDI
78rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi
79"addi <simm16>, r<reg1>, r<reg2>"
80{
81  COMPAT_2 (OP_600 ());
82}
83
84
85
86// AND
87rrrrr,001010,RRRRR:I:::and
88"and r<reg1>, r<reg2>"
89{
90  COMPAT_1 (OP_140 ());
91}
92
93
94
95// ANDI
96rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
97"andi <uimm16>, r<reg1>, r<reg2>"
98{
99  COMPAT_2 (OP_6C0 ());
100}
101
102
103
104// Map condition code to a string
105:%s::::cccc:int cccc
106{
107  switch (cccc)
108    {
109    case 0xf: return "gt";
110    case 0xe: return "ge";
111    case 0x6: return "lt";
112
113    case 0x7: return "le";
114
115    case 0xb: return "h";
116    case 0x9: return "nl";
117    case 0x1: return "l";
118
119    case 0x3: return "nh";
120
121    case 0x2: return "e";
122
123    case 0xa: return "ne";
124
125    case 0x0: return "v";
126    case 0x8: return "nv";
127    case 0x4: return "n";
128    case 0xc: return "p";
129      /* case 0x1: return "c"; */
130      /* case 0x9: return "nc"; */
131      /* case 0x2: return "z"; */
132      /* case 0xa: return "nz"; */
133    case 0x5: return "r"; /* always */
134    case 0xd: return "sa";
135    }
136  return "(null)";
137}
138
139
140// Bcond
141ddddd,1011,ddd,cccc:III:::Bcond
142"b%s<cccc> <disp9>"
143{
144  int cond;
145  if ((ddddd == 0x00) && (ddd == 0x00) && (cccc == 0x05)) {
146    // Special case - treat "br *" like illegal instruction
147    sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
148  } else {
149    cond = condition_met (cccc);
150    if (cond)
151      nia = cia + disp9;
152    TRACE_BRANCH1 (cond);
153  }
154}
155
156
157
158// BSH
159rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
160*v850e
161*v850e1
162"bsh r<reg2>, r<reg3>"
163{
164  unsigned32 value;
165  TRACE_ALU_INPUT1 (GR[reg2]);
166
167  value = (MOVED32 (GR[reg2], 23, 16, 31, 24)
168	   | MOVED32 (GR[reg2], 31, 24, 23, 16)
169	   | MOVED32 (GR[reg2], 7, 0, 15, 8)
170	   | MOVED32 (GR[reg2], 15, 8, 7, 0));
171
172  GR[reg3] = value;
173  PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
174  if (value == 0) PSW |= PSW_Z;
175  if (value & 0x80000000) PSW |= PSW_S;
176  if (((value & 0xff) == 0) || (value & 0x00ff) == 0) PSW |= PSW_CY;
177
178  TRACE_ALU_RESULT (GR[reg3]);
179}
180
181// BSW
182rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
183*v850e
184*v850e1
185"bsw r<reg2>, r<reg3>"
186{
187#define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
188  unsigned32 value;
189  TRACE_ALU_INPUT1 (GR[reg2]);
190
191  value = GR[reg2];
192  value >>= 24;
193  value |= (GR[reg2] << 24);
194  value |= ((GR[reg2] << 8) & 0x00ff0000);
195  value |= ((GR[reg2] >> 8) & 0x0000ff00);
196  GR[reg3] = value;
197
198  PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
199
200  if (value == 0) PSW |= PSW_Z;
201  if (value & 0x80000000) PSW |= PSW_S;
202  if (WORDHASNULLBYTE (value)) PSW |= PSW_CY;
203
204  TRACE_ALU_RESULT (GR[reg3]);
205}
206
207// CALLT
2080000001000,iiiiii:II:::callt
209*v850e
210*v850e1
211"callt <imm6>"
212{
213  unsigned32 adr;
214  unsigned32 off;
215  CTPC  = cia + 2;
216  CTPSW = PSW;
217  adr = (CTBP & ~1) + (imm6 << 1);
218  off = load_mem (adr, 2) & ~1; /* Force alignment */
219  nia = (CTBP & ~1) + off;
220  TRACE_BRANCH3 (adr, CTBP, off);
221}
222
223
224// CLR1
22510,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1
226"clr1 <bit3>, <disp16>[r<reg1>]"
227{
228  COMPAT_2 (OP_87C0 ());
229}
230
231rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
232*v850e
233*v850e1
234"clr1 r<reg2>, [r<reg1>]"
235{
236  COMPAT_2 (OP_E407E0 ());
237}
238
239
240// CTRET
2410000011111100000 + 0000000101000100:X:::ctret
242*v850e
243*v850e1
244"ctret"
245{
246  nia  = (CTPC & ~1);
247  PSW = (CTPSW & (CPU)->psw_mask);
248  TRACE_BRANCH1 (PSW);
249}
250
251// CMOV
252rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
253*v850e
254*v850e1
255"cmov %s<cccc>, r<reg1>, r<reg2>, r<reg3>"
256{
257  int cond = condition_met (cccc);
258  TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]);
259  GR[reg3] = cond ? GR[reg1] : GR[reg2];
260  TRACE_ALU_RESULT (GR[reg3]);
261}
262
263rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
264*v850e
265*v850e1
266"cmov %s<cccc>, <imm5>, r<reg2>, r<reg3>"
267{
268  int cond = condition_met (cccc);
269  TRACE_ALU_INPUT3 (cond, imm5, GR[reg2]);
270  GR[reg3] = cond ? imm5 : GR[reg2];
271  TRACE_ALU_RESULT (GR[reg3]);
272}
273
274// CMP
275rrrrr,001111,RRRRR:I:::cmp
276"cmp r<reg1>, r<reg2>"
277{
278  COMPAT_1 (OP_1E0 ());
279}
280
281rrrrr,010011,iiiii:II:::cmp
282"cmp <imm5>, r<reg2>"
283{
284  COMPAT_1 (OP_260 ());
285}
286
287
288
289// DI
2900000011111100000 + 0000000101100000:X:::di
291"di"
292{
293  COMPAT_2 (OP_16007E0 ());
294}
295
296
297
298// DISPOSE
299// 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose
300// "dispose <imm5>, <list12>"
3010000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose
302*v850e
303*v850e1
304"dispose <imm5>, <list12>":RRRRR == 0
305"dispose <imm5>, <list12>, [reg1]"
306{
307  int i;
308  SAVE_2;
309
310  trace_input ("dispose", OP_PUSHPOP1, 0);
311
312  SP += (OP[3] & 0x3e) << 1;
313
314  /* Load the registers with lower number registers being retrieved
315     from higher addresses.  */
316  for (i = 12; i--;)
317    if ((OP[3] & (1 << type1_regs[ i ])))
318      {
319	State.regs[ 20 + i ] = load_mem (SP, 4);
320	SP += 4;
321      }
322
323  if ((OP[3] & 0x1f0000) != 0)
324    {
325      nia = State.regs[ (OP[3] >> 16) & 0x1f];
326    }
327
328  trace_output (OP_PUSHPOP1);
329}
330
331
332// DIV
333rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
334*v850e
335*v850e1
336"div r<reg1>, r<reg2>, r<reg3>"
337{
338  COMPAT_2 (OP_2C007E0 ());
339}
340
341
342// DIVH
343rrrrr!0,000010,RRRRR!0:I:::divh
344"divh r<reg1>, r<reg2>"
345{
346  unsigned32 ov, s, z;
347  signed long int op0, op1, result;
348
349  trace_input ("divh", OP_REG_REG, 0);
350
351  PC = cia;
352  OP[0] = instruction_0 & 0x1f;
353  OP[1] = (instruction_0 >> 11) & 0x1f;
354
355  /* Compute the result.  */
356  op0 = EXTEND16 (State.regs[OP[0]]);
357  op1 = State.regs[OP[1]];
358
359  if (op0 == 0xffffffff && op1 == 0x80000000)
360    {
361      result = 0x80000000;
362      ov = 1;
363    }
364  else if (op0 != 0)
365    {
366      result = op1 / op0;
367      ov = 0;
368    }
369  else
370    {
371      result = 0x0;
372      ov = 1;
373    }
374
375  /* Compute the condition codes.  */
376  z = (result == 0);
377  s = (result & 0x80000000);
378
379  /* Store the result and condition codes.  */
380  State.regs[OP[1]] = result;
381  PSW &= ~(PSW_Z | PSW_S | PSW_OV);
382  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (ov ? PSW_OV : 0));
383
384  trace_output (OP_REG_REG);
385
386  PC += 2;
387  nia = PC;
388}
389
390rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
391*v850e
392*v850e1
393"divh r<reg1>, r<reg2>, r<reg3>"
394{
395  COMPAT_2 (OP_28007E0 ());
396}
397
398
399// DIVHU
400rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
401*v850e
402*v850e1
403"divhu r<reg1>, r<reg2>, r<reg3>"
404{
405  COMPAT_2 (OP_28207E0 ());
406}
407
408
409// DIVU
410rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
411*v850e
412*v850e1
413"divu r<reg1>, r<reg2>, r<reg3>"
414{
415  COMPAT_2 (OP_2C207E0 ());
416}
417
418
419// EI
4201000011111100000 + 0000000101100000:X:::ei
421"ei"
422{
423  COMPAT_2 (OP_16087E0 ());
424}
425
426
427
428// HALT
4290000011111100000 + 0000000100100000:X:::halt
430"halt"
431{
432  COMPAT_2 (OP_12007E0 ());
433}
434
435
436
437// HSW
438rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
439*v850e
440*v850e1
441"hsw r<reg2>, r<reg3>"
442{
443  unsigned32 value;
444  TRACE_ALU_INPUT1 (GR[reg2]);
445
446  value = GR[reg2];
447  value >>= 16;
448  value |= (GR[reg2] << 16);
449
450  GR[reg3] = value;
451
452  PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
453
454  if (value == 0) PSW |= PSW_Z;
455  if (value & 0x80000000) PSW |= PSW_S;
456  if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;
457
458  TRACE_ALU_RESULT (GR[reg3]);
459}
460
461
462
463// JARL
464rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
465"jarl <disp22>, r<reg2>"
466{
467  GR[reg2] = nia;
468  nia = cia + disp22;
469  TRACE_BRANCH1 (GR[reg2]);
470}
471
472
473
474// JMP
47500000000011,RRRRR:I:::jmp
476"jmp [r<reg1>]"
477{
478  nia = GR[reg1] & ~1;
479  TRACE_BRANCH0 ();
480}
481
482
483
484// JR
4850000011110,dddddd + ddddddddddddddd,0:V:::jr
486"jr <disp22>"
487{
488  nia = cia + disp22;
489  TRACE_BRANCH0 ();
490}
491
492
493
494// LD
495rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
496"ld.b <disp16>[r<reg1>], r<reg2>"
497{
498  COMPAT_2 (OP_700 ());
499}
500
501rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
502"ld.h <disp16>[r<reg1>], r<reg2>"
503{
504  COMPAT_2 (OP_720 ());
505}
506
507rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
508"ld.w <disp16>[r<reg1>], r<reg2>"
509{
510  COMPAT_2 (OP_10720 ());
511}
512
513rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
514*v850e
515*v850e1
516"ld.bu <disp16>[r<reg1>], r<reg2>"
517{
518  COMPAT_2 (OP_10780 ());
519}
520
521rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
522*v850e
523*v850e1
524"ld.hu <disp16>[r<reg1>], r<reg2>"
525{
526  COMPAT_2 (OP_107E0 ());
527}
528
529
530// LDSR
531regID,111111,RRRRR + 0000000000100000:IX:::ldsr
532"ldsr r<reg1>, s<regID>"
533{
534  TRACE_ALU_INPUT1 (GR[reg1]);
535
536  if (&PSW == &SR[regID])
537    PSW = (GR[reg1] & (CPU)->psw_mask);
538  else
539    SR[regID] = GR[reg1];
540
541  TRACE_ALU_RESULT (SR[regID]);
542}
543
544
545
546// MOV
547rrrrr!0,000000,RRRRR:I:::mov
548"mov r<reg1>, r<reg2>"
549{
550  TRACE_ALU_INPUT0 ();
551  GR[reg2] = GR[reg1];
552  TRACE_ALU_RESULT (GR[reg2]);
553}
554
555
556rrrrr!0,010000,iiiii:II:::mov
557"mov <imm5>, r<reg2>"
558{
559  COMPAT_1 (OP_200 ());
560}
561
56200000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov
563*v850e
564*v850e1
565"mov <imm32>, r<reg1>"
566{
567  SAVE_2;
568  trace_input ("mov", OP_IMM_REG, 4);
569  State.regs[ OP[0] ] = load_mem (PC + 2, 4);
570  trace_output (OP_IMM_REG);
571}
572
573
574
575// MOVEA
576rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea
577"movea <simm16>, r<reg1>, r<reg2>"
578{
579  TRACE_ALU_INPUT2 (GR[reg1], simm16);
580  GR[reg2] = GR[reg1] + simm16;
581  TRACE_ALU_RESULT (GR[reg2]);
582}
583
584
585
586// MOVHI
587rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi
588"movhi <uimm16>, r<reg1>, r<reg2>"
589{
590  COMPAT_2 (OP_640 ());
591}
592
593
594
595// MUL
596rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
597*v850e
598*v850e1
599"mul r<reg1>, r<reg2>, r<reg3>"
600{
601  COMPAT_2 (OP_22007E0 ());
602}
603
604rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul
605*v850e
606*v850e1
607"mul <imm9>, r<reg2>, r<reg3>"
608{
609  COMPAT_2 (OP_24007E0 ());
610}
611
612
613// MULH
614rrrrr!0,000111,RRRRR:I:::mulh
615"mulh r<reg1>, r<reg2>"
616{
617  COMPAT_1 (OP_E0 ());
618}
619
620rrrrr!0,010111,iiiii:II:::mulh
621"mulh <imm5>, r<reg2>"
622{
623  COMPAT_1 (OP_2E0 ());
624}
625
626
627
628// MULHI
629rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi
630"mulhi <uimm16>, r<reg1>, r<reg2>"
631{
632  COMPAT_2 (OP_6E0 ());
633}
634
635
636
637// MULU
638rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
639*v850e
640*v850e1
641"mulu r<reg1>, r<reg2>, r<reg3>"
642{
643  COMPAT_2 (OP_22207E0 ());
644}
645
646rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
647*v850e
648*v850e1
649"mulu <imm9>, r<reg2>, r<reg3>"
650{
651  COMPAT_2 (OP_24207E0 ());
652}
653
654
655
656// NOP
6570000000000000000:I:::nop
658"nop"
659{
660  /* do nothing, trace nothing */
661}
662
663
664
665// NOT
666rrrrr,000001,RRRRR:I:::not
667"not r<reg1>, r<reg2>"
668{
669  COMPAT_1 (OP_20 ());
670}
671
672
673
674// NOT1
67501,bbb,111110,RRRRR + dddddddddddddddd:VIII:::not1
676"not1 <bit3>, <disp16>[r<reg1>]"
677{
678  COMPAT_2 (OP_47C0 ());
679}
680
681rrrrr,111111,RRRRR + 0000000011100010:IX:::not1
682*v850e
683*v850e1
684"not1 r<reg2>, r<reg1>"
685{
686  COMPAT_2 (OP_E207E0 ());
687}
688
689
690
691// OR
692rrrrr,001000,RRRRR:I:::or
693"or r<reg1>, r<reg2>"
694{
695  COMPAT_1 (OP_100 ());
696}
697
698
699
700// ORI
701rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
702"ori <uimm16>, r<reg1>, r<reg2>"
703{
704  COMPAT_2 (OP_680 ());
705}
706
707
708
709// PREPARE
7100000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare
711*v850e
712*v850e1
713"prepare <list12>, <imm5>"
714{
715  int  i;
716  SAVE_2;
717
718  trace_input ("prepare", OP_PUSHPOP1, 0);
719
720  /* Store the registers with lower number registers being placed at
721     higher addresses.  */
722  for (i = 0; i < 12; i++)
723    if ((OP[3] & (1 << type1_regs[ i ])))
724      {
725	SP -= 4;
726	store_mem (SP, 4, State.regs[ 20 + i ]);
727      }
728
729  SP -= (OP[3] & 0x3e) << 1;
730
731  trace_output (OP_PUSHPOP1);
732}
733
734
7350000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00
736*v850e
737*v850e1
738"prepare <list12>, <imm5>, sp"
739{
740  COMPAT_2 (OP_30780 ());
741}
742
7430000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01
744*v850e
745*v850e1
746"prepare <list12>, <imm5>, <uimm16>"
747{
748  COMPAT_2 (OP_B0780 ());
749}
750
7510000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10
752*v850e
753*v850e1
754"prepare <list12>, <imm5>, <uimm16>"
755{
756  COMPAT_2 (OP_130780 ());
757}
758
7590000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11
760*v850e
761*v850e1
762"prepare <list12>, <imm5>, <uimm32>"
763{
764  COMPAT_2 (OP_1B0780 ());
765}
766
767
768
769// RETI
7700000011111100000 + 0000000101000000:X:::reti
771"reti"
772{
773  if ((PSW & PSW_EP))
774    {
775      nia = (EIPC & ~1);
776      PSW = EIPSW;
777    }
778  else if ((PSW & PSW_NP))
779    {
780      nia = (FEPC & ~1);
781      PSW = FEPSW;
782    }
783  else
784    {
785      nia = (EIPC & ~1);
786      PSW = EIPSW;
787    }
788  TRACE_BRANCH1 (PSW);
789}
790
791
792
793// SAR
794rrrrr,111111,RRRRR + 0000000010100000:IX:::sar
795"sar r<reg1>, r<reg2>"
796{
797  COMPAT_2 (OP_A007E0 ());
798}
799
800rrrrr,010101,iiiii:II:::sar
801"sar <imm5>, r<reg2>"
802{
803  COMPAT_1 (OP_2A0 ());
804}
805
806
807
808// SASF
809rrrrr,1111110,cccc + 0000001000000000:IX:::sasf
810*v850e
811*v850e1
812"sasf %s<cccc>, r<reg2>"
813{
814  COMPAT_2 (OP_20007E0 ());
815}
816
817
818
819
820// SATADD
821rrrrr!0,000110,RRRRR:I:::satadd
822"satadd r<reg1>, r<reg2>"
823{
824  COMPAT_1 (OP_C0 ());
825}
826
827rrrrr!0,010001,iiiii:II:::satadd
828"satadd <imm5>, r<reg2>"
829{
830  COMPAT_1 (OP_220 ());
831}
832
833
834
835// SATSUB
836rrrrr!0,000101,RRRRR:I:::satsub
837"satsub r<reg1>, r<reg2>"
838{
839  COMPAT_1 (OP_A0 ());
840}
841
842
843
844// SATSUBI
845rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi
846"satsubi <simm16>, r<reg1>, r<reg2>"
847{
848  COMPAT_2 (OP_660 ());
849}
850
851
852
853// SATSUBR
854rrrrr!0,000100,RRRRR:I:::satsubr
855"satsubr r<reg1>, r<reg2>"
856{
857  COMPAT_1 (OP_80 ());
858}
859
860
861
862// SETF
863rrrrr,1111110,cccc + 0000000000000000:IX:::setf
864"setf %s<cccc>, r<reg2>"
865{
866  COMPAT_2 (OP_7E0 ());
867}
868
869
870
871// SET1
87200,bbb,111110,RRRRR + dddddddddddddddd:VIII:::set1
873"set1 <bit3>, <disp16>[r<reg1>]"
874{
875  COMPAT_2 (OP_7C0 ());
876}
877
878rrrrr,111111,RRRRR + 0000000011100000:IX:::set1
879*v850e
880*v850e1
881"set1 r<reg2>, [r<reg1>]"
882{
883  COMPAT_2 (OP_E007E0 ());
884}
885
886
887
888// SHL
889rrrrr,111111,RRRRR + 0000000011000000:IX:::shl
890"shl r<reg1>, r<reg2>"
891{
892  COMPAT_2 (OP_C007E0 ());
893}
894
895rrrrr,010110,iiiii:II:::shl
896"shl <imm5>, r<reg2>"
897{
898  COMPAT_1 (OP_2C0 ());
899}
900
901
902
903// SHR
904rrrrr,111111,RRRRR + 0000000010000000:IX:::shr
905"shr r<reg1>, r<reg2>"
906{
907  COMPAT_2 (OP_8007E0 ());
908}
909
910rrrrr,010100,iiiii:II:::shr
911"shr <imm5>, r<reg2>"
912{
913  COMPAT_1 (OP_280 ());
914}
915
916
917
918// SLD
919rrrrr,0110,ddddddd:IV:::sld.b
920"sld.bu <disp7>[ep], r<reg2>":(PSW & PSW_US)
921"sld.b <disp7>[ep], r<reg2>"
922{
923  unsigned32 addr = EP + disp7;
924  unsigned32 result = load_mem (addr, 1);
925  if (PSW & PSW_US)
926    {
927      GR[reg2] = result;
928      TRACE_LD_NAME ("sld.bu", addr, result);
929    }
930  else
931    {
932      result = EXTEND8 (result);
933      GR[reg2] = result;
934      TRACE_LD (addr, result);
935    }
936}
937
938rrrrr,1000,ddddddd:IV:::sld.h
939"sld.hu <disp8>[ep], r<reg2>":(PSW & PSW_US)
940"sld.h <disp8>[ep], r<reg2>"
941{
942  unsigned32 addr = EP + disp8;
943  unsigned32 result = load_mem (addr, 2);
944  if (PSW & PSW_US)
945    {
946      GR[reg2] = result;
947      TRACE_LD_NAME ("sld.hu", addr, result);
948    }
949  else
950    {
951      result = EXTEND16 (result);
952      GR[reg2] = result;
953      TRACE_LD (addr, result);
954    }
955}
956
957rrrrr,1010,dddddd,0:IV:::sld.w
958"sld.w <disp8>[ep], r<reg2>"
959{
960  unsigned32 addr = EP + disp8;
961  unsigned32 result = load_mem (addr, 4);
962  GR[reg2] = result;
963  TRACE_LD (addr, result);
964}
965
966rrrrr!0,0000110,dddd:IV:::sld.bu
967*v850e
968*v850e1
969"sld.b <disp4>[ep], r<reg2>":(PSW & PSW_US)
970"sld.bu <disp4>[ep], r<reg2>"
971{
972  unsigned32 addr = EP + disp4;
973  unsigned32 result = load_mem (addr, 1);
974  if (PSW & PSW_US)
975    {
976      result = EXTEND8 (result);
977      GR[reg2] = result;
978      TRACE_LD_NAME ("sld.b", addr, result);
979    }
980  else
981    {
982      GR[reg2] = result;
983      TRACE_LD (addr, result);
984    }
985}
986
987rrrrr!0,0000111,dddd:IV:::sld.hu
988*v850e
989*v850e1
990"sld.h <disp5>[ep], r<reg2>":(PSW & PSW_US)
991"sld.hu <disp5>[ep], r<reg2>"
992{
993  unsigned32 addr = EP + disp5;
994  unsigned32 result = load_mem (addr, 2);
995  if (PSW & PSW_US)
996    {
997      result = EXTEND16 (result);
998      GR[reg2] = result;
999      TRACE_LD_NAME ("sld.h", addr, result);
1000    }
1001  else
1002    {
1003      GR[reg2] = result;
1004      TRACE_LD (addr, result);
1005    }
1006}
1007
1008// SST
1009rrrrr,0111,ddddddd:IV:::sst.b
1010"sst.b r<reg2>, <disp7>[ep]"
1011{
1012  COMPAT_1 (OP_380 ());
1013}
1014
1015rrrrr,1001,ddddddd:IV:::sst.h
1016"sst.h r<reg2>, <disp8>[ep]"
1017{
1018  COMPAT_1 (OP_480 ());
1019}
1020
1021rrrrr,1010,dddddd,1:IV:::sst.w
1022"sst.w r<reg2>, <disp8>[ep]"
1023{
1024  COMPAT_1 (OP_501 ());
1025}
1026
1027// ST
1028rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
1029"st.b r<reg2>, <disp16>[r<reg1>]"
1030{
1031  COMPAT_2 (OP_740 ());
1032}
1033
1034rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
1035"st.h r<reg2>, <disp16>[r<reg1>]"
1036{
1037  COMPAT_2 (OP_760 ());
1038}
1039
1040rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
1041"st.w r<reg2>, <disp16>[r<reg1>]"
1042{
1043  COMPAT_2 (OP_10760 ());
1044}
1045
1046// STSR
1047rrrrr,111111,regID + 0000000001000000:IX:::stsr
1048"stsr s<regID>, r<reg2>"
1049{
1050  TRACE_ALU_INPUT1 (SR[regID]);
1051  GR[reg2] = SR[regID];
1052  TRACE_ALU_RESULT (GR[reg2]);
1053}
1054
1055// SUB
1056rrrrr,001101,RRRRR:I:::sub
1057"sub r<reg1>, r<reg2>"
1058{
1059  COMPAT_1 (OP_1A0 ());
1060}
1061
1062// SUBR
1063rrrrr,001100,RRRRR:I:::subr
1064"subr r<reg1>, r<reg2>"
1065{
1066  COMPAT_1 (OP_180 ());
1067}
1068
1069// SWITCH
107000000000010,RRRRR:I:::switch
1071*v850e
1072*v850e1
1073"switch r<reg1>"
1074{
1075  unsigned long adr;
1076  SAVE_1;
1077  trace_input ("switch", OP_REG, 0);
1078  adr = (cia + 2) + (State.regs[ reg1 ] << 1);
1079  nia = (cia + 2) + (EXTEND16 (load_mem (adr, 2)) << 1);
1080  trace_output (OP_REG);
1081}
1082
1083// SXB
108400000000101,RRRRR:I:::sxb
1085*v850e
1086*v850e1
1087"sxb r<reg1>"
1088{
1089  TRACE_ALU_INPUT1 (GR[reg1]);
1090  GR[reg1] = EXTEND8 (GR[reg1]);
1091  TRACE_ALU_RESULT (GR[reg1]);
1092}
1093
1094// SXH
109500000000111,RRRRR:I:::sxh
1096*v850e
1097*v850e1
1098"sxh r<reg1>"
1099{
1100  TRACE_ALU_INPUT1 (GR[reg1]);
1101  GR[reg1] = EXTEND16 (GR[reg1]);
1102  TRACE_ALU_RESULT (GR[reg1]);
1103}
1104
1105// TRAP
110600000111111,iiiii + 0000000100000000:X:::trap
1107"trap <vector>"
1108{
1109  COMPAT_2 (OP_10007E0 ());
1110}
1111
1112// TST
1113rrrrr,001011,RRRRR:I:::tst
1114"tst r<reg1>, r<reg2>"
1115{
1116  COMPAT_1 (OP_160 ());
1117}
1118
1119// TST1
112011,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1
1121"tst1 <bit3>, <disp16>[r<reg1>]"
1122{
1123  COMPAT_2 (OP_C7C0 ());
1124}
1125
1126rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1
1127*v850e
1128*v850e1
1129"tst1 r<reg2>, [r<reg1>]"
1130{
1131  COMPAT_2 (OP_E607E0 ());
1132}
1133
1134// XOR
1135rrrrr,001001,RRRRR:I:::xor
1136"xor r<reg1>, r<reg2>"
1137{
1138  COMPAT_1 (OP_120 ());
1139}
1140
1141// XORI
1142rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
1143"xori <uimm16>, r<reg1>, r<reg2>"
1144{
1145  COMPAT_2 (OP_6A0 ());
1146}
1147
1148// ZXB
114900000000100,RRRRR:I:::zxb
1150*v850e
1151*v850e1
1152"zxb r<reg1>"
1153{
1154  TRACE_ALU_INPUT1 (GR[reg1]);
1155  GR[reg1] = GR[reg1] & 0xff;
1156  TRACE_ALU_RESULT (GR[reg1]);
1157}
1158
1159// ZXH
116000000000110,RRRRR:I:::zxh
1161*v850e
1162*v850e1
1163"zxh r<reg1>"
1164{
1165  TRACE_ALU_INPUT1 (GR[reg1]);
1166  GR[reg1] = GR[reg1] & 0xffff;
1167  TRACE_ALU_RESULT (GR[reg1]);
1168}
1169
1170// Right field must be zero so that it doesn't clash with DIVH
1171// Left field must be non-zero so that it doesn't clash with SWITCH
117211111,000010,00000:I:::break
1173*v850
1174*v850e
1175{
1176  sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
1177}
1178
117911111,000010,00000:I:::dbtrap
1180*v850e1
1181"dbtrap"
1182{
1183  DBPC = cia + 2;
1184  DBPSW = PSW;
1185  PSW = PSW | (PSW_NP | PSW_EP | PSW_ID);
1186  PC = 0x00000060;
1187  nia = 0x00000060;
1188  TRACE_BRANCH0 ();
1189}
1190
1191// New breakpoint: 0x7E0 0x7E0
119200000,111111,00000 + 00000,11111,100000:X:::ilgop
1193{
1194  sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
1195}
1196
1197// Return from debug trap: 0x146007e0
11980000011111100000 + 0000000101000110:X:::dbret
1199*v850e1
1200"dbret"
1201{
1202  nia = DBPC;
1203  PSW = DBPSW;
1204  TRACE_BRANCH1 (PSW);
1205}
1206