1unit AT90PWM81; 2 3{$goto on} 4 5interface 6 7var 8 // PORTB 9 PORTB : byte absolute $00+$25; // Port B Data Register 10 DDRB : byte absolute $00+$24; // Port B Data Direction Register 11 PINB : byte absolute $00+$23; // Port B Input Pins 12 // PORTD 13 PORTD : byte absolute $00+$2B; // Port D Data Register 14 DDRD : byte absolute $00+$2A; // Port D Data Direction Register 15 PIND : byte absolute $00+$29; // Port D Input Pins 16 // DA_CONVERTER 17 DACH : byte absolute $00+$59; // DAC Data Register High Byte 18 DACL : byte absolute $00+$58; // DAC Data Register Low Byte 19 DACON : byte absolute $00+$76; // DAC Control Register 20 // PORTE 21 PORTE : byte absolute $00+$2E; // Port E Data Register 22 DDRE : byte absolute $00+$2D; // Port E Data Direction Register 23 PINE : byte absolute $00+$2C; // Port E Input Pins 24 // SPI 25 SPCR : byte absolute $00+$37; // SPI Control Register 26 SPSR : byte absolute $00+$38; // SPI Status Register 27 SPDR : byte absolute $00+$56; // SPI Data Register 28 // WATCHDOG 29 WDTCSR : byte absolute $00+$82; // Watchdog Timer Control Register 30 // EXTERNAL_INTERRUPT 31 EICRA : byte absolute $00+$89; // External Interrupt Control Register A 32 EIMSK : byte absolute $00+$41; // External Interrupt Mask Register 33 EIFR : byte absolute $00+$40; // External Interrupt Flag Register 34 // AD_CONVERTER 35 ADMUX : byte absolute $00+$28; // The ADC multiplexer Selection Register 36 ADCSRA : byte absolute $00+$26; // The ADC Control and Status register 37 ADC : word absolute $00+$4C; // ADC Data Register Bytes 38 ADCL : byte absolute $00+$4C; // ADC Data Register Bytes 39 ADCH : byte absolute $00+$4C+1; // ADC Data Register Bytes 40 ADCSRB : byte absolute $00+$27; // ADC Control and Status Register B 41 DIDR0 : byte absolute $00+$77; // Digital Input Disable Register 0 42 DIDR1 : byte absolute $00+$78; // Digital Input Disable Register 0 43 AMP0CSR : byte absolute $00+$79; // 44 // ANALOG_COMPARATOR 45 AC3CON : byte absolute $00+$7F; // Analog Comparator3 Control Register 46 AC1CON : byte absolute $00+$7D; // Analog Comparator 1 Control Register 47 AC2CON : byte absolute $00+$7E; // Analog Comparator 2 Control Register 48 ACSR : byte absolute $00+$20; // Analog Comparator Status Register 49 AC3ECON : byte absolute $00+$7C; // 50 AC2ECON : byte absolute $00+$7B; // 51 AC1ECON : byte absolute $00+$7A; // 52 // CPU 53 SREG : byte absolute $00+$5F; // Status Register 54 SP : word absolute $00+$5D; // Stack Pointer 55 SPL : byte absolute $00+$5D; // Stack Pointer 56 SPH : byte absolute $00+$5D+1; // Stack Pointer 57 MCUCR : byte absolute $00+$55; // MCU Control Register 58 MCUSR : byte absolute $00+$54; // MCU Status Register 59 OSCCAL : byte absolute $00+$88; // Oscillator Calibration Value 60 CLKPR : byte absolute $00+$83; // 61 SMCR : byte absolute $00+$53; // Sleep Mode Control Register 62 GPIOR2 : byte absolute $00+$3B; // General Purpose IO Register 2 63 GPIOR1 : byte absolute $00+$3A; // General Purpose IO Register 1 64 GPIOR0 : byte absolute $00+$39; // General Purpose IO Register 0 65 PLLCSR : byte absolute $00+$87; // PLL Control And Status Register 66 PRR : byte absolute $00+$86; // Power Reduction Register 67 CLKCSR : byte absolute $00+$84; // 68 CLKSELR : byte absolute $00+$85; // 69 BGCCR : byte absolute $00+$81; // BandGap Current Calibration Register 70 BGCRR : byte absolute $00+$80; // BandGap Resistor Calibration Register 71 // EEPROM 72 EEAR : word absolute $00+$3E; // EEPROM Read/Write Access Bytes 73 EEARL : byte absolute $00+$3E; // EEPROM Read/Write Access Bytes 74 EEARH : byte absolute $00+$3E+1; // EEPROM Read/Write Access Bytes 75 EEDR : byte absolute $00+$3D; // EEPROM Data Register 76 EECR : byte absolute $00+$3C; // EEPROM Control Register 77 // PSC0 78 PICR0 : word absolute $00+$68; // PSC 0 Input Capture Register 79 PICR0L : byte absolute $00+$68; // PSC 0 Input Capture Register 80 PICR0H : byte absolute $00+$68+1; // PSC 0 Input Capture Register 81 PFRC0B : byte absolute $00+$63; // PSC 0 Input B Control 82 PFRC0A : byte absolute $00+$62; // PSC 0 Input A Control 83 PCTL0 : byte absolute $00+$32; // PSC 0 Control Register 84 PCNF0 : byte absolute $00+$31; // PSC 0 Configuration Register 85 OCR0RB : word absolute $00+$44; // Output Compare RB Register 86 OCR0RBL : byte absolute $00+$44; // Output Compare RB Register 87 OCR0RBH : byte absolute $00+$44+1; // Output Compare RB Register 88 OCR0SB : word absolute $00+$42; // Output Compare SB Register 89 OCR0SBL : byte absolute $00+$42; // Output Compare SB Register 90 OCR0SBH : byte absolute $00+$42+1; // Output Compare SB Register 91 OCR0RA : word absolute $00+$4A; // Output Compare RA Register 92 OCR0RAL : byte absolute $00+$4A; // Output Compare RA Register 93 OCR0RAH : byte absolute $00+$4A+1; // Output Compare RA Register 94 OCR0SA : word absolute $00+$60; // Output Compare SA Register 95 OCR0SAL : byte absolute $00+$60; // Output Compare SA Register 96 OCR0SAH : byte absolute $00+$60+1; // Output Compare SA Register 97 PSOC0 : byte absolute $00+$6A; // PSC0 Synchro and Output Configuration 98 PIM0 : byte absolute $00+$2F; // PSC0 Interrupt Mask Register 99 PIFR0 : byte absolute $00+$30; // PSC0 Interrupt Flag Register 100 // PSC2 101 PICR2H : byte absolute $00+$6D; // PSC 2 Input Capture Register High 102 PICR2L : byte absolute $00+$6C; // PSC 2 Input Capture Register Low 103 PFRC2B : byte absolute $00+$67; // PSC 2 Input B Control 104 PFRC2A : byte absolute $00+$66; // PSC 2 Input B Control 105 PCTL2 : byte absolute $00+$36; // PSC 2 Control Register 106 PCNF2 : byte absolute $00+$35; // PSC 2 Configuration Register 107 PCNFE2 : byte absolute $00+$70; // PSC 2 Enhanced Configuration Register 108 OCR2RB : word absolute $00+$48; // Output Compare RB Register 109 OCR2RBL : byte absolute $00+$48; // Output Compare RB Register 110 OCR2RBH : byte absolute $00+$48+1; // Output Compare RB Register 111 OCR2SB : word absolute $00+$46; // Output Compare SB Register 112 OCR2SBL : byte absolute $00+$46; // Output Compare SB Register 113 OCR2SBH : byte absolute $00+$46+1; // Output Compare SB Register 114 OCR2RA : word absolute $00+$4E; // Output Compare RA Register 115 OCR2RAL : byte absolute $00+$4E; // Output Compare RA Register 116 OCR2RAH : byte absolute $00+$4E+1; // Output Compare RA Register 117 OCR2SA : word absolute $00+$64; // Output Compare SA Register 118 OCR2SAL : byte absolute $00+$64; // Output Compare SA Register 119 OCR2SAH : byte absolute $00+$64+1; // Output Compare SA Register 120 POM2 : byte absolute $00+$6F; // PSC 2 Output Matrix 121 PSOC2 : byte absolute $00+$6E; // PSC2 Synchro and Output Configuration 122 PIM2 : byte absolute $00+$33; // PSC2 Interrupt Mask Register 123 PIFR2 : byte absolute $00+$34; // PSC2 Interrupt Flag Register 124 PASDLY2 : byte absolute $00+$71; // Analog Synchronization Delay Register 125 // TIMER_COUNTER_1 126 TIMSK1 : byte absolute $00+$21; // Timer/Counter Interrupt Mask Register 127 TIFR1 : byte absolute $00+$22; // Timer/Counter Interrupt Flag register 128 TCCR1B : byte absolute $00+$8A; // Timer/Counter1 Control Register B 129 TCNT1 : word absolute $00+$5A; // Timer/Counter1 Bytes 130 TCNT1L : byte absolute $00+$5A; // Timer/Counter1 Bytes 131 TCNT1H : byte absolute $00+$5A+1; // Timer/Counter1 Bytes 132 ICR1 : word absolute $00+$8C; // Timer/Counter1 Input Capture Register Bytes 133 ICR1L : byte absolute $00+$8C; // Timer/Counter1 Input Capture Register Bytes 134 ICR1H : byte absolute $00+$8C+1; // Timer/Counter1 Input Capture Register Bytes 135 // BOOT_LOAD 136 SPMCSR : byte absolute $00+$57; // Store Program Memory Control Register 137 138const 139 // DACH 140 // DACL 141 // DACON 142 DAATE = 7; // DAC Auto Trigger Enable Bit 143 DATS = 4; // DAC Trigger Selection Bits 144 DALA = 2; // DAC Left Adjust 145 DAEN = 0; // DAC Enable Bit 146 // SPCR 147 SPIE = 7; // SPI Interrupt Enable 148 SPE = 6; // SPI Enable 149 DORD = 5; // Data Order 150 MSTR = 4; // Master/Slave Select 151 CPOL = 3; // Clock polarity 152 CPHA = 2; // Clock Phase 153 SPR = 0; // SPI Clock Rate Selects 154 // SPSR 155 SPIF = 7; // SPI Interrupt Flag 156 WCOL = 6; // Write Collision Flag 157 SPI2X = 0; // Double SPI Speed Bit 158 // WDTCSR 159 WDIF = 7; // Watchdog Timeout Interrupt Flag 160 WDIE = 6; // Watchdog Timeout Interrupt Enable 161 WDP = 0; // Watchdog Timer Prescaler Bits 162 WDCE = 4; // Watchdog Change Enable 163 WDE = 3; // Watch Dog Enable 164 // EICRA 165 ISC2 = 4; // External Interrupt Sense Control Bit 166 ISC1 = 2; // External Interrupt Sense Control Bit 167 ISC0 = 0; // External Interrupt Sense Control Bit 168 // EIMSK 169 INT = 0; // External Interrupt Request 2 Enable 170 // EIFR 171 INTF = 0; // External Interrupt Flags 172 // ADMUX 173 REFS = 6; // Reference Selection Bits 174 ADLAR = 5; // Left Adjust Result 175 MUX = 0; // Analog Channel and Gain Selection Bits 176 // ADCSRA 177 ADEN = 7; // ADC Enable 178 ADSC = 6; // ADC Start Conversion 179 ADATE = 5; // ADC Auto Trigger Enable 180 ADIF = 4; // ADC Interrupt Flag 181 ADIE = 3; // ADC Interrupt Enable 182 ADPS = 0; // ADC Prescaler Select Bits 183 // ADCSRB 184 ADHSM = 7; // ADC High Speed Mode 185 ADNCDIS = 6; // ADC Noise Canceller Disable 186 ADSSEN = 4; // ADC Single Shot Enable on PSC's Synchronisation Signals 187 ADTS = 0; // ADC Auto Trigger Sources 188 // DIDR0 189 ADC7D = 7; // 190 ADC6D = 6; // ADC7 Digital input Disable 191 ADC5D = 5; // ADC5 Digital input Disable 192 ADC4D = 4; // ADC4 Digital input Disable 193 ADC3D = 3; // ADC3 Digital input Disable 194 ADC2D = 2; // ADC2 Digital input Disable 195 ADC1D = 1; // ADC1 Digital input Disable 196 ADC0D = 0; // ADC0 Digital input Disable 197 // DIDR1 198 ACMP1MD = 3; // 199 AMP0POSD = 2; // 200 ADC10D = 1; // 201 ADC9D = 0; // 202 // AMP0CSR 203 AMP0EN = 7; // 204 AMP0IS = 6; // 205 AMP0G = 4; // 206 AMP0GS = 3; // 207 AMP0TS = 0; // 208 // AC3CON 209 AC3EN = 7; // Analog Comparator3 Enable Bit 210 AC3IE = 6; // Analog Comparator 3 Interrupt Enable Bit 211 AC3IS = 4; // Analog Comparator 3 Interrupt Select Bit 212 AC3OEA = 3; // Analog Comparator 3 Alternate Output Enable 213 AC3M = 0; // Analog Comparator 3 Multiplexer Register 214 // AC1CON 215 AC1EN = 7; // Analog Comparator 1 Enable Bit 216 AC1IE = 6; // Analog Comparator 1 Interrupt Enable Bit 217 AC1IS = 4; // Analog Comparator 1 Interrupt Select Bit 218 AC1M = 0; // Analog Comparator 1 Multiplexer Register 219 // AC2CON 220 AC2EN = 7; // Analog Comparator 2 Enable Bit 221 AC2IE = 6; // Analog Comparator 2 Interrupt Enable Bit 222 AC2IS = 4; // Analog Comparator 2 Interrupt Select Bit 223 AC2M = 0; // Analog Comparator 2 Multiplexer Register 224 // ACSR 225 AC3IF = 7; // Analog Comparator 3 Interrupt Flag Bit 226 AC2IF = 6; // Analog Comparator 2 Interrupt Flag Bit 227 AC1IF = 5; // Analog Comparator 1 Interrupt Flag Bit 228 AC3O = 3; // Analog Comparator 3 Output Bit 229 AC2O = 2; // Analog Comparator 2 Output Bit 230 AC1O = 1; // Analog Comparator 1 Output Bit 231 // AC3ECON 232 AC3OI = 5; // Analog Comparator Ouput Invert 233 AC3OE = 4; // Analog Comparator Ouput Enable 234 AC3H = 0; // Analog Comparator Hysteresis Select 235 // AC2ECON 236 AC2OI = 5; // Analog Comparator Ouput Invert 237 AC2OE = 4; // Analog Comparator Ouput Enable 238 AC2H = 0; // Analog Comparator Hysteresis Select 239 // AC1ECON 240 AC1OI = 5; // Analog Comparator Ouput Invert 241 AC1OE = 4; // Analog Comparator Ouput Enable 242 AC1ICE = 3; // Analog Comparator Interrupt Capture Enable 243 AC1H = 0; // Analog Comparator Hysteresis Select 244 // SREG 245 I = 7; // Global Interrupt Enable 246 T = 6; // Bit Copy Storage 247 H = 5; // Half Carry Flag 248 S = 4; // Sign Bit 249 V = 3; // Two's Complement Overflow Flag 250 N = 2; // Negative Flag 251 Z = 1; // Zero Flag 252 C = 0; // Carry Flag 253 // MCUCR 254 PUD = 4; // Pull-up disable 255 RSTDIS = 3; // Reset Pin Disable 256 CKRC81 = 2; // Frequency Selection of the Calibrated RC Oscillator 257 IVSEL = 1; // Interrupt Vector Select 258 IVCE = 0; // Interrupt Vector Change Enable 259 // MCUSR 260 WDRF = 3; // Watchdog Reset Flag 261 BORF = 2; // Brown-out Reset Flag 262 EXTRF = 1; // External Reset Flag 263 PORF = 0; // Power-on reset flag 264 // CLKPR 265 CLKPCE = 7; // 266 CLKPS = 0; // 267 // SMCR 268 SM = 1; // Sleep Mode Select bits 269 SE = 0; // Sleep Enable 270 // GPIOR2 271 GPIOR = 0; // General Purpose IO Register 2 bis 272 // GPIOR1 273 // GPIOR0 274 GPIOR07 = 7; // General Purpose IO Register 0 bit 7 275 GPIOR06 = 6; // General Purpose IO Register 0 bit 6 276 GPIOR05 = 5; // General Purpose IO Register 0 bit 5 277 GPIOR04 = 4; // General Purpose IO Register 0 bit 4 278 GPIOR03 = 3; // General Purpose IO Register 0 bit 3 279 GPIOR02 = 2; // General Purpose IO Register 0 bit 2 280 GPIOR01 = 1; // General Purpose IO Register 0 bit 1 281 GPIOR00 = 0; // General Purpose IO Register 0 bit 0 282 // PLLCSR 283 PLLF = 2; // 284 PLLE = 1; // PLL Enable 285 PLOCK = 0; // PLL Lock Detector 286 // PRR 287 PRPSC2 = 7; // Power Reduction PSC2 288 PRPSCR = 5; // Power Reduction PSC0 289 PRTIM1 = 4; // Power Reduction Timer/Counter1 290 PRSPI = 2; // Power Reduction Serial Peripheral Interface 291 PRADC = 0; // Power Reduction ADC 292 // CLKCSR 293 CLKCCE = 7; // Clock Control Change Enable 294 CLKRDY = 4; // Clock Ready Flag 295 CLKC = 0; // Clock Control 296 // CLKSELR 297 COUT = 6; // Clock OUT 298 CSUT = 4; // Clock Start up Time 299 CKSEL = 0; // Clock Source Select 300 // BGCCR 301 BGCC = 0; // 302 // BGCRR 303 BGCR = 0; // 304 // EECR 305 NVMBSY = 7; // None Volatile Busy Memory Busy 306 EEPAGE = 6; // EEPROM Page Access 307 EEPM = 4; // EEPROM Programming Mode 308 EERIE = 3; // EEPROM Ready Interrupt Enable 309 EEMWE = 2; // EEPROM Master Write Enable 310 EEWE = 1; // EEPROM Write Enable 311 EERE = 0; // EEPROM Read Enable 312 // PFRC0B 313 PCAE0B = 7; // PSC 0 Capture Enable Input Part B 314 PISEL0B = 6; // PSC 0 Input Select for Part B 315 PELEV0B = 5; // PSC 0 Edge Level Selector on Input Part B 316 PFLTE0B = 4; // PSC 0 Filter Enable on Input Part B 317 PRFM0B = 0; // PSC 0 Retrigger and Fault Mode for Part B 318 // PFRC0A 319 PCAE0A = 7; // PSC 0 Capture Enable Input Part A 320 PISEL0A = 6; // PSC 0 Input Select for Part A 321 PELEV0A = 5; // PSC 0 Edge Level Selector on Input Part A 322 PFLTE0A = 4; // PSC 0 Filter Enable on Input Part A 323 PRFM0A = 0; // PSC 0 Retrigger and Fault Mode for Part A 324 // PCTL0 325 PPRE0 = 6; // PSC 0 Prescaler Selects 326 PBFM0 = 2; // PSC 0 Balance Flank Width Modulation 327 PAOC0B = 4; // PSC 0 Asynchronous Output Control B 328 PAOC0A = 3; // PSC 0 Asynchronous Output Control A 329 PCCYC0 = 1; // PSC0 Complete Cycle 330 PRUN0 = 0; // PSC 0 Run 331 // PCNF0 332 PFIFTY0 = 7; // PSC 0 Fifty 333 PALOCK0 = 6; // PSC 0 Autolock 334 PLOCK0 = 5; // PSC 0 Lock 335 PMODE0 = 3; // PSC 0 Mode 336 POP0 = 2; // PSC 0 Output Polarity 337 PCLKSEL0 = 1; // PSC 0 Input Clock Select 338 // PSOC0 339 PISEL0A1 = 7; // PSC Input Select 340 PISEL0B1 = 6; // PSC Input Select 341 PSYNC0 = 4; // Synchronisation out for ADC selection 342 POEN0B = 2; // PSCOUT01 Output Enable 343 POEN0A = 0; // PSCOUT00 Output Enable 344 // PIM0 345 PEVE0B = 4; // External Event B Interrupt Enable 346 PEVE0A = 3; // External Event A Interrupt Enable 347 PEOEPE0 = 1; // End of Enhanced Cycle Enable 348 PEOPE0 = 0; // End of Cycle Interrupt Enable 349 // PIFR0 350 POAC0B = 7; // PSC 0 Output A Activity 351 POAC0A = 6; // PSC 0 Output A Activity 352 PEV0B = 4; // External Event B Interrupt 353 PEV0A = 3; // External Event A Interrupt 354 PRN0 = 1; // Ramp Number 355 PEOP0 = 0; // End of PSC0 Interrupt 356 // PICR2H 357 PCST2 = 7; // PSC 2 Capture Software Trigger Bit 358 PICR21 = 2; // 359 PICR2 = 0; // 360 // PFRC2B 361 PCAE2B = 7; // PSC 2 Capture Enable Input Part B 362 PISEL2B = 6; // PSC 2 Input Select for Part B 363 PELEV2B = 5; // PSC 2 Edge Level Selector on Input Part B 364 PFLTE2B = 4; // PSC 2 Filter Enable on Input Part B 365 PRFM2B = 0; // PSC 2 Retrigger and Fault Mode for Part B 366 // PFRC2A 367 PCAE2A = 7; // PSC 2 Capture Enable Input Part A 368 PISEL2A = 6; // PSC 2 Input Select for Part A 369 PELEV2A = 5; // PSC 2 Edge Level Selector on Input Part A 370 PFLTE2A = 4; // PSC 2 Filter Enable on Input Part A 371 PRFM2A = 0; // PSC 2 Retrigger and Fault Mode for Part A 372 // PCTL2 373 PPRE2 = 6; // PSC 2 Prescaler Selects 374 PBFM2 = 5; // Balance Flank Width Modulation 375 PAOC2B = 4; // PSC 2 Asynchronous Output Control B 376 PAOC2A = 3; // PSC 2 Asynchronous Output Control A 377 PARUN2 = 2; // PSC2 Auto Run 378 PCCYC2 = 1; // PSC2 Complete Cycle 379 PRUN2 = 0; // PSC 2 Run 380 // PCNF2 381 PFIFTY2 = 7; // PSC 2 Fifty 382 PALOCK2 = 6; // PSC 2 Autolock 383 PLOCK2 = 5; // PSC 2 Lock 384 PMODE2 = 3; // PSC 2 Mode 385 POP2 = 2; // PSC 2 Output Polarity 386 PCLKSEL2 = 1; // PSC 2 Input Clock Select 387 POME2 = 0; // PSC 2 Output Matrix Enable 388 // PCNFE2 389 PASDLK2 = 5; // 390 PBFM21 = 4; // 391 PELEV2A1 = 3; // 392 PELEV2B1 = 2; // 393 PISEL2A1 = 1; // 394 PISEL2B1 = 0; // 395 // POM2 396 POMV2B = 4; // Output Matrix Output B Ramps 397 POMV2A = 0; // Output Matrix Output A Ramps 398 // PSOC2 399 POS2 = 6; // PSC 2 Output 23 Select 400 PSYNC2 = 4; // Synchronization Out for ADC Selection 401 POEN2D = 3; // PSCOUT23 Output Enable 402 POEN2B = 2; // PSCOUT21 Output Enable 403 POEN2C = 1; // PSCOUT22 Output Enable 404 POEN2A = 0; // PSCOUT20 Output Enable 405 // PIM2 406 PSEIE2 = 5; // PSC 2 Synchro Error Interrupt Enable 407 PEVE2B = 4; // External Event B Interrupt Enable 408 PEVE2A = 3; // External Event A Interrupt Enable 409 PEOEPE2 = 1; // End of Enhanced Cycle Interrupt Enable 410 PEOPE2 = 0; // End of Cycle Interrupt Enable 411 // PIFR2 412 POAC2B = 7; // PSC 2 Output A Activity 413 POAC2A = 6; // PSC 2 Output A Activity 414 PSEI2 = 5; // PSC 2 Synchro Error Interrupt 415 PEV2B = 4; // External Event B Interrupt 416 PEV2A = 3; // External Event A Interrupt 417 PRN2 = 1; // Ramp Number 418 PEOP2 = 0; // End of PSC2 Interrupt 419 // TIMSK1 420 ICIE1 = 5; // Timer/Counter1 Input Capture Interrupt Enable 421 TOIE1 = 0; // Timer/Counter1 Overflow Interrupt Enable 422 // TIFR1 423 ICF1 = 5; // Input Capture Flag 1 424 TOV1 = 0; // Timer/Counter1 Overflow Flag 425 // TCCR1B 426 ICNC1 = 7; // Input Capture 1 Noise Canceler 427 ICES1 = 6; // Input Capture 1 Edge Select 428 WGM13 = 4; // Waveform Generation Mode 429 CS1 = 0; // Prescaler source of Timer/Counter 1 430 // SPMCSR 431 SPMIE = 7; // SPM Interrupt Enable 432 RWWSB = 6; // Read While Write Section Busy 433 SIGRD = 5; // Signature Row Read 434 RWWSRE = 4; // Read While Write section read enable 435 BLBSET = 3; // Boot Lock Bit Set 436 PGWRT = 2; // Page Write 437 PGERS = 1; // Page Erase 438 SPMEN = 0; // Store Program Memory Enable 439 440implementation 441 442{$define RELBRANCHES} 443 444{$i avrcommon.inc} 445 446procedure PSC2_CAPT_ISR; external name 'PSC2_CAPT_ISR'; // Interrupt 1 PSC2 Capture Event 447procedure PSC2_EC_ISR; external name 'PSC2_EC_ISR'; // Interrupt 2 PSC2 End Cycle 448procedure PSC2_EEC_ISR; external name 'PSC2_EEC_ISR'; // Interrupt 3 PSC2 End Of Enhanced Cycle 449procedure PSC0_CAPT_ISR; external name 'PSC0_CAPT_ISR'; // Interrupt 4 PSC0 Capture Event 450procedure PSC0_EC_ISR; external name 'PSC0_EC_ISR'; // Interrupt 5 PSC0 End Cycle 451procedure PSC0_EEC_ISR; external name 'PSC0_EEC_ISR'; // Interrupt 6 PSC0 End Of Enhanced Cycle 452procedure ANALOG_COMP_1_ISR; external name 'ANALOG_COMP_1_ISR'; // Interrupt 7 Analog Comparator 1 453procedure ANALOG_COMP_2_ISR; external name 'ANALOG_COMP_2_ISR'; // Interrupt 8 Analog Comparator 2 454procedure ANALOG_COMP_3_ISR; external name 'ANALOG_COMP_3_ISR'; // Interrupt 9 Analog Comparator 3 455procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 10 External Interrupt Request 0 456procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 11 Timer/Counter1 Capture Event 457procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 12 Timer/Counter1 Overflow 458procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 13 ADC Conversion Complete 459procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 14 External Interrupt Request 1 460procedure SPI__STC_ISR; external name 'SPI__STC_ISR'; // Interrupt 15 SPI Serial Transfer Complet 461procedure INT2_ISR; external name 'INT2_ISR'; // Interrupt 16 External Interrupt Request 2 462procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 17 Watchdog Timeout Interrupt 463procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 18 EEPROM Ready 464procedure SPM_READY_ISR; external name 'SPM_READY_ISR'; // Interrupt 19 Store Program Memory Read 465 466procedure _FPC_start; assembler; nostackframe; 467label 468 _start; 469 asm 470 .init 471 .globl _start 472 473 rjmp _start 474 rjmp PSC2_CAPT_ISR 475 rjmp PSC2_EC_ISR 476 rjmp PSC2_EEC_ISR 477 rjmp PSC0_CAPT_ISR 478 rjmp PSC0_EC_ISR 479 rjmp PSC0_EEC_ISR 480 rjmp ANALOG_COMP_1_ISR 481 rjmp ANALOG_COMP_2_ISR 482 rjmp ANALOG_COMP_3_ISR 483 rjmp INT0_ISR 484 rjmp TIMER1_CAPT_ISR 485 rjmp TIMER1_OVF_ISR 486 rjmp ADC_ISR 487 rjmp INT1_ISR 488 rjmp SPI__STC_ISR 489 rjmp INT2_ISR 490 rjmp WDT_ISR 491 rjmp EE_READY_ISR 492 rjmp SPM_READY_ISR 493 494 {$i start.inc} 495 496 .weak PSC2_CAPT_ISR 497 .weak PSC2_EC_ISR 498 .weak PSC2_EEC_ISR 499 .weak PSC0_CAPT_ISR 500 .weak PSC0_EC_ISR 501 .weak PSC0_EEC_ISR 502 .weak ANALOG_COMP_1_ISR 503 .weak ANALOG_COMP_2_ISR 504 .weak ANALOG_COMP_3_ISR 505 .weak INT0_ISR 506 .weak TIMER1_CAPT_ISR 507 .weak TIMER1_OVF_ISR 508 .weak ADC_ISR 509 .weak INT1_ISR 510 .weak SPI__STC_ISR 511 .weak INT2_ISR 512 .weak WDT_ISR 513 .weak EE_READY_ISR 514 .weak SPM_READY_ISR 515 516 .set PSC2_CAPT_ISR, Default_IRQ_handler 517 .set PSC2_EC_ISR, Default_IRQ_handler 518 .set PSC2_EEC_ISR, Default_IRQ_handler 519 .set PSC0_CAPT_ISR, Default_IRQ_handler 520 .set PSC0_EC_ISR, Default_IRQ_handler 521 .set PSC0_EEC_ISR, Default_IRQ_handler 522 .set ANALOG_COMP_1_ISR, Default_IRQ_handler 523 .set ANALOG_COMP_2_ISR, Default_IRQ_handler 524 .set ANALOG_COMP_3_ISR, Default_IRQ_handler 525 .set INT0_ISR, Default_IRQ_handler 526 .set TIMER1_CAPT_ISR, Default_IRQ_handler 527 .set TIMER1_OVF_ISR, Default_IRQ_handler 528 .set ADC_ISR, Default_IRQ_handler 529 .set INT1_ISR, Default_IRQ_handler 530 .set SPI__STC_ISR, Default_IRQ_handler 531 .set INT2_ISR, Default_IRQ_handler 532 .set WDT_ISR, Default_IRQ_handler 533 .set EE_READY_ISR, Default_IRQ_handler 534 .set SPM_READY_ISR, Default_IRQ_handler 535 end; 536 537end. 538