1 unit PIC16F884; 2 3 // Define hardware 4 {$SET PIC_MODEL = 'PIC16F884'} 5 {$SET PIC_MAXFREQ = 20000000} 6 {$SET PIC_NPINS = 40} 7 {$SET PIC_NUMBANKS = 4} 8 {$SET PIC_NUMPAGES = 2} 9 {$SET PIC_MAXFLASH = 4096} 10 11 interface 12 var 13 INDF : byte absolute $0000; 14 TMR0 : byte absolute $0001; 15 PCL : byte absolute $0002; 16 STATUS : byte absolute $0003; 17 STATUS_IRP : bit absolute STATUS.7; 18 STATUS_RP1 : bit absolute STATUS.6; 19 STATUS_RP0 : bit absolute STATUS.5; 20 STATUS_nTO : bit absolute STATUS.4; 21 STATUS_nPD : bit absolute STATUS.3; 22 STATUS_Z : bit absolute STATUS.2; 23 STATUS_DC : bit absolute STATUS.1; 24 STATUS_C : bit absolute STATUS.0; 25 FSR : byte absolute $0004; 26 PORTA : byte absolute $0005; 27 PORTA_RA7 : bit absolute PORTA.7; 28 PORTA_RA6 : bit absolute PORTA.6; 29 PORTA_RA5 : bit absolute PORTA.5; 30 PORTA_RA4 : bit absolute PORTA.4; 31 PORTA_RA3 : bit absolute PORTA.3; 32 PORTA_RA2 : bit absolute PORTA.2; 33 PORTA_RA1 : bit absolute PORTA.1; 34 PORTA_RA0 : bit absolute PORTA.0; 35 PORTB : byte absolute $0006; 36 PORTB_RB7 : bit absolute PORTB.7; 37 PORTB_RB6 : bit absolute PORTB.6; 38 PORTB_RB5 : bit absolute PORTB.5; 39 PORTB_RB4 : bit absolute PORTB.4; 40 PORTB_RB3 : bit absolute PORTB.3; 41 PORTB_RB2 : bit absolute PORTB.2; 42 PORTB_RB1 : bit absolute PORTB.1; 43 PORTB_RB0 : bit absolute PORTB.0; 44 PORTC : byte absolute $0007; 45 PORTC_RC7 : bit absolute PORTC.7; 46 PORTC_RC6 : bit absolute PORTC.6; 47 PORTC_RC5 : bit absolute PORTC.5; 48 PORTC_RC4 : bit absolute PORTC.4; 49 PORTC_RC3 : bit absolute PORTC.3; 50 PORTC_RC2 : bit absolute PORTC.2; 51 PORTC_RC1 : bit absolute PORTC.1; 52 PORTC_RC0 : bit absolute PORTC.0; 53 PORTD : byte absolute $0008; 54 PORTD_RD7 : bit absolute PORTD.7; 55 PORTD_RD6 : bit absolute PORTD.6; 56 PORTD_RD5 : bit absolute PORTD.5; 57 PORTD_RD4 : bit absolute PORTD.4; 58 PORTD_RD3 : bit absolute PORTD.3; 59 PORTD_RD2 : bit absolute PORTD.2; 60 PORTD_RD1 : bit absolute PORTD.1; 61 PORTD_RD0 : bit absolute PORTD.0; 62 PORTE : byte absolute $0009; 63 PORTE_RE3 : bit absolute PORTE.3; 64 PORTE_RE2 : bit absolute PORTE.2; 65 PORTE_RE1 : bit absolute PORTE.1; 66 PORTE_RE0 : bit absolute PORTE.0; 67 PCLATH : byte absolute $000A; 68 PCLATH_PCLATH4 : bit absolute PCLATH.4; 69 PCLATH_PCLATH3 : bit absolute PCLATH.3; 70 PCLATH_PCLATH2 : bit absolute PCLATH.2; 71 PCLATH_PCLATH1 : bit absolute PCLATH.1; 72 PCLATH_PCLATH0 : bit absolute PCLATH.0; 73 INTCON : byte absolute $000B; 74 INTCON_GIE : bit absolute INTCON.7; 75 INTCON_PEIE : bit absolute INTCON.6; 76 INTCON_T0IE : bit absolute INTCON.5; 77 INTCON_INTE : bit absolute INTCON.4; 78 INTCON_RBIE : bit absolute INTCON.3; 79 INTCON_T0IF : bit absolute INTCON.2; 80 INTCON_INTF : bit absolute INTCON.1; 81 INTCON_RBIF : bit absolute INTCON.0; 82 PIR1 : byte absolute $000C; 83 PIR1_ADIF : bit absolute PIR1.6; 84 PIR1_RCIF : bit absolute PIR1.5; 85 PIR1_TXIF : bit absolute PIR1.4; 86 PIR1_SSPIF : bit absolute PIR1.3; 87 PIR1_CCP1IF : bit absolute PIR1.2; 88 PIR1_TMR2IF : bit absolute PIR1.1; 89 PIR1_TMR1IF : bit absolute PIR1.0; 90 PIR2 : byte absolute $000D; 91 PIR2_OSFIF : bit absolute PIR2.7; 92 PIR2_C2IF : bit absolute PIR2.6; 93 PIR2_C1IF : bit absolute PIR2.5; 94 PIR2_EEIF : bit absolute PIR2.4; 95 PIR2_BCLIF : bit absolute PIR2.3; 96 PIR2_ULPWUIF : bit absolute PIR2.2; 97 PIR2_CCP2IF : bit absolute PIR2.0; 98 TMR1L : byte absolute $000E; 99 TMR1H : byte absolute $000F; 100 T1CON : byte absolute $0010; 101 T1CON_T1GINV : bit absolute T1CON.7; 102 T1CON_TMR1GE : bit absolute T1CON.6; 103 T1CON_T1CKPS1 : bit absolute T1CON.5; 104 T1CON_T1CKPS0 : bit absolute T1CON.4; 105 T1CON_T1OSCEN : bit absolute T1CON.3; 106 T1CON_nT1SYNC : bit absolute T1CON.2; 107 T1CON_TMR1CS : bit absolute T1CON.1; 108 T1CON_TMR1ON : bit absolute T1CON.0; 109 TMR2 : byte absolute $0011; 110 T2CON : byte absolute $0012; 111 T2CON_TOUTPS3 : bit absolute T2CON.6; 112 T2CON_TOUTPS2 : bit absolute T2CON.5; 113 T2CON_TOUTPS1 : bit absolute T2CON.4; 114 T2CON_TOUTPS0 : bit absolute T2CON.3; 115 T2CON_TMR2ON : bit absolute T2CON.2; 116 T2CON_T2CKPS1 : bit absolute T2CON.1; 117 T2CON_T2CKPS0 : bit absolute T2CON.0; 118 SSPBUF : byte absolute $0013; 119 SSPCON : byte absolute $0014; 120 SSPCON_WCOL : bit absolute SSPCON.7; 121 SSPCON_SSPOV : bit absolute SSPCON.6; 122 SSPCON_SSPEN : bit absolute SSPCON.5; 123 SSPCON_CKP : bit absolute SSPCON.4; 124 SSPCON_SSPM3 : bit absolute SSPCON.3; 125 SSPCON_SSPM2 : bit absolute SSPCON.2; 126 SSPCON_SSPM1 : bit absolute SSPCON.1; 127 SSPCON_SSPM0 : bit absolute SSPCON.0; 128 CCPR1L : byte absolute $0015; 129 CCPR1H : byte absolute $0016; 130 CCP1CON : byte absolute $0017; 131 CCP1CON_P1M1 : bit absolute CCP1CON.7; 132 CCP1CON_P1M0 : bit absolute CCP1CON.6; 133 CCP1CON_DC1B1 : bit absolute CCP1CON.5; 134 CCP1CON_DC1B0 : bit absolute CCP1CON.4; 135 CCP1CON_CCP1M3 : bit absolute CCP1CON.3; 136 CCP1CON_CCP1M2 : bit absolute CCP1CON.2; 137 CCP1CON_CCP1M1 : bit absolute CCP1CON.1; 138 CCP1CON_CCP1M0 : bit absolute CCP1CON.0; 139 RCSTA : byte absolute $0018; 140 RCSTA_SPEN : bit absolute RCSTA.7; 141 RCSTA_RX9 : bit absolute RCSTA.6; 142 RCSTA_SREN : bit absolute RCSTA.5; 143 RCSTA_CREN : bit absolute RCSTA.4; 144 RCSTA_ADDEN : bit absolute RCSTA.3; 145 RCSTA_FERR : bit absolute RCSTA.2; 146 RCSTA_OERR : bit absolute RCSTA.1; 147 RCSTA_RX9D : bit absolute RCSTA.0; 148 TXREG : byte absolute $0019; 149 RCREG : byte absolute $001A; 150 CCPR2L : byte absolute $001B; 151 CCPR2H : byte absolute $001C; 152 CCP2CON : byte absolute $001D; 153 CCP2CON_DC2B1 : bit absolute CCP2CON.5; 154 CCP2CON_DC2B0 : bit absolute CCP2CON.4; 155 CCP2CON_CCP2M3 : bit absolute CCP2CON.3; 156 CCP2CON_CCP2M2 : bit absolute CCP2CON.2; 157 CCP2CON_CCP2M1 : bit absolute CCP2CON.1; 158 CCP2CON_CCP2M0 : bit absolute CCP2CON.0; 159 ADRESH : byte absolute $001E; 160 ADCON0 : byte absolute $001F; 161 ADCON0_ADCS1 : bit absolute ADCON0.7; 162 ADCON0_ADCS0 : bit absolute ADCON0.6; 163 ADCON0_CHS3 : bit absolute ADCON0.5; 164 ADCON0_CHS2 : bit absolute ADCON0.4; 165 ADCON0_CHS1 : bit absolute ADCON0.3; 166 ADCON0_CHS0 : bit absolute ADCON0.2; 167 ADCON0_GO_nDONE : bit absolute ADCON0.1; 168 ADCON0_ADON : bit absolute ADCON0.0; 169 OPTION_REG : byte absolute $0081; 170 OPTION_REG_nRBPU : bit absolute OPTION_REG.7; 171 OPTION_REG_INTEDG : bit absolute OPTION_REG.6; 172 OPTION_REG_T0CS : bit absolute OPTION_REG.5; 173 OPTION_REG_T0SE : bit absolute OPTION_REG.4; 174 OPTION_REG_PSA : bit absolute OPTION_REG.3; 175 OPTION_REG_PS2 : bit absolute OPTION_REG.2; 176 OPTION_REG_PS1 : bit absolute OPTION_REG.1; 177 OPTION_REG_PS0 : bit absolute OPTION_REG.0; 178 TRISA : byte absolute $0085; 179 TRISA_TRISA7 : bit absolute TRISA.7; 180 TRISA_TRISA6 : bit absolute TRISA.6; 181 TRISA_TRISA5 : bit absolute TRISA.5; 182 TRISA_TRISA4 : bit absolute TRISA.4; 183 TRISA_TRISA3 : bit absolute TRISA.3; 184 TRISA_TRISA2 : bit absolute TRISA.2; 185 TRISA_TRISA1 : bit absolute TRISA.1; 186 TRISA_TRISA0 : bit absolute TRISA.0; 187 TRISB : byte absolute $0086; 188 TRISB_TRISB7 : bit absolute TRISB.7; 189 TRISB_TRISB6 : bit absolute TRISB.6; 190 TRISB_TRISB5 : bit absolute TRISB.5; 191 TRISB_TRISB4 : bit absolute TRISB.4; 192 TRISB_TRISB3 : bit absolute TRISB.3; 193 TRISB_TRISB2 : bit absolute TRISB.2; 194 TRISB_TRISB1 : bit absolute TRISB.1; 195 TRISB_TRISB0 : bit absolute TRISB.0; 196 TRISC : byte absolute $0087; 197 TRISC_TRISC7 : bit absolute TRISC.7; 198 TRISC_TRISC6 : bit absolute TRISC.6; 199 TRISC_TRISC5 : bit absolute TRISC.5; 200 TRISC_TRISC4 : bit absolute TRISC.4; 201 TRISC_TRISC3 : bit absolute TRISC.3; 202 TRISC_TRISC2 : bit absolute TRISC.2; 203 TRISC_TRISC1 : bit absolute TRISC.1; 204 TRISC_TRISC0 : bit absolute TRISC.0; 205 TRISD : byte absolute $0088; 206 TRISD_TRISD7 : bit absolute TRISD.7; 207 TRISD_TRISD6 : bit absolute TRISD.6; 208 TRISD_TRISD5 : bit absolute TRISD.5; 209 TRISD_TRISD4 : bit absolute TRISD.4; 210 TRISD_TRISD3 : bit absolute TRISD.3; 211 TRISD_TRISD2 : bit absolute TRISD.2; 212 TRISD_TRISD1 : bit absolute TRISD.1; 213 TRISD_TRISD0 : bit absolute TRISD.0; 214 TRISE : byte absolute $0089; 215 TRISE_TRISE3 : bit absolute TRISE.3; 216 TRISE_TRISE2 : bit absolute TRISE.2; 217 TRISE_TRISE1 : bit absolute TRISE.1; 218 TRISE_TRISE0 : bit absolute TRISE.0; 219 PIE1 : byte absolute $008C; 220 PIE1_ADIE : bit absolute PIE1.6; 221 PIE1_RCIE : bit absolute PIE1.5; 222 PIE1_TXIE : bit absolute PIE1.4; 223 PIE1_SSPIE : bit absolute PIE1.3; 224 PIE1_CCP1IE : bit absolute PIE1.2; 225 PIE1_TMR2IE : bit absolute PIE1.1; 226 PIE1_TMR1IE : bit absolute PIE1.0; 227 PIE2 : byte absolute $008D; 228 PIE2_OSFIE : bit absolute PIE2.7; 229 PIE2_C2IE : bit absolute PIE2.6; 230 PIE2_C1IE : bit absolute PIE2.5; 231 PIE2_EEIE : bit absolute PIE2.4; 232 PIE2_BCLIE : bit absolute PIE2.3; 233 PIE2_ULPWUIE : bit absolute PIE2.2; 234 PIE2_CCP2IE : bit absolute PIE2.0; 235 PCON : byte absolute $008E; 236 PCON_ULPWUE : bit absolute PCON.5; 237 PCON_SBOREN : bit absolute PCON.4; 238 PCON_nPOR : bit absolute PCON.1; 239 PCON_nBOR : bit absolute PCON.0; 240 OSCCON : byte absolute $008F; 241 OSCCON_IRCF2 : bit absolute OSCCON.6; 242 OSCCON_IRCF1 : bit absolute OSCCON.5; 243 OSCCON_IRCF0 : bit absolute OSCCON.4; 244 OSCCON_OSTS : bit absolute OSCCON.3; 245 OSCCON_HTS : bit absolute OSCCON.2; 246 OSCCON_LTS : bit absolute OSCCON.1; 247 OSCCON_SCS : bit absolute OSCCON.0; 248 OSCTUNE : byte absolute $0090; 249 OSCTUNE_TUN4 : bit absolute OSCTUNE.4; 250 OSCTUNE_TUN3 : bit absolute OSCTUNE.3; 251 OSCTUNE_TUN2 : bit absolute OSCTUNE.2; 252 OSCTUNE_TUN1 : bit absolute OSCTUNE.1; 253 OSCTUNE_TUN0 : bit absolute OSCTUNE.0; 254 SSPCON2 : byte absolute $0091; 255 SSPCON2_GCEN : bit absolute SSPCON2.7; 256 SSPCON2_ACKSTAT : bit absolute SSPCON2.6; 257 SSPCON2_ACKDT : bit absolute SSPCON2.5; 258 SSPCON2_ACKEN : bit absolute SSPCON2.4; 259 SSPCON2_RCEN : bit absolute SSPCON2.3; 260 SSPCON2_PEN : bit absolute SSPCON2.2; 261 SSPCON2_RSEN : bit absolute SSPCON2.1; 262 SSPCON2_SEN : bit absolute SSPCON2.0; 263 PR2 : byte absolute $0092; 264 SSPADD : byte absolute $0093; 265 SSPSTAT : byte absolute $0094; 266 SSPSTAT_SMP : bit absolute SSPSTAT.7; 267 SSPSTAT_CKE : bit absolute SSPSTAT.6; 268 SSPSTAT_D_nA : bit absolute SSPSTAT.5; 269 SSPSTAT_P : bit absolute SSPSTAT.4; 270 SSPSTAT_S : bit absolute SSPSTAT.3; 271 SSPSTAT_R_nW : bit absolute SSPSTAT.2; 272 SSPSTAT_UA : bit absolute SSPSTAT.1; 273 SSPSTAT_BF : bit absolute SSPSTAT.0; 274 WPUB : byte absolute $0095; 275 IOCB : byte absolute $0096; 276 VRCON : byte absolute $0097; 277 VRCON_VREN : bit absolute VRCON.7; 278 VRCON_VROE : bit absolute VRCON.6; 279 VRCON_VRR : bit absolute VRCON.5; 280 VRCON_VRSS : bit absolute VRCON.4; 281 VRCON_VR3 : bit absolute VRCON.3; 282 VRCON_VR2 : bit absolute VRCON.2; 283 VRCON_VR1 : bit absolute VRCON.1; 284 VRCON_VR0 : bit absolute VRCON.0; 285 TXSTA : byte absolute $0098; 286 TXSTA_CSRC : bit absolute TXSTA.7; 287 TXSTA_TX9 : bit absolute TXSTA.6; 288 TXSTA_TXEN : bit absolute TXSTA.5; 289 TXSTA_SYNC : bit absolute TXSTA.4; 290 TXSTA_SENDB : bit absolute TXSTA.3; 291 TXSTA_BRGH : bit absolute TXSTA.2; 292 TXSTA_TRMT : bit absolute TXSTA.1; 293 TXSTA_TX9D : bit absolute TXSTA.0; 294 SPBRG : byte absolute $0099; 295 SPBRGH : byte absolute $009A; 296 PWM1CON : byte absolute $009B; 297 PWM1CON_PRSEN : bit absolute PWM1CON.7; 298 PWM1CON_PDC6 : bit absolute PWM1CON.6; 299 PWM1CON_PDC5 : bit absolute PWM1CON.5; 300 PWM1CON_PDC4 : bit absolute PWM1CON.4; 301 PWM1CON_PDC3 : bit absolute PWM1CON.3; 302 PWM1CON_PDC2 : bit absolute PWM1CON.2; 303 PWM1CON_PDC1 : bit absolute PWM1CON.1; 304 PWM1CON_PDC0 : bit absolute PWM1CON.0; 305 ECCPAS : byte absolute $009C; 306 ECCPAS_ECCPASE : bit absolute ECCPAS.7; 307 ECCPAS_ECCPAS2 : bit absolute ECCPAS.6; 308 ECCPAS_ECCPAS1 : bit absolute ECCPAS.5; 309 ECCPAS_ECCPAS0 : bit absolute ECCPAS.4; 310 ECCPAS_PSSAC1 : bit absolute ECCPAS.3; 311 ECCPAS_PSSAC0 : bit absolute ECCPAS.2; 312 ECCPAS_PSSBD1 : bit absolute ECCPAS.1; 313 ECCPAS_PSSBD0 : bit absolute ECCPAS.0; 314 PSTRCON : byte absolute $009D; 315 PSTRCON_STRSYNC : bit absolute PSTRCON.4; 316 PSTRCON_STRD : bit absolute PSTRCON.3; 317 PSTRCON_STRC : bit absolute PSTRCON.2; 318 PSTRCON_STRB : bit absolute PSTRCON.1; 319 PSTRCON_STRA : bit absolute PSTRCON.0; 320 ADRESL : byte absolute $009E; 321 ADCON1 : byte absolute $009F; 322 ADCON1_ADFM : bit absolute ADCON1.7; 323 ADCON1_VCFG1 : bit absolute ADCON1.5; 324 ADCON1_VCFG0 : bit absolute ADCON1.4; 325 WDTCON : byte absolute $0105; 326 WDTCON_WDTPS3 : bit absolute WDTCON.4; 327 WDTCON_WDTPS2 : bit absolute WDTCON.3; 328 WDTCON_WDTPS1 : bit absolute WDTCON.2; 329 WDTCON_WDTPS0 : bit absolute WDTCON.1; 330 WDTCON_SWDTEN : bit absolute WDTCON.0; 331 CM1CON0 : byte absolute $0107; 332 CM1CON0_C1ON : bit absolute CM1CON0.7; 333 CM1CON0_C1OUT : bit absolute CM1CON0.6; 334 CM1CON0_C1OE : bit absolute CM1CON0.5; 335 CM1CON0_C1POL : bit absolute CM1CON0.4; 336 CM1CON0_C1R : bit absolute CM1CON0.2; 337 CM1CON0_C1CH1 : bit absolute CM1CON0.1; 338 CM1CON0_C1CH0 : bit absolute CM1CON0.0; 339 CM2CON0 : byte absolute $0108; 340 CM2CON0_C2ON : bit absolute CM2CON0.7; 341 CM2CON0_C2OUT : bit absolute CM2CON0.6; 342 CM2CON0_C2OE : bit absolute CM2CON0.5; 343 CM2CON0_C2POL : bit absolute CM2CON0.4; 344 CM2CON0_C2R : bit absolute CM2CON0.2; 345 CM2CON0_C2CH1 : bit absolute CM2CON0.1; 346 CM2CON0_C2CH0 : bit absolute CM2CON0.0; 347 CM2CON1 : byte absolute $0109; 348 CM2CON1_MC1OUT : bit absolute CM2CON1.7; 349 CM2CON1_MC2OUT : bit absolute CM2CON1.6; 350 CM2CON1_C1RSEL : bit absolute CM2CON1.5; 351 CM2CON1_C2RSEL : bit absolute CM2CON1.4; 352 CM2CON1_T1GSS : bit absolute CM2CON1.1; 353 CM2CON1_C2SYNC : bit absolute CM2CON1.0; 354 EEDATA : byte absolute $010C; 355 EEADR : byte absolute $010D; 356 EEDATH : byte absolute $010E; 357 EEDATH_EEDATH5 : bit absolute EEDATH.5; 358 EEDATH_EEDATH4 : bit absolute EEDATH.4; 359 EEDATH_EEDATH3 : bit absolute EEDATH.3; 360 EEDATH_EEDATH2 : bit absolute EEDATH.2; 361 EEDATH_EEDATH1 : bit absolute EEDATH.1; 362 EEDATH_EEDATH0 : bit absolute EEDATH.0; 363 EEADRH : byte absolute $010F; 364 EEADRH_EEADRH4 : bit absolute EEADRH.4; 365 EEADRH_EEADRH3 : bit absolute EEADRH.3; 366 EEADRH_EEADRH2 : bit absolute EEADRH.2; 367 EEADRH_EEADRH1 : bit absolute EEADRH.1; 368 EEADRH_EEADRH0 : bit absolute EEADRH.0; 369 SRCON : byte absolute $0185; 370 SRCON_SR1 : bit absolute SRCON.7; 371 SRCON_SR0 : bit absolute SRCON.6; 372 SRCON_C1SEN : bit absolute SRCON.5; 373 SRCON_C2REN : bit absolute SRCON.4; 374 SRCON_PULSS : bit absolute SRCON.3; 375 SRCON_PULSR : bit absolute SRCON.2; 376 SRCON_FVREN : bit absolute SRCON.0; 377 BAUDCTL : byte absolute $0187; 378 BAUDCTL_ABDOVF : bit absolute BAUDCTL.7; 379 BAUDCTL_RCIDL : bit absolute BAUDCTL.6; 380 BAUDCTL_SCKP : bit absolute BAUDCTL.4; 381 BAUDCTL_BRG16 : bit absolute BAUDCTL.3; 382 BAUDCTL_WUE : bit absolute BAUDCTL.1; 383 BAUDCTL_ABDEN : bit absolute BAUDCTL.0; 384 ANSEL : byte absolute $0188; 385 ANSEL_ANS7 : bit absolute ANSEL.7; 386 ANSEL_ANS6 : bit absolute ANSEL.6; 387 ANSEL_ANS5 : bit absolute ANSEL.5; 388 ANSEL_ANS4 : bit absolute ANSEL.4; 389 ANSEL_ANS3 : bit absolute ANSEL.3; 390 ANSEL_ANS2 : bit absolute ANSEL.2; 391 ANSEL_ANS1 : bit absolute ANSEL.1; 392 ANSEL_ANS0 : bit absolute ANSEL.0; 393 ANSELH : byte absolute $0189; 394 ANSELH_ANS13 : bit absolute ANSELH.5; 395 ANSELH_ANS12 : bit absolute ANSELH.4; 396 ANSELH_ANS11 : bit absolute ANSELH.3; 397 ANSELH_ANS10 : bit absolute ANSELH.2; 398 ANSELH_ANS9 : bit absolute ANSELH.1; 399 ANSELH_ANS8 : bit absolute ANSELH.0; 400 EECON1 : byte absolute $018C; 401 EECON1_EEPGD : bit absolute EECON1.7; 402 EECON1_WRERR : bit absolute EECON1.3; 403 EECON1_WREN : bit absolute EECON1.2; 404 EECON1_WR : bit absolute EECON1.1; 405 EECON1_RD : bit absolute EECON1.0; 406 EECON2 : byte absolute $018D; 407 408 409 // -- Define RAM state values -- 410 411 {$CLEAR_STATE_RAM} 412 413 {$SET_STATE_RAM '000-000:SFR:ALLMAPPED'} // Banks 0-3 : INDF 414 {$SET_STATE_RAM '001-001:SFR:ALL'} // Bank 0 : TMR0 415 // Bank 1 : OPTION_REG 416 // Bank 2 : TMR0 417 // Bank 3 : OPTION_REG 418 {$SET_STATE_RAM '002-004:SFR:ALLMAPPED'} // Banks 0-3 : PCL, STATUS, FSR 419 {$SET_STATE_RAM '005-009:SFR:ALL'} // Bank 0 : PORTA, PORTB, PORTC, PORTD, PORTE 420 // Bank 1 : TRISA, TRISB, TRISC, TRISD, TRISE 421 // Bank 2 : WDTCON, PORTB, CM1CON0, CM2CON0, CM2CON1 422 // Bank 3 : SRCON, TRISB, BAUDCTL, ANSEL, ANSELH 423 {$SET_STATE_RAM '00A-00B:SFR:ALLMAPPED'} // Banks 0-3 : PCLATH, INTCON 424 {$SET_STATE_RAM '00C-00D:SFR:ALL'} // Bank 0 : PIR1, PIR2 425 // Bank 1 : PIE1, PIE2 426 // Bank 2 : EEDATA, EEADR 427 // Bank 3 : EECON1, EECON2 428 {$SET_STATE_RAM '00E-01F:SFR'} // Bank 0 : TMR1L, TMR1H, T1CON, TMR2, T2CON, SSPBUF, SSPCON, CCPR1L, CCPR1H, CCP1CON, RCSTA, TXREG, RCREG, CCPR2L, CCPR2H, CCP2CON, ADRESH, ADCON0 429 {$SET_STATE_RAM '020-06F:GPR'} 430 {$SET_STATE_RAM '070-07F:GPR:ALLMAPPED'} 431 {$SET_STATE_RAM '08E-09F:SFR'} // Bank 1 : PCON, OSCCON, OSCTUNE, SSPCON2, PR2, SSPADD, SSPSTAT, WPUB, IOCB, VRCON, TXSTA, SPBRG, SPBRGH, PWM1CON, ECCPAS, PSTRCON, ADRESL, ADCON1 432 {$SET_STATE_RAM '0A0-0EF:GPR'} 433 {$SET_STATE_RAM '10E-10F:SFR'} // Bank 2 : EEDATH, EEADRH 434 {$SET_STATE_RAM '120-16F:GPR'} 435 436 437 // -- Define mapped RAM -- 438 439 {$SET_MAPPED_RAM '101-101:bnk0'} // maps to TMR0 (bank 0) 440 {$SET_MAPPED_RAM '106-106:bnk0'} // maps to PORTB (bank 0) 441 {$SET_MAPPED_RAM '181-181:bnk1'} // maps to OPTION_REG (bank 1) 442 {$SET_MAPPED_RAM '186-186:bnk1'} // maps to TRISB (bank 1) 443 444 445 // -- Un-implemented fields -- 446 447 {$SET_UNIMP_BITS '009:0F'} // PORTE bits 7,6,5,4 un-implemented (read as 0) 448 {$SET_UNIMP_BITS '00A:1F'} // PCLATH bits 7,6,5 un-implemented (read as 0) 449 {$SET_UNIMP_BITS '00C:7F'} // PIR1 bit 7 un-implemented (read as 0) 450 {$SET_UNIMP_BITS '00D:FD'} // PIR2 bit 1 un-implemented (read as 0) 451 {$SET_UNIMP_BITS '012:7F'} // T2CON bit 7 un-implemented (read as 0) 452 {$SET_UNIMP_BITS '01D:3F'} // CCP2CON bits 7,6 un-implemented (read as 0) 453 {$SET_UNIMP_BITS '089:0F'} // TRISE bits 7,6,5,4 un-implemented (read as 0) 454 {$SET_UNIMP_BITS '08C:7F'} // PIE1 bit 7 un-implemented (read as 0) 455 {$SET_UNIMP_BITS '08D:FD'} // PIE2 bit 1 un-implemented (read as 0) 456 {$SET_UNIMP_BITS '08E:33'} // PCON bits 7,6,3,2 un-implemented (read as 0) 457 {$SET_UNIMP_BITS '08F:7F'} // OSCCON bit 7 un-implemented (read as 0) 458 {$SET_UNIMP_BITS '090:1F'} // OSCTUNE bits 7,6,5 un-implemented (read as 0) 459 {$SET_UNIMP_BITS '09D:1F'} // PSTRCON bits 7,6,5 un-implemented (read as 0) 460 {$SET_UNIMP_BITS '09F:B0'} // ADCON1 bits 6,3,2,1,0 un-implemented (read as 0) 461 {$SET_UNIMP_BITS '105:1F'} // WDTCON bits 7,6,5 un-implemented (read as 0) 462 {$SET_UNIMP_BITS '107:F7'} // CM1CON0 bit 3 un-implemented (read as 0) 463 {$SET_UNIMP_BITS '108:F7'} // CM2CON0 bit 3 un-implemented (read as 0) 464 {$SET_UNIMP_BITS '109:F3'} // CM2CON1 bits 3,2 un-implemented (read as 0) 465 {$SET_UNIMP_BITS '10E:3F'} // EEDATH bits 7,6 un-implemented (read as 0) 466 {$SET_UNIMP_BITS '10F:1F'} // EEADRH bits 7,6,5 un-implemented (read as 0) 467 {$SET_UNIMP_BITS '185:FD'} // SRCON bit 1 un-implemented (read as 0) 468 {$SET_UNIMP_BITS '187:DB'} // BAUDCTL bits 5,2 un-implemented (read as 0) 469 {$SET_UNIMP_BITS '189:3F'} // ANSELH bits 7,6 un-implemented (read as 0) 470 {$SET_UNIMP_BITS '18C:8F'} // EECON1 bits 6,5,4 un-implemented (read as 0) 471 472 473 // -- PIN mapping -- 474 475 // Pin 1 : RE3/MCLR/Vpp 476 // Pin 2 : RA0/AN0/ULPWU/C12IN0- 477 // Pin 3 : RA1/AN1/C12IN1- 478 // Pin 4 : RA2/AN2/Vref-/CVref/C2IN+ 479 // Pin 5 : RA3/AN3/Vref+/C1IN+ 480 // Pin 6 : RA4/T0CKI/C1OUT 481 // Pin 7 : RA5/AN4/SS/C2OUT 482 // Pin 8 : RE0/AN5 483 // Pin 9 : RE1/AN6 484 // Pin 10 : RE2/AN7 485 // Pin 11 : Vdd 486 // Pin 12 : Vss 487 // Pin 13 : RA7/OSC1/CLKIN 488 // Pin 14 : RA6/OSC2/CLKOUT 489 // Pin 15 : RC0/T1OSO/T1CKI 490 // Pin 16 : RC1/T1OSI/CCP2 491 // Pin 17 : RC2/P1A/CCP1 492 // Pin 18 : RC3/SCK/SCL 493 // Pin 19 : RD0 494 // Pin 20 : RD1 495 // Pin 21 : RD2 496 // Pin 22 : RD3 497 // Pin 23 : RC4/SDI/SDA 498 // Pin 24 : RC5/SDO 499 // Pin 25 : RC6/TX/CK 500 // Pin 26 : RC7/RX/DT 501 // Pin 27 : RD4 502 // Pin 28 : RD5/P1B 503 // Pin 29 : RD6/P1C 504 // Pin 30 : RD7/P1D 505 // Pin 31 : Vss 506 // Pin 32 : Vdd 507 // Pin 33 : RB0/AN12/INT 508 // Pin 34 : RB1/AN10/C12IN3- 509 // Pin 35 : RB2/AN8 510 // Pin 36 : RB3/AN9/PGM/C12IN2- 511 // Pin 37 : RB4/AN11 512 // Pin 38 : RB5/AN13/T1G 513 // Pin 39 : RB6/ICSPCLK 514 // Pin 40 : RB7/ICSPDAT 515 516 517 // -- RAM to PIN mapping -- 518 519 {$MAP_RAM_TO_PIN '005:0-2,1-3,2-4,3-5,4-6,5-7,6-14,7-13'} // PORTA 520 {$MAP_RAM_TO_PIN '006:0-33,1-34,2-35,3-36,4-37,5-38,6-39,7-40'} // PORTB 521 {$MAP_RAM_TO_PIN '007:0-15,1-16,2-17,3-18,4-23,5-24,6-25,7-26'} // PORTC 522 {$MAP_RAM_TO_PIN '008:0-19,1-20,2-21,3-22,4-27,5-28,6-29,7-30'} // PORTD 523 {$MAP_RAM_TO_PIN '009:0-8,1-9,2-10,3-1'} // PORTE 524 525 526 // -- Bits Configuration -- 527 528 // FOSC : Oscillator Selection bits 529 {$define _FOSC_EXTRC_CLKOUT = $3FFF} // RC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN 530 {$define _FOSC_EXTRC_NOCLKOUT = $3FFE} // RCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN 531 {$define _FOSC_INTRC_CLKOUT = $3FFD} // INTOSC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN 532 {$define _FOSC_INTRC_NOCLKOUT = $3FFC} // INTOSCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN 533 {$define _FOSC_EC = $3FFB} // EC: I/O function on RA6/OSC2/CLKOUT pin, CLKIN on RA7/OSC1/CLKIN 534 {$define _FOSC_HS = $3FFA} // HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN 535 {$define _FOSC_XT = $3FF9} // XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN 536 {$define _FOSC_LP = $3FF8} // LP oscillator: Low-power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN 537 538 // WDTE : Watchdog Timer Enable bit 539 {$define _WDTE_ON = $3FFF} // WDT enabled 540 {$define _WDTE_OFF = $3FF7} // WDT disabled and can be enabled by SWDTEN bit of the WDTCON register 541 542 // PWRTE : Power-up Timer Enable bit 543 {$define _PWRTE_OFF = $3FFF} // PWRT disabled 544 {$define _PWRTE_ON = $3FEF} // PWRT enabled 545 546 // MCLRE : RE3/MCLR pin function select bit 547 {$define _MCLRE_ON = $3FFF} // RE3/MCLR pin function is MCLR 548 {$define _MCLRE_OFF = $3FDF} // RE3/MCLR pin function is digital input, MCLR internally tied to VDD 549 550 // CP : Code Protection bit 551 {$define _CP_OFF = $3FFF} // Program memory code protection is disabled 552 {$define _CP_ON = $3FBF} // Program memory code protection is enabled 553 554 // CPD : Data Code Protection bit 555 {$define _CPD_OFF = $3FFF} // Data memory code protection is disabled 556 {$define _CPD_ON = $3F7F} // Data memory code protection is enabled 557 558 // BOREN : Brown Out Reset Selection bits 559 {$define _BOREN_ON = $3FFF} // BOR enabled 560 {$define _BOREN_NSLEEP = $3EFF} // BOR enabled during operation and disabled in Sleep 561 {$define _BOREN_SBODEN = $3DFF} // BOR controlled by SBOREN bit of the PCON register 562 {$define _BOREN_OFF = $3CFF} // BOR disabled 563 564 // IESO : Internal External Switchover bit 565 {$define _IESO_ON = $3FFF} // Internal/External Switchover mode is enabled 566 {$define _IESO_OFF = $3BFF} // Internal/External Switchover mode is disabled 567 568 // FCMEN : Fail-Safe Clock Monitor Enabled bit 569 {$define _FCMEN_ON = $3FFF} // Fail-Safe Clock Monitor is enabled 570 {$define _FCMEN_OFF = $37FF} // Fail-Safe Clock Monitor is disabled 571 572 // LVP : Low Voltage Programming Enable bit 573 {$define _LVP_ON = $3FFF} // RB3/PGM pin has PGM function, low voltage programming enabled 574 {$define _LVP_OFF = $2FFF} // RB3 pin has digital I/O, HV on MCLR must be used for programming 575 576 // DEBUG : In-Circuit Debugger Mode bit 577 {$define _DEBUG_OFF = $3FFF} // In-Circuit Debugger disabled, RB6/ICSPCLK and RB7/ICSPDAT are general purpose I/O pins 578 {$define _DEBUG_ON = $1FFF} // In_Circuit Debugger enabled, RB6/ICSPCLK and RB7/ICSPDAT are dedicated to the debugger 579 580 // BOR4V : Brown-out Reset Selection bit 581 {$define _BOR4V_BOR21V = $3EFF} // Brown-out Reset set to 2.1V 582 {$define _BOR4V_BOR40V = $3FFF} // Brown-out Reset set to 4.0V 583 584 // WRT : Flash Program Memory Self Write Enable bits 585 {$define _WRT_HALF = $39FF} // 0000h to 07FFh write protected, 0800h to 0FFFh may be modified by EECON control 586 {$define _WRT_1FOURTH = $3BFF} // 0000h to 03FFh write protected, 0400h to 0FFFh may be modified by EECON control 587 {$define _WRT_256 = $3DFF} // 0000h to 00FFh write protected, 0100h to 0FFFh may be modified by EECON control 588 {$define _WRT_OFF = $3FFF} // Write protection off 589 590 implementation 591 end. 592