1 /*
2 DSP M56001 emulation
3 Disassembler
4
5 (C) 2003-2008 ARAnyM developer team
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 #ifdef HAVE_CONFIG_H
23 #include "config.h"
24 #endif
25
26 #include <string.h>
27
28 #include "dsp_core.h"
29 #include "dsp_cpu.h"
30 #include "dsp_disasm.h"
31
32 #define DEBUG 0
33
34 /* More disasm infos, if wanted */
35 #define DSP_DISASM_REG_PC 0
36
37 /**********************************
38 * Defines
39 **********************************/
40
41 #define BITMASK(x) ((1<<(x))-1)
42
43 /**********************************
44 * Variables
45 **********************************/
46
47 /* Current instruction */
48 static Uint32 cur_inst;
49
50 /* Previous instruction */
51 static Uint32 prev_inst_pc = 0x10000; /* Init to an invalid value */
52
53 static dsp_core_t *dsp_core;
54
dsp56k_disasm_init(dsp_core_t * my_dsp_core)55 void dsp56k_disasm_init(dsp_core_t *my_dsp_core)
56 {
57 dsp_core = my_dsp_core;
58 }
59
60 /**********************************
61 * Register change
62 **********************************/
63
64 static Uint32 registers_save[64];
65 static Uint32 registers_changed[64];
66 #if DSP_DISASM_REG_PC
67 static Uint32 pc_save;
68 #endif
69
70 static const char *registers_name[64]={
71 "???","???","???","???",
72 "x0","x1","y0","y1",
73 "a0","b0","a2","b2",
74 "a1","b1","a","b",
75
76 "r0","r1","r2","r3",
77 "r4","r5","r6","r7",
78 "n0","n1","n2","n3",
79 "n4","n5","n6","n7",
80
81 "m0","m1","m2","m3",
82 "m4","m5","m6","m7",
83 "???","???","???","???",
84 "???","???","???","???",
85
86 "???","???","???","???",
87 "???","???","???","???",
88 "???","sr","omr","sp",
89 "ssh","ssl","la","lc"
90 };
91
dsp56k_disasm_reg_read(void)92 void dsp56k_disasm_reg_read(void)
93 {
94 memcpy(registers_save, dsp_core->registers , sizeof(registers_save));
95 memset(registers_changed, 0, sizeof(registers_changed));
96 #if DSP_DISASM_REG_PC
97 pc_save = dsp_core->pc;
98 #endif
99 }
100
dsp56k_disasm_reg_compare(void)101 void dsp56k_disasm_reg_compare(void)
102 {
103 int i;
104
105 for (i=0;i<64;i++) {
106 if (!registers_changed[i]) {
107 continue;
108 }
109
110 switch(i) {
111 case DSP_REG_X0:
112 case DSP_REG_X1:
113 case DSP_REG_Y0:
114 case DSP_REG_Y1:
115 case DSP_REG_A0:
116 case DSP_REG_A1:
117 case DSP_REG_B0:
118 case DSP_REG_B1:
119 fprintf(stderr,"Dsp: Reg: %s: 0x%06x -> 0x%06x\n", registers_name[i], registers_save[i] & BITMASK(24), dsp_core->registers[i] & BITMASK(24));
120 break;
121 case DSP_REG_R0:
122 case DSP_REG_R1:
123 case DSP_REG_R2:
124 case DSP_REG_R3:
125 case DSP_REG_R4:
126 case DSP_REG_R5:
127 case DSP_REG_R6:
128 case DSP_REG_R7:
129 case DSP_REG_M0:
130 case DSP_REG_M1:
131 case DSP_REG_M2:
132 case DSP_REG_M3:
133 case DSP_REG_M4:
134 case DSP_REG_M5:
135 case DSP_REG_M6:
136 case DSP_REG_M7:
137 case DSP_REG_N0:
138 case DSP_REG_N1:
139 case DSP_REG_N2:
140 case DSP_REG_N3:
141 case DSP_REG_N4:
142 case DSP_REG_N5:
143 case DSP_REG_N6:
144 case DSP_REG_N7:
145 case DSP_REG_SR:
146 case DSP_REG_LA:
147 case DSP_REG_LC:
148 fprintf(stderr,"Dsp: Reg: %s: 0x%04x -> 0x%04x\n", registers_name[i], registers_save[i] & BITMASK(16), dsp_core->registers[i] & BITMASK(16));
149 break;
150 case DSP_REG_A2:
151 case DSP_REG_B2:
152 case DSP_REG_OMR:
153 case DSP_REG_SP:
154 case DSP_REG_SSH:
155 case DSP_REG_SSL:
156 fprintf(stderr,"Dsp: Reg: %s: 0x%02x -> 0x%02x\n", registers_name[i], registers_save[i] & BITMASK(8), dsp_core->registers[i] & BITMASK(8));
157 break;
158 case DSP_REG_A:
159 case DSP_REG_B:
160 {
161 fprintf(stderr,"Dsp: Reg: %s: 0x%02x:%06x:%06x -> 0x%02x:%06x:%06x\n",
162 registers_name[i],
163 registers_save[DSP_REG_A2+(i & 1)] & BITMASK(8),
164 registers_save[DSP_REG_A1+(i & 1)] & BITMASK(24),
165 registers_save[DSP_REG_A0+(i & 1)] & BITMASK(24),
166 dsp_core->registers[DSP_REG_A2+(i & 1)] & BITMASK(8),
167 dsp_core->registers[DSP_REG_A1+(i & 1)] & BITMASK(24),
168 dsp_core->registers[DSP_REG_A0+(i & 1)] & BITMASK(24)
169 );
170 }
171 break;
172 }
173 }
174 #if DSP_DISASM_REG_PC
175 if (pc_save != dsp_core->pc) {
176 fprintf(stderr,"Dsp: Reg: pc: 0x%04x -> 0x%04x\n", pc_save, dsp_core->pc);
177 }
178 #endif
179 }
180
181 /**********************************
182 * Opcode disassembler
183 **********************************/
184
185 static Uint32 read_memory(Uint32 currPc);
186
187 typedef void (*dsp_emul_t)(void);
188
189 static void opcode8h_0(void);
190 static void opcode8h_1(void);
191 static void opcode8h_4(void);
192 static void opcode8h_6(void);
193 static void opcode8h_8(void);
194 static void opcode8h_a(void);
195 static void opcode8h_b(void);
196
197 static int dsp_calc_ea(Uint32 ea_mode, char *dest);
198 static void dsp_calc_cc(Uint32 cc_mode, char *dest);
199 static void dsp_undefined(void);
200
201 /* Instructions without parallel moves */
202 static void dsp_andi(void);
203 static void dsp_bchg(void);
204 static void dsp_bclr(void);
205 static void dsp_bset(void);
206 static void dsp_btst(void);
207 static void dsp_div(void);
208 static void dsp_do(void);
209 static void dsp_enddo(void);
210 static void dsp_illegal(void);
211 static void dsp_jcc(void);
212 static void dsp_jclr(void);
213 static void dsp_jmp(void);
214 static void dsp_jscc(void);
215 static void dsp_jsclr(void);
216 static void dsp_jset(void);
217 static void dsp_jsr(void);
218 static void dsp_jsset(void);
219 static void dsp_lua(void);
220 static void dsp_movec(void);
221 static void dsp_movem(void);
222 static void dsp_movep(void);
223 static void dsp_nop(void);
224 static void dsp_norm(void);
225 static void dsp_ori(void);
226 static void dsp_rep(void);
227 static void dsp_reset(void);
228 static void dsp_rti(void);
229 static void dsp_rts(void);
230 static void dsp_stop(void);
231 static void dsp_swi(void);
232 static void dsp_tcc(void);
233 static void dsp_wait(void);
234
235 static void dsp_do_0(void);
236 static void dsp_do_2(void);
237 static void dsp_do_4(void);
238 static void dsp_do_c(void);
239 static void dsp_movec_reg(void);
240 static void dsp_movec_aa(void);
241 static void dsp_movec_ea(void);
242 static void dsp_movec_imm(void);
243 static void dsp_movep_0(void);
244 static void dsp_movep_1(void);
245 static void dsp_movep_2(void);
246 static void dsp_rep_aa(void);
247 static void dsp_rep_imm(void);
248 static void dsp_rep_ea(void);
249 static void dsp_rep_reg(void);
250
251 /* Parallel moves */
252 static void dsp_pm(void);
253 static void dsp_pm_0(void);
254 static void dsp_pm_1(void);
255 static void dsp_pm_2(void);
256 static void dsp_pm_4(void);
257 static void dsp_pm_8(void);
258
259 /* Instructions with parallel moves */
260 static void dsp_abs(void);
261 static void dsp_adc(void);
262 static void dsp_add(void);
263 static void dsp_addl(void);
264 static void dsp_addr(void);
265 static void dsp_and(void);
266 static void dsp_asl(void);
267 static void dsp_asr(void);
268 static void dsp_clr(void);
269 static void dsp_cmp(void);
270 static void dsp_cmpm(void);
271 static void dsp_eor(void);
272 static void dsp_lsl(void);
273 static void dsp_lsr(void);
274 static void dsp_mac(void);
275 static void dsp_macr(void);
276 static void dsp_move(void);
277 static void dsp_move_nopm(void);
278 static void dsp_mpy(void);
279 static void dsp_mpyr(void);
280 static void dsp_neg(void);
281 static void dsp_not(void);
282 static void dsp_or(void);
283 static void dsp_rnd(void);
284 static void dsp_rol(void);
285 static void dsp_ror(void);
286 static void dsp_sbc(void);
287 static void dsp_sub(void);
288 static void dsp_subl(void);
289 static void dsp_subr(void);
290 static void dsp_tfr(void);
291 static void dsp_tst(void);
292
293 static dsp_emul_t opcodes8h[16]={
294 opcode8h_0,
295 opcode8h_1,
296 dsp_tcc,
297 dsp_tcc,
298 opcode8h_4,
299 dsp_movec,
300 opcode8h_6,
301 dsp_movem,
302 opcode8h_8,
303 opcode8h_8,
304 opcode8h_a,
305 opcode8h_b,
306 dsp_jmp,
307 dsp_jsr,
308 dsp_jcc,
309 dsp_jscc
310 };
311
312 static dsp_emul_t opcodes_0809[16]={
313 dsp_move_nopm,
314 dsp_move_nopm,
315 dsp_move_nopm,
316 dsp_move_nopm,
317
318 dsp_movep,
319 dsp_movep,
320 dsp_movep,
321 dsp_movep,
322
323 dsp_move_nopm,
324 dsp_move_nopm,
325 dsp_move_nopm,
326 dsp_move_nopm,
327
328 dsp_movep,
329 dsp_movep,
330 dsp_movep,
331 dsp_movep
332 };
333
334 static dsp_emul_t opcodes_0a[32]={
335 dsp_bclr,
336 dsp_bset,
337 dsp_bclr,
338 dsp_bset,
339 dsp_jclr,
340 dsp_jset,
341 dsp_jclr,
342 dsp_jset,
343
344 dsp_bclr,
345 dsp_bset,
346 dsp_bclr,
347 dsp_bset,
348 dsp_jclr,
349 dsp_jset,
350 dsp_jclr,
351 dsp_jset,
352
353 dsp_bclr,
354 dsp_bset,
355 dsp_bclr,
356 dsp_bset,
357 dsp_jclr,
358 dsp_jset,
359 dsp_jclr,
360 dsp_jset,
361
362 dsp_jclr,
363 dsp_jset,
364 dsp_bclr,
365 dsp_bset,
366 dsp_jmp,
367 dsp_jcc,
368 dsp_undefined,
369 dsp_undefined
370 };
371
372 static dsp_emul_t opcodes_0b[32]={
373 dsp_bchg,
374 dsp_btst,
375 dsp_bchg,
376 dsp_btst,
377 dsp_jsclr,
378 dsp_jsset,
379 dsp_jsclr,
380 dsp_jsset,
381
382 dsp_bchg,
383 dsp_btst,
384 dsp_bchg,
385 dsp_btst,
386 dsp_jsclr,
387 dsp_jsset,
388 dsp_jsclr,
389 dsp_jsset,
390
391 dsp_bchg,
392 dsp_btst,
393 dsp_bchg,
394 dsp_btst,
395 dsp_jsclr,
396 dsp_jsset,
397 dsp_jsclr,
398 dsp_jsset,
399
400 dsp_jsclr,
401 dsp_jsclr,
402 dsp_bchg,
403 dsp_btst,
404 dsp_jsr,
405 dsp_jscc,
406 dsp_undefined,
407 dsp_undefined
408 };
409
410 static dsp_emul_t opcodes_alu003f[64]={
411 /* 0x00 - 0x0f */
412 dsp_move,
413 dsp_tfr,
414 dsp_addr,
415 dsp_tst,
416 dsp_undefined,
417 dsp_cmp,
418 dsp_subr,
419 dsp_cmpm,
420 dsp_undefined,
421 dsp_tfr,
422 dsp_addr,
423 dsp_tst,
424 dsp_undefined,
425 dsp_cmp,
426 dsp_subr,
427 dsp_cmpm,
428
429 /* 0x10 - 0x1f */
430 dsp_add,
431 dsp_rnd,
432 dsp_addl,
433 dsp_clr,
434 dsp_sub,
435 dsp_undefined,
436 dsp_subl,
437 dsp_not,
438 dsp_add,
439 dsp_rnd,
440 dsp_addl,
441 dsp_clr,
442 dsp_sub,
443 dsp_undefined,
444 dsp_subl,
445 dsp_not,
446
447 /* 0x20 - 0x2f */
448 dsp_add,
449 dsp_adc,
450 dsp_asr,
451 dsp_lsr,
452 dsp_sub,
453 dsp_sbc,
454 dsp_abs,
455 dsp_ror,
456 dsp_add,
457 dsp_adc,
458 dsp_asr,
459 dsp_lsr,
460 dsp_sub,
461 dsp_sbc,
462 dsp_abs,
463 dsp_ror,
464
465 /* 0x30 - 0x3f */
466 dsp_add,
467 dsp_adc,
468 dsp_asl,
469 dsp_lsl,
470 dsp_sub,
471 dsp_sbc,
472 dsp_neg,
473 dsp_rol,
474 dsp_add,
475 dsp_adc,
476 dsp_asl,
477 dsp_lsl,
478 dsp_sub,
479 dsp_sbc,
480 dsp_neg,
481 dsp_rol
482 };
483
484 static dsp_emul_t opcodes_alu407f[16]={
485 dsp_add,
486 dsp_tfr,
487 dsp_or,
488 dsp_eor,
489 dsp_sub,
490 dsp_cmp,
491 dsp_and,
492 dsp_cmpm,
493 dsp_add,
494 dsp_tfr,
495 dsp_or,
496 dsp_eor,
497 dsp_sub,
498 dsp_cmp,
499 dsp_and,
500 dsp_cmpm
501 };
502
503 static dsp_emul_t opcodes_alu80ff[4]={
504 dsp_mpy,
505 dsp_mpyr,
506 dsp_mac,
507 dsp_macr
508 };
509
510 static dsp_emul_t opcodes_do[16]={
511 dsp_do_0,
512 dsp_undefined,
513 dsp_do_2,
514 dsp_undefined,
515
516 dsp_do_4,
517 dsp_undefined,
518 dsp_do_2,
519 dsp_undefined,
520
521 dsp_undefined,
522 dsp_undefined,
523 dsp_do_2,
524 dsp_undefined,
525
526 dsp_do_c,
527 dsp_undefined,
528 dsp_do_2,
529 dsp_undefined
530 };
531
532 static dsp_emul_t opcodes_movec[16]={
533 dsp_undefined,
534 dsp_undefined,
535 dsp_undefined,
536 dsp_undefined,
537
538 dsp_undefined,
539 dsp_undefined,
540 dsp_undefined,
541 dsp_movec_reg,
542
543 dsp_undefined,
544 dsp_movec_aa,
545 dsp_undefined,
546 dsp_movec_ea,
547
548 dsp_undefined,
549 dsp_movec_imm,
550 dsp_undefined,
551 dsp_movec_imm
552 };
553
554 static dsp_emul_t opcodes_movep[4]={
555 dsp_movep_0,
556 dsp_movep_1,
557 dsp_movep_2,
558 dsp_movep_2
559 };
560
561 static dsp_emul_t opcodes_rep[16]={
562 dsp_undefined,
563 dsp_rep_aa,
564 dsp_undefined,
565 dsp_rep_imm,
566
567 dsp_undefined,
568 dsp_rep_ea,
569 dsp_undefined,
570 dsp_rep_imm,
571
572 dsp_undefined,
573 dsp_undefined,
574 dsp_undefined,
575 dsp_rep_imm,
576
577 dsp_undefined,
578 dsp_rep_reg,
579 dsp_undefined,
580 dsp_rep_imm
581 };
582
583 static dsp_emul_t opcodes_parmove[16]={
584 dsp_pm_0,
585 dsp_pm_1,
586 dsp_pm_2,
587 dsp_pm_2,
588 dsp_pm_4,
589 dsp_pm_4,
590 dsp_pm_4,
591 dsp_pm_4,
592
593 dsp_pm_8,
594 dsp_pm_8,
595 dsp_pm_8,
596 dsp_pm_8,
597 dsp_pm_8,
598 dsp_pm_8,
599 dsp_pm_8,
600 dsp_pm_8
601 };
602
603 static int registers_tcc[16][2]={
604 {DSP_REG_B,DSP_REG_A},
605 {DSP_REG_A,DSP_REG_B},
606 {DSP_REG_NULL,DSP_REG_NULL},
607 {DSP_REG_NULL,DSP_REG_NULL},
608
609 {DSP_REG_NULL,DSP_REG_NULL},
610 {DSP_REG_NULL,DSP_REG_NULL},
611 {DSP_REG_NULL,DSP_REG_NULL},
612 {DSP_REG_NULL,DSP_REG_NULL},
613
614 {DSP_REG_X0,DSP_REG_A},
615 {DSP_REG_X0,DSP_REG_B},
616 {DSP_REG_Y0,DSP_REG_A},
617 {DSP_REG_Y0,DSP_REG_B},
618
619 {DSP_REG_X1,DSP_REG_A},
620 {DSP_REG_X1,DSP_REG_B},
621 {DSP_REG_Y1,DSP_REG_A},
622 {DSP_REG_Y1,DSP_REG_B}
623 };
624
625 static const char *registers_lmove[8]={
626 "a10",
627 "b10",
628 "x",
629 "y",
630 "a",
631 "b",
632 "ab",
633 "ba"
634 };
635
636 static int disasm_registers_lmove[8][2]={
637 {DSP_REG_A1,DSP_REG_A0}, /* A10 */
638 {DSP_REG_B1,DSP_REG_B0}, /* B10 */
639 {DSP_REG_X1,DSP_REG_X0}, /* X */
640 {DSP_REG_Y1,DSP_REG_Y0}, /* Y */
641 {DSP_REG_A,DSP_REG_A}, /* A */
642 {DSP_REG_B,DSP_REG_B}, /* B */
643 {DSP_REG_A,DSP_REG_B}, /* AB */
644 {DSP_REG_B,DSP_REG_A} /* BA */
645 };
646
647 static const char *ea_names[9]={
648 "(r%d)-n%d", /* 000xxx */
649 "(r%d)+n%d", /* 001xxx */
650 "(r%d)-", /* 010xxx */
651 "(r%d)+", /* 011xxx */
652 "(r%d)", /* 100xxx */
653 "(r%d+n%d)", /* 101xxx */
654 "0x%04x", /* 110000 */
655 "-(r%d)", /* 111xxx */
656 "0x%06x" /* 110100 */
657 };
658
659 static const char *cc_name[16]={
660 "cc",
661 "ge",
662 "ne",
663 "pl",
664 "nn",
665 "ec",
666 "lc",
667 "gt",
668
669 "cs",
670 "lt",
671 "eq",
672 "mi",
673 "nr",
674 "es",
675 "ls",
676 "le"
677 };
678
679 static char parallelmove_name[64];
680
dsp56k_disasm(void)681 void dsp56k_disasm(void)
682 {
683 Uint32 value;
684
685 if (prev_inst_pc == dsp_core->pc){
686 return;
687 }
688 prev_inst_pc = dsp_core->pc;
689
690 cur_inst = read_memory(dsp_core->pc);
691
692 strcpy(parallelmove_name, "");
693
694 value = (cur_inst >> 16) & BITMASK(8);
695 if ((value < 0x10) && ((cur_inst & 0xfe4000) != 0x080000)) {
696 opcodes8h[value]();
697 } else {
698 dsp_pm();
699 value = cur_inst & BITMASK(8);
700 if (value < 0x40) {
701 opcodes_alu003f[value]();
702 } else if (value < 0x80) {
703 value &= BITMASK(4);
704 opcodes_alu407f[value]();
705 } else {
706 value &= BITMASK(2);
707 opcodes_alu80ff[value]();
708 }
709 }
710 }
711
dsp56k_disasm_force_reg_changed(int num_dsp_reg)712 void dsp56k_disasm_force_reg_changed(int num_dsp_reg)
713 {
714 registers_changed[num_dsp_reg]=1;
715 }
716
read_memory(Uint32 currPc)717 static Uint32 read_memory(Uint32 currPc)
718 {
719 Uint32 value;
720
721 if (currPc<0x200) {
722 value = dsp_core->ramint[DSP_SPACE_P][currPc];
723 } else {
724 value = dsp_core->ram[DSP_SPACE_P][currPc & (DSP_RAMSIZE-1)];
725 }
726
727 return value & BITMASK(24);
728 }
729
730 /**********************************
731 * Conditions code calculation
732 **********************************/
733
dsp_calc_cc(Uint32 cc_mode,char * dest)734 static void dsp_calc_cc(Uint32 cc_mode, char *dest)
735 {
736 strcpy(dest, cc_name[cc_mode & BITMASK(4)]);
737 }
738
739 /**********************************
740 * Effective address calculation
741 **********************************/
742
dsp_calc_ea(Uint32 ea_mode,char * dest)743 static int dsp_calc_ea(Uint32 ea_mode, char *dest)
744 {
745 int value, retour, numreg;
746
747 value = (ea_mode >> 3) & BITMASK(3);
748 numreg = ea_mode & BITMASK(3);
749 retour = 0;
750 switch (value) {
751 case 0:
752 /* (Rx)-Nx */
753 sprintf(dest, ea_names[value], numreg, numreg);
754 registers_changed[DSP_REG_R0+numreg]=1;
755 break;
756 case 1:
757 /* (Rx)+Nx */
758 sprintf(dest, ea_names[value], numreg, numreg);
759 registers_changed[DSP_REG_R0+numreg]=1;
760 break;
761 case 5:
762 /* (Rx+Nx) */
763 sprintf(dest, ea_names[value], numreg, numreg);
764 break;
765 case 2:
766 /* (Rx)- */
767 sprintf(dest, ea_names[value], numreg);
768 registers_changed[DSP_REG_R0+numreg]=1;
769 break;
770 case 3:
771 /* (Rx)+ */
772 sprintf(dest, ea_names[value], numreg);
773 registers_changed[DSP_REG_R0+numreg]=1;
774 break;
775 case 4:
776 /* (Rx) */
777 sprintf(dest, ea_names[value], numreg);
778 break;
779 case 7:
780 /* -(Rx) */
781 sprintf(dest, ea_names[value], numreg);
782 registers_changed[DSP_REG_R0+numreg]=1;
783 break;
784 case 6:
785 switch ((ea_mode >> 2) & 1) {
786 case 0:
787 /* Absolute address */
788 sprintf(dest, ea_names[value], read_memory(dsp_core->pc+1));
789 break;
790 case 1:
791 /* Immediate value */
792 sprintf(dest, ea_names[8], read_memory(dsp_core->pc+1));
793 retour = 1;
794 break;
795 }
796 break;
797 }
798 return retour;
799 }
800
opcode8h_0(void)801 static void opcode8h_0(void)
802 {
803 Uint32 value;
804
805 if (cur_inst <= 0x00008c) {
806 switch(cur_inst) {
807 case 0x000000:
808 dsp_nop();
809 break;
810 case 0x000004:
811 dsp_rti();
812 break;
813 case 0x000005:
814 dsp_illegal();
815 break;
816 case 0x000006:
817 dsp_swi();
818 break;
819 case 0x00000c:
820 dsp_rts();
821 break;
822 case 0x000084:
823 dsp_reset();
824 break;
825 case 0x000086:
826 dsp_wait();
827 break;
828 case 0x000087:
829 dsp_stop();
830 break;
831 case 0x00008c:
832 dsp_enddo();
833 break;
834 }
835 } else {
836 value = cur_inst & 0xf8;
837 switch (value) {
838 case 0x0000b8:
839 dsp_andi();
840 break;
841 case 0x0000f8:
842 dsp_ori();
843 break;
844 }
845 }
846 }
847
opcode8h_1(void)848 static void opcode8h_1(void)
849 {
850 switch(cur_inst & 0xfff8c7) {
851 case 0x018040:
852 dsp_div();
853 break;
854 case 0x01c805:
855 dsp_norm();
856 break;
857 }
858 }
859
opcode8h_4(void)860 static void opcode8h_4(void)
861 {
862 switch((cur_inst>>5) & BITMASK(3)) {
863 case 0:
864 dsp_lua();
865 break;
866 case 5:
867 dsp_movec();
868 break;
869 }
870 }
871
opcode8h_6(void)872 static void opcode8h_6(void)
873 {
874 if (cur_inst & (1<<5)) {
875 dsp_rep();
876 } else {
877 dsp_do();
878 }
879 }
880
opcode8h_8(void)881 static void opcode8h_8(void)
882 {
883 Uint32 value;
884
885 value = (cur_inst >> 12) & BITMASK(4);
886 opcodes_0809[value]();
887 }
888
opcode8h_a(void)889 static void opcode8h_a(void)
890 {
891 Uint32 value;
892
893 value = (cur_inst >> 11) & (BITMASK(2)<<3);
894 value |= (cur_inst >> 5) & BITMASK(3);
895
896 opcodes_0a[value]();
897 }
898
opcode8h_b(void)899 static void opcode8h_b(void)
900 {
901 Uint32 value;
902
903 value = (cur_inst >> 11) & (BITMASK(2)<<3);
904 value |= (cur_inst >> 5) & BITMASK(3);
905
906 opcodes_0b[value]();
907 }
908
909 /**********************************
910 * Non-parallel moves instructions
911 **********************************/
912
dsp_undefined(void)913 static void dsp_undefined(void)
914 {
915 fprintf(stderr,"Dsp: 0x%04x: 0x%06x unknown instruction\n",dsp_core->pc, cur_inst);
916 }
917
dsp_andi(void)918 static void dsp_andi(void)
919 {
920 const char *regname;
921
922 switch(cur_inst & BITMASK(2)) {
923 case 0:
924 regname="mr";
925 registers_changed[DSP_REG_SR]=1;
926 break;
927 case 1:
928 regname="ccr";
929 registers_changed[DSP_REG_SR]=1;
930 break;
931 case 2:
932 regname="omr";
933 registers_changed[DSP_REG_OMR]=1;
934 break;
935 default:
936 regname="???";
937 break;
938 }
939
940 registers_changed[DSP_REG_SR]=1;
941
942 fprintf(stderr,"Dsp: 0x%04x: andi #0x%02x,%s\n",
943 dsp_core->pc,
944 (cur_inst>>8) & BITMASK(8),
945 regname
946 );
947 }
948
dsp_bchg(void)949 static void dsp_bchg(void)
950 {
951 char name[18], addr_name[16];
952 Uint32 memspace, value, numbit;
953
954 memspace = (cur_inst>>6) & 1;
955 value = (cur_inst>>8) & BITMASK(6);
956 numbit = cur_inst & BITMASK(5);
957
958 switch((cur_inst>>14) & BITMASK(2)) {
959 case 0:
960 /* bchg #n,x:aa */
961 /* bchg #n,y:aa */
962 if (memspace) {
963 sprintf(name,"y:0x%04x",value);
964 } else {
965 sprintf(name,"x:0x%04x",value);
966 }
967 break;
968 case 1:
969 /* bchg #n,x:ea */
970 /* bchg #n,y:ea */
971 dsp_calc_ea(value, addr_name);
972 if (memspace) {
973 sprintf(name,"y:%s",addr_name);
974 } else {
975 sprintf(name,"x:%s",addr_name);
976 }
977 break;
978 case 2:
979 /* bchg #n,x:pp */
980 /* bchg #n,y:pp */
981 if (memspace) {
982 sprintf(name,"y:0x%04x",value+0xffc0);
983 } else {
984 sprintf(name,"x:0x%04x",value+0xffc0);
985 }
986 break;
987 case 3:
988 /* bchg #n,R */
989 sprintf(name,"%s",registers_name[value]);
990 registers_changed[value]=1;
991 break;
992 }
993
994 registers_changed[DSP_REG_SR]=1;
995
996 fprintf(stderr,"Dsp: 0x%04x: bchg #%d,%s\n",dsp_core->pc, numbit, name);
997 }
998
dsp_bclr(void)999 static void dsp_bclr(void)
1000 {
1001 char name[18], addr_name[16];
1002 Uint32 memspace, value, numbit;
1003
1004 memspace = (cur_inst>>6) & 1;
1005 value = (cur_inst>>8) & BITMASK(6);
1006 numbit = cur_inst & BITMASK(5);
1007
1008 switch((cur_inst>>14) & BITMASK(2)) {
1009 case 0:
1010 /* bclr #n,x:aa */
1011 /* bclr #n,y:aa */
1012 if (memspace) {
1013 sprintf(name,"y:0x%04x",value);
1014 } else {
1015 sprintf(name,"x:0x%04x",value);
1016 }
1017 break;
1018 case 1:
1019 /* bclr #n,x:ea */
1020 /* bclr #n,y:ea */
1021 dsp_calc_ea(value, addr_name);
1022 if (memspace) {
1023 sprintf(name,"y:%s",addr_name);
1024 } else {
1025 sprintf(name,"x:%s",addr_name);
1026 }
1027 break;
1028 case 2:
1029 /* bclr #n,x:pp */
1030 /* bclr #n,y:pp */
1031 if (memspace) {
1032 sprintf(name,"y:0x%04x",value+0xffc0);
1033 } else {
1034 sprintf(name,"x:0x%04x",value+0xffc0);
1035 }
1036 break;
1037 case 3:
1038 /* bclr #n,R */
1039 sprintf(name,"%s",registers_name[value]);
1040 registers_changed[value]=1;
1041 break;
1042 }
1043
1044 registers_changed[DSP_REG_SR]=1;
1045
1046 fprintf(stderr,"Dsp: 0x%04x: bclr #%d,%s\n",dsp_core->pc, numbit, name);
1047 }
1048
dsp_bset(void)1049 static void dsp_bset(void)
1050 {
1051 char name[18], addr_name[16];
1052 Uint32 memspace, value, numbit;
1053
1054 memspace = (cur_inst>>6) & 1;
1055 value = (cur_inst>>8) & BITMASK(6);
1056 numbit = cur_inst & BITMASK(5);
1057
1058 switch((cur_inst>>14) & BITMASK(2)) {
1059 case 0:
1060 /* bset #n,x:aa */
1061 /* bset #n,y:aa */
1062 if (memspace) {
1063 sprintf(name,"y:0x%04x",value);
1064 } else {
1065 sprintf(name,"x:0x%04x",value);
1066 }
1067 break;
1068 case 1:
1069 /* bset #n,x:ea */
1070 /* bset #n,y:ea */
1071 dsp_calc_ea(value, addr_name);
1072 if (memspace) {
1073 sprintf(name,"y:%s",addr_name);
1074 } else {
1075 sprintf(name,"x:%s",addr_name);
1076 }
1077 break;
1078 case 2:
1079 /* bset #n,x:pp */
1080 /* bset #n,y:pp */
1081 if (memspace) {
1082 sprintf(name,"y:0x%04x",value+0xffc0);
1083 } else {
1084 sprintf(name,"x:0x%04x",value+0xffc0);
1085 }
1086 break;
1087 case 3:
1088 /* bset #n,R */
1089 sprintf(name,"%s",registers_name[value]);
1090 registers_changed[value]=1;
1091 break;
1092 }
1093
1094 registers_changed[DSP_REG_SR]=1;
1095
1096 fprintf(stderr,"Dsp: 0x%04x: bset #%d,%s\n",dsp_core->pc, numbit, name);
1097 }
1098
dsp_btst(void)1099 static void dsp_btst(void)
1100 {
1101 char name[18], addr_name[16];
1102 Uint32 memspace, value, numbit;
1103
1104 memspace = (cur_inst>>6) & 1;
1105 value = (cur_inst>>8) & BITMASK(6);
1106 numbit = cur_inst & BITMASK(5);
1107
1108 switch((cur_inst>>14) & BITMASK(2)) {
1109 case 0:
1110 /* btst #n,x:aa */
1111 /* btst #n,y:aa */
1112 if (memspace) {
1113 sprintf(name,"y:0x%04x",value);
1114 } else {
1115 sprintf(name,"x:0x%04x",value);
1116 }
1117 break;
1118 case 1:
1119 /* btst #n,x:ea */
1120 /* btst #n,y:ea */
1121 dsp_calc_ea(value, addr_name);
1122 if (memspace) {
1123 sprintf(name,"y:%s",addr_name);
1124 } else {
1125 sprintf(name,"x:%s",addr_name);
1126 }
1127 break;
1128 case 2:
1129 /* btst #n,x:pp */
1130 /* btst #n,y:pp */
1131 if (memspace) {
1132 sprintf(name,"y:0x%04x",value+0xffc0);
1133 } else {
1134 sprintf(name,"x:0x%04x",value+0xffc0);
1135 }
1136 break;
1137 case 3:
1138 /* btst #n,R */
1139 sprintf(name,"%s",registers_name[value]);
1140 registers_changed[value]=1;
1141 break;
1142 }
1143
1144 registers_changed[DSP_REG_SR]=1;
1145
1146 fprintf(stderr,"Dsp: 0x%04x: btst #%d,%s\n",dsp_core->pc, numbit, name);
1147 }
1148
dsp_div(void)1149 static void dsp_div(void)
1150 {
1151 Uint32 srcreg=DSP_REG_NULL, destreg;
1152
1153 switch((cur_inst>>4) & BITMASK(2)) {
1154 case 0:
1155 srcreg = DSP_REG_X0;
1156 break;
1157 case 1:
1158 srcreg = DSP_REG_Y0;
1159 break;
1160 case 2:
1161 srcreg = DSP_REG_X1;
1162 break;
1163 case 3:
1164 srcreg = DSP_REG_Y1;
1165 break;
1166 }
1167 destreg = DSP_REG_A+((cur_inst>>3) & 1);
1168 registers_changed[destreg]=1;
1169 registers_changed[DSP_REG_SR]=1;
1170
1171 fprintf(stderr,"Dsp: 0x%04x: div %s,%s\n",dsp_core->pc, registers_name[srcreg],registers_name[destreg]);
1172 }
1173
dsp_do(void)1174 static void dsp_do(void)
1175 {
1176 Uint32 value;
1177
1178 value = (cur_inst>>12) & (BITMASK(2)<<2);
1179 value |= (cur_inst>>6) & 1<<1;
1180 value |= (cur_inst>>5) & 1;
1181
1182 opcodes_do[value]();
1183
1184 registers_changed[DSP_REG_LA]=1;
1185 registers_changed[DSP_REG_LC]=1;
1186 registers_changed[DSP_REG_SR]=1;
1187 }
1188
dsp_do_0(void)1189 static void dsp_do_0(void)
1190 {
1191 char name[16];
1192
1193 if (cur_inst & (1<<6)) {
1194 sprintf(name, "y:0x%04x", (cur_inst>>8) & BITMASK(6));
1195 } else {
1196 sprintf(name, "x:0x%04x", (cur_inst>>8) & BITMASK(6));
1197 }
1198
1199 fprintf(stderr,"Dsp: 0x%04x: do %s,p:0x%04x\n",
1200 dsp_core->pc,
1201 name,
1202 read_memory(dsp_core->pc+1)
1203 );
1204 }
1205
dsp_do_2(void)1206 static void dsp_do_2(void)
1207 {
1208 fprintf(stderr,"Dsp: 0x%04x: do #0x%04x,p:0x%04x\n",
1209 dsp_core->pc,
1210 ((cur_inst>>8) & BITMASK(8))|((cur_inst & BITMASK(4))<<8),
1211 read_memory(dsp_core->pc+1)
1212 );
1213 }
1214
dsp_do_4(void)1215 static void dsp_do_4(void)
1216 {
1217 char addr_name[16], name[18];
1218 Uint32 ea_mode;
1219
1220 ea_mode = (cur_inst>>8) & BITMASK(6);
1221 dsp_calc_ea(ea_mode, addr_name);
1222
1223 if (cur_inst & (1<<6)) {
1224 sprintf(name, "y:%s", addr_name);
1225 } else {
1226 sprintf(name, "x:%s", addr_name);
1227 }
1228
1229 fprintf(stderr,"Dsp: 0x%04x: do %s,p:0x%04x\n",
1230 dsp_core->pc,
1231 name,
1232 read_memory(dsp_core->pc+1)
1233 );
1234 }
1235
dsp_do_c(void)1236 static void dsp_do_c(void)
1237 {
1238 fprintf(stderr,"Dsp: 0x%04x: do %s,p:0x%04x\n",
1239 dsp_core->pc,
1240 registers_name[(cur_inst>>8) & BITMASK(6)],
1241 read_memory(dsp_core->pc+1)
1242 );
1243 }
1244
dsp_enddo(void)1245 static void dsp_enddo(void)
1246 {
1247 fprintf(stderr,"Dsp: 0x%04x: enddo\n",dsp_core->pc);
1248 }
1249
dsp_illegal(void)1250 static void dsp_illegal(void)
1251 {
1252 fprintf(stderr,"Dsp: 0x%04x: illegal\n",dsp_core->pc);
1253 }
1254
dsp_jcc(void)1255 static void dsp_jcc(void)
1256 {
1257 char cond_name[18], addr_name[16];
1258 Uint32 cc_code=0;
1259
1260 switch((cur_inst >> 16) & BITMASK(8)) {
1261 case 0x0a:
1262 dsp_calc_ea((cur_inst >>8) & BITMASK(6), addr_name);
1263 cc_code=cur_inst & BITMASK(4);
1264 break;
1265 case 0x0e:
1266 sprintf(addr_name, "0x%04x", cur_inst & BITMASK(12));
1267 cc_code=(cur_inst>>12) & BITMASK(4);
1268 break;
1269 }
1270 dsp_calc_cc(cc_code, cond_name);
1271
1272 fprintf(stderr,"Dsp: 0x%04x: j%s p:%s\n",dsp_core->pc, cond_name, addr_name);
1273 }
1274
dsp_jclr(void)1275 static void dsp_jclr(void)
1276 {
1277 char srcname[18], addr_name[16];
1278 Uint32 memspace, value, numbit;
1279
1280 memspace = (cur_inst>>6) & 1;
1281 value = (cur_inst>>8) & BITMASK(6);
1282 numbit = cur_inst & BITMASK(5);
1283
1284 switch((cur_inst>>14) & BITMASK(2)) {
1285 case 0:
1286 /* jclr #n,x:aa,p:xx */
1287 /* jclr #n,y:aa,p:xx */
1288 if (memspace) {
1289 sprintf(srcname, "y:0x%04x", value);
1290 } else {
1291 sprintf(srcname, "x:0x%04x", value);
1292 }
1293 break;
1294 case 1:
1295 /* jclr #n,x:ea,p:xx */
1296 /* jclr #n,y:ea,p:xx */
1297 dsp_calc_ea(value, addr_name);
1298 if (memspace) {
1299 sprintf(srcname, "y:%s", addr_name);
1300 } else {
1301 sprintf(srcname, "x:%s", addr_name);
1302 }
1303 break;
1304 case 2:
1305 /* jclr #n,x:pp,p:xx */
1306 /* jclr #n,y:pp,p:xx */
1307 value += 0xffc0;
1308 if (memspace) {
1309 sprintf(srcname, "y:0x%04x", value);
1310 } else {
1311 sprintf(srcname, "x:0x%04x", value);
1312 }
1313 break;
1314 case 3:
1315 /* jclr #n,R,p:xx */
1316 strcpy(srcname, registers_name[value]);
1317 break;
1318 }
1319
1320 fprintf(stderr,"Dsp: 0x%04x: jclr #%d,%s,p:0x%04x\n",
1321 dsp_core->pc,
1322 numbit,
1323 srcname,
1324 read_memory(dsp_core->pc+1)
1325 );
1326 }
1327
dsp_jmp(void)1328 static void dsp_jmp(void)
1329 {
1330 char dstname[16];
1331
1332 switch((cur_inst >> 16) & BITMASK(8)) {
1333 case 0x0a:
1334 dsp_calc_ea((cur_inst >>8) & BITMASK(6), dstname);
1335 break;
1336 case 0x0c:
1337 sprintf(dstname, "0x%04x", cur_inst & BITMASK(12));
1338 break;
1339 }
1340
1341 fprintf(stderr,"Dsp: 0x%04x: jmp p:%s\n",dsp_core->pc, dstname);
1342 }
1343
dsp_jscc(void)1344 static void dsp_jscc(void)
1345 {
1346 char cond_name[16], addr_name[16];
1347 Uint32 cc_code=0;
1348
1349 switch((cur_inst >> 16) & BITMASK(8)) {
1350 case 0x0b:
1351 dsp_calc_ea((cur_inst >>8) & BITMASK(6), addr_name);
1352 cc_code=cur_inst & BITMASK(4);
1353 break;
1354 case 0x0f:
1355 sprintf(addr_name, "0x%04x", cur_inst & BITMASK(12));
1356 cc_code=(cur_inst>>12) & BITMASK(4);
1357 break;
1358 }
1359 dsp_calc_cc(cc_code, cond_name);
1360
1361 fprintf(stderr,"Dsp: 0x%04x: js%s p:%s\n",dsp_core->pc, cond_name, addr_name);
1362 }
1363
dsp_jsclr(void)1364 static void dsp_jsclr(void)
1365 {
1366 char srcname[18], addr_name[16];
1367 Uint32 memspace, value, numbit;
1368
1369 memspace = (cur_inst>>6) & 1;
1370 value = (cur_inst>>8) & BITMASK(6);
1371 numbit = cur_inst & BITMASK(5);
1372
1373 switch((cur_inst>>14) & BITMASK(2)) {
1374 case 0:
1375 /* jsclr #n,x:aa,p:xx */
1376 /* jsclr #n,y:aa,p:xx */
1377 if (memspace) {
1378 sprintf(srcname, "y:0x%04x", value);
1379 } else {
1380 sprintf(srcname, "x:0x%04x", value);
1381 }
1382 break;
1383 case 1:
1384 /* jsclr #n,x:ea,p:xx */
1385 /* jsclr #n,y:ea,p:xx */
1386 dsp_calc_ea(value, addr_name);
1387 if (memspace) {
1388 sprintf(srcname, "y:%s", addr_name);
1389 } else {
1390 sprintf(srcname, "x:%s", addr_name);
1391 }
1392 break;
1393 case 2:
1394 /* jsclr #n,x:pp,p:xx */
1395 /* jsclr #n,y:pp,p:xx */
1396 value += 0xffc0;
1397 if (memspace) {
1398 sprintf(srcname, "y:0x%04x", value);
1399 } else {
1400 sprintf(srcname, "x:0x%04x", value);
1401 }
1402 break;
1403 case 3:
1404 /* jsclr #n,R,p:xx */
1405 strcpy(srcname, registers_name[value]);
1406 break;
1407 }
1408
1409 fprintf(stderr,"Dsp: 0x%04x: jsclr #%d,%s,p:0x%04x\n",
1410 dsp_core->pc,
1411 numbit,
1412 srcname,
1413 read_memory(dsp_core->pc+1)
1414 );
1415 }
1416
dsp_jset(void)1417 static void dsp_jset(void)
1418 {
1419 char srcname[18], addr_name[16];
1420 Uint32 memspace, value, numbit;
1421
1422 memspace = (cur_inst>>6) & 1;
1423 value = (cur_inst>>8) & BITMASK(6);
1424 numbit = cur_inst & BITMASK(5);
1425
1426 switch((cur_inst>>14) & BITMASK(2)) {
1427 case 0:
1428 /* jset #n,x:aa,p:xx */
1429 /* jset #n,y:aa,p:xx */
1430 if (memspace) {
1431 sprintf(srcname, "y:0x%04x", value);
1432 } else {
1433 sprintf(srcname, "x:0x%04x", value);
1434 }
1435 break;
1436 case 1:
1437 /* jset #n,x:ea,p:xx */
1438 /* jset #n,y:ea,p:xx */
1439 dsp_calc_ea(value, addr_name);
1440 if (memspace) {
1441 sprintf(srcname, "y:%s", addr_name);
1442 } else {
1443 sprintf(srcname, "x:%s", addr_name);
1444 }
1445 break;
1446 case 2:
1447 /* jset #n,x:pp,p:xx */
1448 /* jset #n,y:pp,p:xx */
1449 value += 0xffc0;
1450 if (memspace) {
1451 sprintf(srcname, "y:0x%04x", value);
1452 } else {
1453 sprintf(srcname, "x:0x%04x", value);
1454 }
1455 break;
1456 case 3:
1457 /* jset #n,R,p:xx */
1458 strcpy(srcname, registers_name[value]);
1459 break;
1460 }
1461
1462 fprintf(stderr,"Dsp: 0x%04x: jset #%d,%s,p:0x%04x\n",
1463 dsp_core->pc,
1464 numbit,
1465 srcname,
1466 read_memory(dsp_core->pc+1)
1467 );
1468 }
1469
dsp_jsr(void)1470 static void dsp_jsr(void)
1471 {
1472 char dstname[16];
1473
1474 if (((cur_inst>>12) & BITMASK(4))==0) {
1475 sprintf(dstname, "0x%04x", cur_inst & BITMASK(12));
1476 } else {
1477 dsp_calc_ea((cur_inst>>8) & BITMASK(6),dstname);
1478 }
1479
1480 fprintf(stderr,"Dsp: 0x%04x: jsr p:%s\n",dsp_core->pc, dstname);
1481 }
1482
dsp_jsset(void)1483 static void dsp_jsset(void)
1484 {
1485 char srcname[18], addr_name[16];
1486 Uint32 memspace, value, numbit;
1487
1488 memspace = (cur_inst>>6) & 1;
1489 value = (cur_inst>>8) & BITMASK(6);
1490 numbit = cur_inst & BITMASK(5);
1491
1492 switch((cur_inst>>14) & BITMASK(2)) {
1493 case 0:
1494 /* jsset #n,x:aa,p:xx */
1495 /* jsset #n,y:aa,p:xx */
1496 if (memspace) {
1497 sprintf(srcname, "y:0x%04x", value);
1498 } else {
1499 sprintf(srcname, "x:0x%04x", value);
1500 }
1501 break;
1502 case 1:
1503 /* jsset #n,x:ea,p:xx */
1504 /* jsset #n,y:ea,p:xx */
1505 dsp_calc_ea(value, addr_name);
1506 if (memspace) {
1507 sprintf(srcname, "y:%s", addr_name);
1508 } else {
1509 sprintf(srcname, "x:%s", addr_name);
1510 }
1511 break;
1512 case 2:
1513 /* jsset #n,x:pp,p:xx */
1514 /* jsset #n,y:pp,p:xx */
1515 value += 0xffc0;
1516 if (memspace) {
1517 sprintf(srcname, "y:0x%04x", value);
1518 } else {
1519 sprintf(srcname, "x:0x%04x", value);
1520 }
1521 break;
1522 case 3:
1523 /* jsset #n,R,p:xx */
1524 strcpy(srcname, registers_name[value]);
1525 break;
1526 }
1527
1528 fprintf(stderr,"Dsp: 0x%04x: jsset #%d,%s,p:0x%04x\n",
1529 dsp_core->pc,
1530 numbit,
1531 srcname,
1532 read_memory(dsp_core->pc+1)
1533 );
1534 }
1535
dsp_lua(void)1536 static void dsp_lua(void)
1537 {
1538 char addr_name[16], numreg;
1539
1540 dsp_calc_ea((cur_inst>>8) & BITMASK(5), addr_name);
1541 numreg = cur_inst & BITMASK(3);
1542 registers_changed[DSP_REG_R0+numreg]=1;
1543
1544 fprintf(stderr,"Dsp: 0x%04x: lua %s,r%d\n",dsp_core->pc, addr_name, numreg);
1545 }
1546
dsp_movec(void)1547 static void dsp_movec(void)
1548 {
1549 Uint32 value;
1550
1551 value = (cur_inst>>13) & (1<<3);
1552 value |= (cur_inst>>12) & (1<<2);
1553 value |= (cur_inst>>6) & (1<<1);
1554 value |= (cur_inst>>5) & 1;
1555
1556 opcodes_movec[value]();
1557
1558 registers_changed[DSP_REG_SR]=1;
1559 }
1560
dsp_movec_reg(void)1561 static void dsp_movec_reg(void)
1562 {
1563 Uint32 numreg1, numreg2;
1564
1565 /* S1,D2 */
1566 /* S2,D1 */
1567
1568 numreg2 = (cur_inst>>8) & BITMASK(6);
1569 numreg1 = (cur_inst & BITMASK(5))|0x20;
1570
1571 if (cur_inst & (1<<15)) {
1572 /* Write D1 */
1573 fprintf(stderr,"Dsp: 0x%04x: movec %s,%s\n",dsp_core->pc, registers_name[numreg2], registers_name[numreg1]);
1574 registers_changed[numreg1]=1;
1575 } else {
1576 /* Read S1 */
1577 fprintf(stderr,"Dsp: 0x%04x: movec %s,%s\n",dsp_core->pc, registers_name[numreg1], registers_name[numreg2]);
1578 registers_changed[numreg2]=1;
1579 }
1580 }
1581
dsp_movec_aa(void)1582 static void dsp_movec_aa(void)
1583 {
1584 const char *spacename;
1585 char srcname[16],dstname[16];
1586 Uint32 numreg, addr;
1587
1588 /* x:aa,D1 */
1589 /* S1,x:aa */
1590 /* y:aa,D1 */
1591 /* S1,y:aa */
1592
1593 numreg = (cur_inst & BITMASK(5))|0x20;
1594 addr = (cur_inst>>8) & BITMASK(6);
1595
1596 if (cur_inst & (1<<6)) {
1597 spacename="y";
1598 } else {
1599 spacename="x";
1600 }
1601
1602 if (cur_inst & (1<<15)) {
1603 /* Write D1 */
1604 sprintf(srcname, "%s:<0x%04x", spacename, addr);
1605 strcpy(dstname, registers_name[numreg]);
1606 } else {
1607 /* Read S1 */
1608 strcpy(srcname, registers_name[numreg]);
1609 sprintf(dstname, "%s:<0x%04x", spacename, addr);
1610 }
1611
1612 fprintf(stderr,"Dsp: 0x%04x: movec %s,%s\n",dsp_core->pc, srcname, dstname);
1613 }
1614
dsp_movec_ea(void)1615 static void dsp_movec_ea(void)
1616 {
1617 Uint32 numreg;
1618
1619 /* #xx,D1 */
1620
1621 numreg = (cur_inst & BITMASK(5))|0x20;
1622
1623 registers_changed[numreg]=1;
1624 fprintf(stderr,"Dsp: 0x%04x: movec #0x%02x,%s\n",dsp_core->pc, (cur_inst>>8) & BITMASK(8), registers_name[numreg]);
1625 }
1626
dsp_movec_imm(void)1627 static void dsp_movec_imm(void)
1628 {
1629 const char *spacename;
1630 char srcname[18], dstname[18], addr_name[16];
1631 Uint32 numreg, ea_mode;
1632 int retour;
1633
1634 /* x:ea,D1 */
1635 /* S1,x:ea */
1636 /* y:ea,D1 */
1637 /* S1,y:ea */
1638 /* #xxxx,D1 */
1639
1640 numreg = (cur_inst & BITMASK(5))|0x20;
1641 ea_mode = (cur_inst>>8) & BITMASK(6);
1642 retour = dsp_calc_ea(ea_mode, addr_name);
1643
1644 if (cur_inst & (1<<6)) {
1645 spacename="y";
1646 } else {
1647 spacename="x";
1648 }
1649
1650 if (cur_inst & (1<<15)) {
1651 /* Write D1 */
1652 if (retour) {
1653 sprintf(srcname, "#%s", addr_name);
1654 } else {
1655 sprintf(srcname, "%s:%s", spacename, addr_name);
1656 }
1657 registers_changed[numreg]=1;
1658 strcpy(dstname, registers_name[numreg]);
1659 } else {
1660 /* Read S1 */
1661 strcpy(srcname, registers_name[numreg]);
1662 sprintf(dstname, "%s:%s", spacename, addr_name);
1663 }
1664
1665 fprintf(stderr,"Dsp: 0x%04x: movec %s,%s\n",dsp_core->pc, srcname, dstname);
1666 }
1667
dsp_movem(void)1668 static void dsp_movem(void)
1669 {
1670 char addr_name[16], srcname[18], dstname[18];
1671 Uint32 ea_mode, numreg;
1672
1673 if (cur_inst & (1<<14)) {
1674 /* S,p:ea */
1675 /* p:ea,D */
1676
1677 ea_mode = (cur_inst>>8) & BITMASK(6);
1678 dsp_calc_ea(ea_mode, addr_name);
1679 } else {
1680 /* S,p:aa */
1681 /* p:aa,D */
1682
1683 sprintf(addr_name, "0x%04x",(cur_inst>>8) & BITMASK(6));
1684 }
1685
1686 numreg = cur_inst & BITMASK(6);
1687 if (cur_inst & (1<<15)) {
1688 /* Write D */
1689 registers_changed[numreg]=1;
1690 sprintf(srcname, "p:%s", addr_name);
1691 strcpy(dstname, registers_name[numreg]);
1692 } else {
1693 /* Read S */
1694 strcpy(srcname, registers_name[numreg]);
1695 sprintf(dstname, "p:%s", addr_name);
1696 }
1697
1698 registers_changed[DSP_REG_SR]=1;
1699
1700 fprintf(stderr,"Dsp: 0x%04x: movem %s,%s\n",dsp_core->pc, srcname, dstname);
1701 }
1702
dsp_movep(void)1703 static void dsp_movep(void)
1704 {
1705 Uint32 value;
1706
1707 value = (cur_inst>>6) & BITMASK(2);
1708
1709 opcodes_movep[value]();
1710 registers_changed[DSP_REG_SR]=1;
1711 }
1712
dsp_movep_0(void)1713 static void dsp_movep_0(void)
1714 {
1715 char srcname[16]="",dstname[16]="";
1716 Uint32 addr, memspace, numreg;
1717
1718 /* S,x:pp */
1719 /* x:pp,D */
1720 /* S,y:pp */
1721 /* y:pp,D */
1722
1723 addr = 0xffc0 + (cur_inst & BITMASK(6));
1724 memspace = (cur_inst>>16) & 1;
1725 numreg = (cur_inst>>8) & BITMASK(6);
1726
1727 if (cur_inst & (1<<15)) {
1728 /* Write pp */
1729
1730 strcpy(srcname, registers_name[numreg]);
1731
1732 if (memspace) {
1733 sprintf(dstname, "y:0x%04x", addr);
1734 } else {
1735 sprintf(dstname, "x:0x%04x", addr);
1736 }
1737 } else {
1738 /* Read pp */
1739
1740 if (memspace) {
1741 sprintf(srcname, "y:0x%04x", addr);
1742 } else {
1743 sprintf(srcname, "x:0x%04x", addr);
1744 }
1745
1746 registers_changed[numreg]=1;
1747 strcpy(dstname, registers_name[numreg]);
1748 }
1749
1750 fprintf(stderr,"Dsp: 0x%04x: movep %s,%s\n",dsp_core->pc, srcname, dstname);
1751 }
1752
dsp_movep_1(void)1753 static void dsp_movep_1(void)
1754 {
1755 char srcname[18]="",dstname[18]="",name[16]="";
1756 Uint32 addr, memspace;
1757
1758 /* p:ea,x:pp */
1759 /* x:pp,p:ea */
1760 /* p:ea,y:pp */
1761 /* y:pp,p:ea */
1762
1763 addr = 0xffc0 + (cur_inst & BITMASK(6));
1764 dsp_calc_ea((cur_inst>>8) & BITMASK(6), name);
1765 memspace = (cur_inst>>16) & 1;
1766
1767 if (cur_inst & (1<<15)) {
1768 /* Write pp */
1769
1770 sprintf(srcname, "p:%s", name);
1771
1772 if (memspace) {
1773 sprintf(dstname, "y:0x%04x", addr);
1774 } else {
1775 sprintf(dstname, "x:0x%04x", addr);
1776 }
1777 } else {
1778 /* Read pp */
1779
1780 if (memspace) {
1781 sprintf(srcname, "y:0x%04x", addr);
1782 } else {
1783 sprintf(srcname, "x:0x%04x", addr);
1784 }
1785
1786 sprintf(dstname, "p:%s", name);
1787 }
1788
1789 fprintf(stderr,"Dsp: 0x%04x: movep %s,%s\n",dsp_core->pc, srcname, dstname);
1790 }
1791
dsp_movep_2(void)1792 static void dsp_movep_2(void)
1793 {
1794 char srcname[18]="",dstname[18]="",name[16]="";
1795 Uint32 addr, memspace, easpace, retour;
1796
1797 /* x:ea,x:pp */
1798 /* y:ea,x:pp */
1799 /* #xxxxxx,x:pp */
1800 /* x:pp,x:ea */
1801 /* x:pp,y:ea */
1802
1803 /* x:ea,y:pp */
1804 /* y:ea,y:pp */
1805 /* #xxxxxx,y:pp */
1806 /* y:pp,y:ea */
1807 /* y:pp,x:ea */
1808
1809 addr = 0xffc0 + (cur_inst & BITMASK(6));
1810 retour = dsp_calc_ea((cur_inst>>8) & BITMASK(6), name);
1811 memspace = (cur_inst>>16) & 1;
1812 easpace = (cur_inst>>6) & 1;
1813
1814 if (cur_inst & (1<<15)) {
1815 /* Write pp */
1816
1817 if (retour) {
1818 sprintf(srcname, "#%s", name);
1819 } else {
1820 if (easpace) {
1821 sprintf(srcname, "y:%s", name);
1822 } else {
1823 sprintf(srcname, "x:%s", name);
1824 }
1825 }
1826
1827 if (memspace) {
1828 sprintf(dstname, "y:0x%04x", addr);
1829 } else {
1830 sprintf(dstname, "x:0x%04x", addr);
1831 }
1832 } else {
1833 /* Read pp */
1834
1835 if (memspace) {
1836 sprintf(srcname, "y:0x%04x", addr);
1837 } else {
1838 sprintf(srcname, "x:0x%04x", addr);
1839 }
1840
1841 if (easpace) {
1842 sprintf(dstname, "y:%s", name);
1843 } else {
1844 sprintf(dstname, "x:%s", name);
1845 }
1846 }
1847
1848 fprintf(stderr,"Dsp: 0x%04x: movep %s,%s\n",dsp_core->pc, srcname, dstname);
1849 }
1850
dsp_nop(void)1851 static void dsp_nop(void)
1852 {
1853 fprintf(stderr,"Dsp: 0x%04x: nop\n",dsp_core->pc);
1854 }
1855
dsp_norm(void)1856 static void dsp_norm(void)
1857 {
1858 Uint32 srcreg, destreg;
1859
1860 srcreg = DSP_REG_R0+((cur_inst>>8) & BITMASK(3));
1861 destreg = DSP_REG_A+((cur_inst>>3) & 1);
1862
1863 registers_changed[srcreg]=1;
1864 registers_changed[destreg]=1;
1865 registers_changed[DSP_REG_SR]=1;
1866
1867 fprintf(stderr,"Dsp: 0x%04x: norm %s,%s\n",dsp_core->pc, registers_name[srcreg], registers_name[destreg]);
1868 }
1869
dsp_ori(void)1870 static void dsp_ori(void)
1871 {
1872 const char *regname;
1873
1874 switch(cur_inst & BITMASK(2)) {
1875 case 0:
1876 regname="mr";
1877 registers_changed[DSP_REG_SR]=1;
1878 break;
1879 case 1:
1880 regname="ccr";
1881 registers_changed[DSP_REG_SR]=1;
1882 break;
1883 case 2:
1884 regname="omr";
1885 registers_changed[DSP_REG_OMR]=1;
1886 break;
1887 default:
1888 regname="???";
1889 break;
1890 }
1891
1892 registers_changed[DSP_REG_SR]=1;
1893
1894 fprintf(stderr,"Dsp: 0x%04x: ori #0x%02x,%s\n",
1895 dsp_core->pc,
1896 (cur_inst>>8) & BITMASK(8),
1897 regname
1898 );
1899 }
1900
dsp_rep(void)1901 static void dsp_rep(void)
1902 {
1903 Uint32 value;
1904
1905 value = (cur_inst>>12) & (BITMASK(2)<<2);
1906 value |= (cur_inst>>6) & (1<<1);
1907 value |= (cur_inst>>5) & 1;
1908
1909 opcodes_rep[value]();
1910
1911 registers_changed[DSP_REG_LC]=1;
1912 registers_changed[DSP_REG_SR]=1;
1913 }
1914
dsp_rep_aa(void)1915 static void dsp_rep_aa(void)
1916 {
1917 char name[16];
1918
1919 /* x:aa */
1920 /* y:aa */
1921
1922 if (cur_inst & (1<<6)) {
1923 sprintf(name, "y:<0x%04x",(cur_inst>>8) & BITMASK(6));
1924 } else {
1925 sprintf(name, "x:<0x%04x",(cur_inst>>8) & BITMASK(6));
1926 }
1927
1928 fprintf(stderr,"Dsp: 0x%04x: rep %s\n",dsp_core->pc, name);
1929 }
1930
dsp_rep_imm(void)1931 static void dsp_rep_imm(void)
1932 {
1933 /* #xxx */
1934 fprintf(stderr,"Dsp: 0x%04x: rep #0x%02x\n",dsp_core->pc, (cur_inst>>8) & BITMASK(8));
1935 }
1936
dsp_rep_ea(void)1937 static void dsp_rep_ea(void)
1938 {
1939 char name[18],addr_name[16];
1940
1941 /* x:ea */
1942 /* y:ea */
1943
1944 dsp_calc_ea((cur_inst>>8) & BITMASK(6), addr_name);
1945 if (cur_inst & (1<<6)) {
1946 sprintf(name, "y:%s",addr_name);
1947 } else {
1948 sprintf(name, "x:%s",addr_name);
1949 }
1950
1951 fprintf(stderr,"Dsp: 0x%04x: rep %s\n",dsp_core->pc, name);
1952 }
1953
dsp_rep_reg(void)1954 static void dsp_rep_reg(void)
1955 {
1956 /* R */
1957
1958 fprintf(stderr,"Dsp: 0x%04x: rep %s\n",dsp_core->pc, registers_name[(cur_inst>>8) & BITMASK(6)]);
1959 }
1960
dsp_reset(void)1961 static void dsp_reset(void)
1962 {
1963 fprintf(stderr,"Dsp: 0x%04x: reset\n",dsp_core->pc);
1964 }
1965
dsp_rti(void)1966 static void dsp_rti(void)
1967 {
1968 registers_changed[DSP_REG_SR]=1;
1969 fprintf(stderr,"Dsp: 0x%04x: rti\n",dsp_core->pc);
1970 }
1971
dsp_rts(void)1972 static void dsp_rts(void)
1973 {
1974 registers_changed[DSP_REG_SR]=1;
1975 fprintf(stderr,"Dsp: 0x%04x: rts\n",dsp_core->pc);
1976 }
1977
dsp_stop(void)1978 static void dsp_stop(void)
1979 {
1980 fprintf(stderr,"Dsp: 0x%04x: stop\n",dsp_core->pc);
1981 }
1982
dsp_swi(void)1983 static void dsp_swi(void)
1984 {
1985 fprintf(stderr,"Dsp: 0x%04x: swi\n",dsp_core->pc);
1986 }
1987
dsp_tcc(void)1988 static void dsp_tcc(void)
1989 {
1990 char ccname[16];
1991 Uint32 src1reg, dst1reg, src2reg, dst2reg;
1992
1993 dsp_calc_cc((cur_inst>>12) & BITMASK(4), ccname);
1994 src1reg = registers_tcc[(cur_inst>>3) & BITMASK(4)][0];
1995 dst1reg = registers_tcc[(cur_inst>>3) & BITMASK(4)][1];
1996
1997 registers_changed[dst1reg]=1;
1998 if (cur_inst & (1<<16)) {
1999 src2reg = DSP_REG_R0+(cur_inst & BITMASK(3));
2000 dst2reg = DSP_REG_R0+((cur_inst>>8) & BITMASK(3));
2001
2002 registers_changed[dst2reg]=1;
2003 fprintf(stderr,"Dsp: 0x%04x: t%s %s,%s %s,%s\n",
2004 dsp_core->pc,
2005 ccname,
2006 registers_name[src1reg],
2007 registers_name[dst1reg],
2008 registers_name[src2reg],
2009 registers_name[dst2reg]
2010 );
2011 } else {
2012 fprintf(stderr,"Dsp: 0x%04x: t%s %s,%s\n",
2013 dsp_core->pc,
2014 ccname,
2015 registers_name[src1reg],
2016 registers_name[dst1reg]
2017 );
2018 }
2019 }
2020
dsp_wait(void)2021 static void dsp_wait(void)
2022 {
2023 fprintf(stderr,"Dsp: 0x%04x: wait\n",dsp_core->pc);
2024 }
2025
2026 /**********************************
2027 * Parallel moves
2028 **********************************/
2029
dsp_pm(void)2030 static void dsp_pm(void)
2031 {
2032 Uint32 value;
2033
2034 value = (cur_inst >> 20) & BITMASK(4);
2035
2036 opcodes_parmove[value]();
2037 }
2038
dsp_pm_0(void)2039 static void dsp_pm_0(void)
2040 {
2041 char space_name[16], addr_name[16];
2042 Uint32 memspace, numreg1, numreg2;
2043 /*
2044 0000 100d 00mm mrrr S,x:ea x0,D
2045 0000 100d 10mm mrrr S,y:ea y0,D
2046 */
2047 memspace = (cur_inst>>15) & 1;
2048 numreg1 = DSP_REG_A+((cur_inst>>16) & 1);
2049 dsp_calc_ea((cur_inst>>8) & BITMASK(6), addr_name);
2050
2051 if (memspace) {
2052 strcpy(space_name,"y");
2053 numreg2 = DSP_REG_Y0;
2054 } else {
2055 strcpy(space_name,"x");
2056 numreg2 = DSP_REG_X0;
2057 }
2058
2059 registers_changed[numreg1]=1;
2060
2061 sprintf(parallelmove_name,
2062 "%s,%s:%s %s,%s",
2063 registers_name[numreg1],
2064 space_name,
2065 addr_name,
2066 registers_name[numreg2],
2067 registers_name[numreg1]
2068 );
2069 }
2070
dsp_pm_1(void)2071 static void dsp_pm_1(void)
2072 {
2073 /*
2074 0001 ffdf w0mm mrrr x:ea,D1 S2,D2
2075 S1,x:ea S2,D2
2076 #xxxxxx,D1 S2,D2
2077 0001 deff w1mm mrrr S1,D1 y:ea,D2
2078 S1,D1 S2,y:ea
2079 S1,D1 #xxxxxx,D2
2080 */
2081
2082 char addr_name[16];
2083 Uint32 memspace, write_flag, retour, s1reg, s2reg, d1reg, d2reg;
2084
2085 memspace = (cur_inst>>14) & 1;
2086 write_flag = (cur_inst>>15) & 1;
2087 retour = dsp_calc_ea((cur_inst>>8) & BITMASK(6), addr_name);
2088
2089 if (memspace==DSP_SPACE_Y) {
2090 s2reg = d2reg = DSP_REG_Y0;
2091 switch((cur_inst>>16) & BITMASK(2)) {
2092 case 0: s2reg = d2reg = DSP_REG_Y0; break;
2093 case 1: s2reg = d2reg = DSP_REG_Y1; break;
2094 case 2: s2reg = d2reg = DSP_REG_A; break;
2095 case 3: s2reg = d2reg = DSP_REG_B; break;
2096 }
2097
2098 s1reg = DSP_REG_A+((cur_inst>>19) & 1);
2099 d1reg = DSP_REG_X0+((cur_inst>>18) & 1);
2100
2101 registers_changed[d1reg]=1;
2102
2103 if (write_flag) {
2104 /* Write D2 */
2105
2106 registers_changed[d2reg]=1;
2107
2108 if (retour) {
2109 sprintf(parallelmove_name,"%s,%s #%s,%s",
2110 registers_name[s1reg],
2111 registers_name[d1reg],
2112 addr_name,
2113 registers_name[d2reg]
2114 );
2115 } else {
2116 sprintf(parallelmove_name,"%s,%s y:%s,%s",
2117 registers_name[s1reg],
2118 registers_name[d1reg],
2119 addr_name,
2120 registers_name[d2reg]
2121 );
2122 }
2123 } else {
2124 /* Read S2 */
2125 sprintf(parallelmove_name,"%s,%s %s,y:%s",
2126 registers_name[s1reg],
2127 registers_name[d1reg],
2128 registers_name[s2reg],
2129 addr_name
2130 );
2131 }
2132
2133 } else {
2134 s1reg = d1reg = DSP_REG_X0;
2135 switch((cur_inst>>18) & BITMASK(2)) {
2136 case 0: s1reg = d1reg = DSP_REG_X0; break;
2137 case 1: s1reg = d1reg = DSP_REG_X1; break;
2138 case 2: s1reg = d1reg = DSP_REG_A; break;
2139 case 3: s1reg = d1reg = DSP_REG_B; break;
2140 }
2141
2142 s2reg = DSP_REG_A+((cur_inst>>17) & 1);
2143 d2reg = DSP_REG_Y0+((cur_inst>>16) & 1);
2144
2145 registers_changed[d2reg]=1;
2146
2147 if (write_flag) {
2148 /* Write D1 */
2149
2150 registers_changed[d1reg]=1;
2151
2152 if (retour) {
2153 sprintf(parallelmove_name,"#%s,%s %s,%s",
2154 addr_name,
2155 registers_name[d1reg],
2156 registers_name[s2reg],
2157 registers_name[d2reg]
2158 );
2159 } else {
2160 sprintf(parallelmove_name,"x:%s,%s %s,%s",
2161 addr_name,
2162 registers_name[d1reg],
2163 registers_name[s2reg],
2164 registers_name[d2reg]
2165 );
2166 }
2167 } else {
2168 /* Read S1 */
2169 sprintf(parallelmove_name,"%s,x:%s %s,%s",
2170 registers_name[s1reg],
2171 addr_name,
2172 registers_name[s2reg],
2173 registers_name[d2reg]
2174 );
2175 }
2176
2177 }
2178 }
2179
dsp_pm_2(void)2180 static void dsp_pm_2(void)
2181 {
2182 char addr_name[16];
2183 Uint32 numreg1, numreg2;
2184 /*
2185 0010 0000 0000 0000 nop
2186 0010 0000 010m mrrr R update
2187 0010 00ee eeed dddd S,D
2188 001d dddd iiii iiii #xx,D
2189 */
2190 if (((cur_inst >> 8) & 0xffff) == 0x2000) {
2191 return;
2192 }
2193
2194 if (((cur_inst >> 8) & 0xffe0) == 0x2040) {
2195 dsp_calc_ea((cur_inst>>8) & BITMASK(5), addr_name);
2196 registers_changed[DSP_REG_R0+((cur_inst>>8) & BITMASK(3))]=1;
2197 sprintf(parallelmove_name, "%s,r%d",addr_name, (cur_inst>>8) & BITMASK(3));
2198 return;
2199 }
2200
2201 if (((cur_inst >> 8) & 0xfc00) == 0x2000) {
2202 numreg1 = (cur_inst>>13) & BITMASK(5);
2203 numreg2 = (cur_inst>>8) & BITMASK(5);
2204 registers_changed[numreg2]=1;
2205 sprintf(parallelmove_name, "%s,%s", registers_name[numreg1], registers_name[numreg2]);
2206 return;
2207 }
2208
2209 numreg1 = (cur_inst>>16) & BITMASK(5);
2210 registers_changed[numreg1]=1;
2211 sprintf(parallelmove_name, "#0x%02x,%s", (cur_inst >> 8) & BITMASK(8), registers_name[numreg1]);
2212 }
2213
dsp_pm_4(void)2214 static void dsp_pm_4(void)
2215 {
2216 char addr_name[16];
2217 Uint32 value, retour, ea_mode, memspace;
2218 /*
2219 0100 l0ll w0aa aaaa l:aa,D
2220 S,l:aa
2221 0100 l0ll w1mm mrrr l:ea,D
2222 S,l:ea
2223 01dd 0ddd w0aa aaaa x:aa,D
2224 S,x:aa
2225 01dd 0ddd w1mm mrrr x:ea,D
2226 S,x:ea
2227 #xxxxxx,D
2228 01dd 1ddd w0aa aaaa y:aa,D
2229 S,y:aa
2230 01dd 1ddd w1mm mrrr y:ea,D
2231 S,y:ea
2232 #xxxxxx,D
2233 */
2234 value = (cur_inst>>16) & BITMASK(3);
2235 value |= (cur_inst>>17) & (BITMASK(2)<<3);
2236
2237 ea_mode = (cur_inst>>8) & BITMASK(6);
2238
2239 if ((value>>2)==0) {
2240 /* L: memory move */
2241 if (cur_inst & (1<<14)) {
2242 retour = dsp_calc_ea(ea_mode, addr_name);
2243 } else {
2244 sprintf(addr_name,"0x%04x", ea_mode);
2245 retour = 0;
2246 }
2247
2248 value = (cur_inst>>16) & BITMASK(2);
2249 value |= (cur_inst>>17) & (1<<2);
2250
2251 if (cur_inst & (1<<15)) {
2252 /* Write D */
2253
2254 registers_changed[disasm_registers_lmove[value][0]]=1;
2255 registers_changed[disasm_registers_lmove[value][1]]=1;
2256 if (retour) {
2257 sprintf(parallelmove_name, "#%s,%s", addr_name, registers_lmove[value]);
2258 } else {
2259 sprintf(parallelmove_name, "l:%s,%s", addr_name, registers_lmove[value]);
2260 }
2261 } else {
2262 /* Read S */
2263 sprintf(parallelmove_name, "%s,l:%s", registers_lmove[value], addr_name);
2264 }
2265
2266 return;
2267 }
2268
2269 memspace = (cur_inst>>19) & 1;
2270 if (cur_inst & (1<<14)) {
2271 retour = dsp_calc_ea(ea_mode, addr_name);
2272 } else {
2273 sprintf(addr_name,"0x%04x", ea_mode);
2274 retour = 0;
2275 }
2276
2277 if (memspace) {
2278 /* Y: */
2279
2280 if (cur_inst & (1<<15)) {
2281 /* Write D */
2282
2283 registers_changed[value]=1;
2284 if (retour) {
2285 sprintf(parallelmove_name, "#%s,%s", addr_name, registers_name[value]);
2286 } else {
2287 sprintf(parallelmove_name, "y:%s,%s", addr_name, registers_name[value]);
2288 }
2289
2290 } else {
2291 /* Read S */
2292 sprintf(parallelmove_name, "%s,y:%s", registers_name[value], addr_name);
2293 }
2294 } else {
2295 /* X: */
2296
2297 if (cur_inst & (1<<15)) {
2298 /* Write D */
2299
2300 registers_changed[value]=1;
2301
2302 if (retour) {
2303 sprintf(parallelmove_name, "#%s,%s", addr_name, registers_name[value]);
2304 } else {
2305 sprintf(parallelmove_name, "x:%s,%s", addr_name, registers_name[value]);
2306 }
2307 } else {
2308 /* Read S */
2309 sprintf(parallelmove_name, "%s,x:%s", registers_name[value], addr_name);
2310 }
2311 }
2312 }
2313
dsp_pm_8(void)2314 static void dsp_pm_8(void)
2315 {
2316 char addr1_name[16], addr2_name[16];
2317 Uint32 ea_mode1, ea_mode2, numreg1, numreg2;
2318 /*
2319 1wmm eeff WrrM MRRR x:ea,D1 y:ea,D2
2320 x:ea,D1 S2,y:ea
2321 S1,x:ea y:ea,D2
2322 S1,x:ea S2,y:ea
2323 */
2324 numreg1 = DSP_REG_X0;
2325 switch((cur_inst>>18) & BITMASK(2)) {
2326 case 0: numreg1 = DSP_REG_X0; break;
2327 case 1: numreg1 = DSP_REG_X1; break;
2328 case 2: numreg1 = DSP_REG_A; break;
2329 case 3: numreg1 = DSP_REG_B; break;
2330 }
2331
2332 numreg2 = DSP_REG_Y0;
2333 switch((cur_inst>>16) & BITMASK(2)) {
2334 case 0: numreg2 = DSP_REG_Y0; break;
2335 case 1: numreg2 = DSP_REG_Y1; break;
2336 case 2: numreg2 = DSP_REG_A; break;
2337 case 3: numreg2 = DSP_REG_B; break;
2338 }
2339
2340 ea_mode1 = (cur_inst>>8) & BITMASK(5);
2341 if ((ea_mode1>>3) == 0) {
2342 ea_mode1 |= (1<<5);
2343 }
2344 ea_mode2 = (cur_inst>>13) & BITMASK(2);
2345 ea_mode2 |= ((cur_inst>>20) & BITMASK(2))<<3;
2346 if ((ea_mode1 & (1<<2))==0) {
2347 ea_mode2 |= 1<<2;
2348 }
2349 if ((ea_mode2>>3) == 0) {
2350 ea_mode2 |= (1<<5);
2351 }
2352
2353 dsp_calc_ea(ea_mode1, addr1_name);
2354 dsp_calc_ea(ea_mode2, addr2_name);
2355
2356 if (cur_inst & (1<<15)) {
2357 registers_changed[numreg1]=1;
2358 if (cur_inst & (1<<22)) {
2359 registers_changed[numreg2]=1;
2360 sprintf(parallelmove_name, "x:%s,%s y:%s,%s",
2361 addr1_name,
2362 registers_name[numreg1],
2363 addr2_name,
2364 registers_name[numreg2]
2365 );
2366 } else {
2367 sprintf(parallelmove_name, "x:%s,%s %s,y:%s",
2368 addr1_name,
2369 registers_name[numreg1],
2370 registers_name[numreg2],
2371 addr2_name
2372 );
2373 }
2374 } else {
2375 if (cur_inst & (1<<22)) {
2376 registers_changed[numreg2]=1;
2377 sprintf(parallelmove_name, "%s,x:%s y:%s,%s",
2378 registers_name[numreg1],
2379 addr1_name,
2380 addr2_name,
2381 registers_name[numreg2]
2382 );
2383 } else {
2384 sprintf(parallelmove_name, "%s,x:%s %s,y:%s",
2385 registers_name[numreg1],
2386 addr1_name,
2387 registers_name[numreg2],
2388 addr2_name
2389 );
2390 }
2391 }
2392 }
2393
2394
2395 /**********************************
2396 * Parallel moves ALU instructions
2397 **********************************/
2398
dsp_abs(void)2399 static void dsp_abs(void)
2400 {
2401 Uint32 numreg;
2402
2403 numreg = DSP_REG_A+((cur_inst>>3) & 1);
2404
2405 registers_changed[numreg]=1;
2406 registers_changed[DSP_REG_SR]=1;
2407
2408 fprintf(stderr,"Dsp: 0x%04x: abs %s %s\n",
2409 dsp_core->pc,
2410 registers_name[numreg],
2411 parallelmove_name
2412 );
2413 }
2414
dsp_adc(void)2415 static void dsp_adc(void)
2416 {
2417 const char *srcname;
2418 Uint32 numreg;
2419
2420 if (cur_inst & (1<<4)) {
2421 srcname="y";
2422 } else {
2423 srcname="x";
2424 }
2425
2426 numreg=DSP_REG_A+((cur_inst>>3) & 1);
2427 registers_changed[numreg]=1;
2428 registers_changed[DSP_REG_SR]=1;
2429
2430 fprintf(stderr,"Dsp: 0x%04x: adc %s,%s %s\n",
2431 dsp_core->pc,
2432 srcname,
2433 registers_name[numreg],
2434 parallelmove_name
2435 );
2436 }
2437
dsp_add(void)2438 static void dsp_add(void)
2439 {
2440 const char *srcname;
2441 Uint32 srcreg, dstreg;
2442
2443 srcreg = (cur_inst>>4) & BITMASK(3);
2444 dstreg = (cur_inst>>3) & 1;
2445
2446 switch(srcreg) {
2447 case 1:
2448 srcreg = dstreg ^ 1;
2449 srcname = registers_name[DSP_REG_A+srcreg];
2450 break;
2451 case 2:
2452 srcname="x";
2453 break;
2454 case 3:
2455 srcname="y";
2456 break;
2457 case 4:
2458 srcname=registers_name[DSP_REG_X0];
2459 break;
2460 case 5:
2461 srcname=registers_name[DSP_REG_Y0];
2462 break;
2463 case 6:
2464 srcname=registers_name[DSP_REG_X1];
2465 break;
2466 case 7:
2467 srcname=registers_name[DSP_REG_Y1];
2468 break;
2469 default:
2470 srcname="???";
2471 break;
2472 }
2473
2474 registers_changed[DSP_REG_A+dstreg]=1;
2475 registers_changed[DSP_REG_SR]=1;
2476
2477 fprintf(stderr,"Dsp: 0x%04x: add %s,%s %s\n",
2478 dsp_core->pc,
2479 srcname,
2480 registers_name[DSP_REG_A+dstreg],
2481 parallelmove_name
2482 );
2483 }
2484
dsp_addl(void)2485 static void dsp_addl(void)
2486 {
2487 Uint32 numreg;
2488
2489 numreg = (cur_inst>>3) & 1;
2490
2491 registers_changed[DSP_REG_A+numreg]=1;
2492 registers_changed[DSP_REG_SR]=1;
2493
2494 fprintf(stderr,"Dsp: 0x%04x: addl %s,%s %s\n",
2495 dsp_core->pc,
2496 registers_name[DSP_REG_A+(numreg ^ 1)],
2497 registers_name[DSP_REG_A+numreg],
2498 parallelmove_name
2499 );
2500 }
2501
dsp_addr(void)2502 static void dsp_addr(void)
2503 {
2504 Uint32 numreg;
2505
2506 numreg = (cur_inst>>3) & 1;
2507
2508 registers_changed[DSP_REG_A+numreg]=1;
2509 registers_changed[DSP_REG_SR]=1;
2510
2511 fprintf(stderr,"Dsp: 0x%04x: addr %s,%s %s\n",
2512 dsp_core->pc,
2513 registers_name[DSP_REG_A+(numreg ^ 1)],
2514 registers_name[DSP_REG_A+numreg],
2515 parallelmove_name
2516 );
2517 }
2518
dsp_and(void)2519 static void dsp_and(void)
2520 {
2521 Uint32 srcreg,dstreg;
2522
2523 switch((cur_inst>>4) & BITMASK(2)) {
2524 case 1:
2525 srcreg=DSP_REG_Y0;
2526 break;
2527 case 2:
2528 srcreg=DSP_REG_X1;
2529 break;
2530 case 3:
2531 srcreg=DSP_REG_Y1;
2532 break;
2533 case 0:
2534 default:
2535 srcreg=DSP_REG_X0;
2536 }
2537 dstreg = DSP_REG_A+((cur_inst>>3) & 1);
2538
2539 registers_changed[dstreg]=1;
2540 registers_changed[DSP_REG_SR]=1;
2541
2542 fprintf(stderr,"Dsp: 0x%04x: and %s,%s %s\n",
2543 dsp_core->pc,
2544 registers_name[srcreg],
2545 registers_name[dstreg],
2546 parallelmove_name
2547 );
2548 }
2549
dsp_asl(void)2550 static void dsp_asl(void)
2551 {
2552 Uint32 numreg;
2553
2554 numreg = DSP_REG_A+((cur_inst>>3) & 1);
2555
2556 registers_changed[numreg]=1;
2557 registers_changed[DSP_REG_SR]=1;
2558
2559 fprintf(stderr,"Dsp: 0x%04x: asl %s %s\n",
2560 dsp_core->pc,
2561 registers_name[numreg],
2562 parallelmove_name
2563 );
2564 }
2565
dsp_asr(void)2566 static void dsp_asr(void)
2567 {
2568 Uint32 numreg;
2569
2570 numreg = DSP_REG_A+((cur_inst>>3) & 1);
2571
2572 registers_changed[numreg]=1;
2573 registers_changed[DSP_REG_SR]=1;
2574
2575 fprintf(stderr,"Dsp: 0x%04x: asr %s %s\n",
2576 dsp_core->pc,
2577 registers_name[numreg],
2578 parallelmove_name
2579 );
2580 }
2581
dsp_clr(void)2582 static void dsp_clr(void)
2583 {
2584 Uint32 numreg;
2585
2586 numreg = DSP_REG_A+((cur_inst>>3) & 1);
2587
2588 registers_changed[numreg]=1;
2589 registers_changed[DSP_REG_SR]=1;
2590
2591 fprintf(stderr,"Dsp: 0x%04x: clr %s %s\n",
2592 dsp_core->pc,
2593 registers_name[numreg],
2594 parallelmove_name
2595 );
2596 }
2597
dsp_cmp(void)2598 static void dsp_cmp(void)
2599 {
2600 Uint32 srcreg, dstreg;
2601
2602 srcreg = (cur_inst>>4) & BITMASK(3);
2603 dstreg = (cur_inst>>3) & 1;
2604
2605 switch(srcreg) {
2606 case 0:
2607 srcreg = DSP_REG_A+(dstreg ^ 1);
2608 break;
2609 case 4:
2610 srcreg = DSP_REG_X0;
2611 break;
2612 case 5:
2613 srcreg = DSP_REG_Y0;
2614 break;
2615 case 6:
2616 srcreg = DSP_REG_X1;
2617 break;
2618 case 7:
2619 srcreg = DSP_REG_Y1;
2620 break;
2621 }
2622
2623 registers_changed[DSP_REG_SR]=1;
2624
2625 fprintf(stderr,"Dsp: 0x%04x: cmp %s,%s %s\n",
2626 dsp_core->pc,
2627 registers_name[srcreg],
2628 registers_name[DSP_REG_A+dstreg],
2629 parallelmove_name
2630 );
2631 }
2632
dsp_cmpm(void)2633 static void dsp_cmpm(void)
2634 {
2635 Uint32 srcreg, dstreg;
2636
2637 srcreg = (cur_inst>>4) & BITMASK(3);
2638 dstreg = (cur_inst>>3) & 1;
2639
2640 switch(srcreg) {
2641 case 0:
2642 srcreg = DSP_REG_A+(dstreg ^ 1);
2643 break;
2644 case 4:
2645 srcreg = DSP_REG_X0;
2646 break;
2647 case 5:
2648 srcreg = DSP_REG_Y0;
2649 break;
2650 case 6:
2651 srcreg = DSP_REG_X1;
2652 break;
2653 case 7:
2654 srcreg = DSP_REG_Y1;
2655 break;
2656 }
2657
2658 registers_changed[DSP_REG_SR]=1;
2659
2660 fprintf(stderr,"Dsp: 0x%04x: cmpm %s,%s %s\n",
2661 dsp_core->pc,
2662 registers_name[srcreg],
2663 registers_name[DSP_REG_A+dstreg],
2664 parallelmove_name
2665 );
2666 }
2667
dsp_eor(void)2668 static void dsp_eor(void)
2669 {
2670 Uint32 srcreg, dstreg;
2671
2672 switch((cur_inst>>4) & BITMASK(2)) {
2673 case 1:
2674 srcreg=DSP_REG_Y0;
2675 break;
2676 case 2:
2677 srcreg=DSP_REG_X1;
2678 break;
2679 case 3:
2680 srcreg=DSP_REG_Y1;
2681 break;
2682 case 0:
2683 default:
2684 srcreg=DSP_REG_X0;
2685 }
2686 dstreg = DSP_REG_A+((cur_inst>>3) & 1);
2687
2688 registers_changed[dstreg]=1;
2689 registers_changed[DSP_REG_SR]=1;
2690
2691 fprintf(stderr,"Dsp: 0x%04x: eor %s,%s %s\n",
2692 dsp_core->pc,
2693 registers_name[srcreg],
2694 registers_name[dstreg],
2695 parallelmove_name
2696 );
2697 }
2698
dsp_lsl(void)2699 static void dsp_lsl(void)
2700 {
2701 Uint32 numreg;
2702
2703 numreg = DSP_REG_A+((cur_inst>>3) & 1);
2704
2705 registers_changed[numreg]=1;
2706 registers_changed[DSP_REG_SR]=1;
2707
2708 fprintf(stderr,"Dsp: 0x%04x: lsl %s %s\n",
2709 dsp_core->pc,
2710 registers_name[numreg],
2711 parallelmove_name
2712 );
2713 }
2714
dsp_lsr(void)2715 static void dsp_lsr(void)
2716 {
2717 Uint32 numreg;
2718
2719 numreg = DSP_REG_A+((cur_inst>>3) & 1);
2720
2721 registers_changed[numreg]=1;
2722 registers_changed[DSP_REG_SR]=1;
2723
2724 fprintf(stderr,"Dsp: 0x%04x: lsr %s %s\n",
2725 dsp_core->pc,
2726 registers_name[numreg],
2727 parallelmove_name
2728 );
2729 }
2730
dsp_mac(void)2731 static void dsp_mac(void)
2732 {
2733 const char *sign_name;
2734 Uint32 src1reg=DSP_REG_NULL, src2reg=DSP_REG_NULL, dstreg;
2735
2736 if (cur_inst & (1<<2)) {
2737 sign_name="-";
2738 } else {
2739 sign_name="";
2740 }
2741
2742 switch((cur_inst>>4) & BITMASK(3)) {
2743 case 0:
2744 src1reg = DSP_REG_X0;
2745 src2reg = DSP_REG_X0;
2746 break;
2747 case 1:
2748 src1reg = DSP_REG_Y0;
2749 src2reg = DSP_REG_Y0;
2750 break;
2751 case 2:
2752 src1reg = DSP_REG_X1;
2753 src2reg = DSP_REG_X0;
2754 break;
2755 case 3:
2756 src1reg = DSP_REG_Y1;
2757 src2reg = DSP_REG_Y0;
2758 break;
2759 case 4:
2760 src1reg = DSP_REG_X0;
2761 src2reg = DSP_REG_Y1;
2762 break;
2763 case 5:
2764 src1reg = DSP_REG_Y0;
2765 src2reg = DSP_REG_X0;
2766 break;
2767 case 6:
2768 src1reg = DSP_REG_X1;
2769 src2reg = DSP_REG_Y0;
2770 break;
2771 case 7:
2772 src1reg = DSP_REG_Y1;
2773 src2reg = DSP_REG_X1;
2774 break;
2775 }
2776 dstreg = (cur_inst>>3) & 1;
2777
2778 registers_changed[DSP_REG_A+dstreg]=1;
2779 registers_changed[DSP_REG_SR]=1;
2780
2781 fprintf(stderr,"Dsp: 0x%04x: mac %s%s,%s,%s %s\n",
2782 dsp_core->pc,
2783 sign_name,
2784 registers_name[src1reg],
2785 registers_name[src2reg],
2786 registers_name[DSP_REG_A+dstreg],
2787 parallelmove_name
2788 );
2789 }
2790
dsp_macr(void)2791 static void dsp_macr(void)
2792 {
2793 const char *sign_name;
2794 Uint32 src1reg=DSP_REG_NULL, src2reg=DSP_REG_NULL, dstreg;
2795
2796 if (cur_inst & (1<<2)) {
2797 sign_name="-";
2798 } else {
2799 sign_name="";
2800 }
2801
2802 switch((cur_inst>>4) & BITMASK(3)) {
2803 case 0:
2804 src1reg = DSP_REG_X0;
2805 src2reg = DSP_REG_X0;
2806 break;
2807 case 1:
2808 src1reg = DSP_REG_Y0;
2809 src2reg = DSP_REG_Y0;
2810 break;
2811 case 2:
2812 src1reg = DSP_REG_X1;
2813 src2reg = DSP_REG_X0;
2814 break;
2815 case 3:
2816 src1reg = DSP_REG_Y1;
2817 src2reg = DSP_REG_Y0;
2818 break;
2819 case 4:
2820 src1reg = DSP_REG_X0;
2821 src2reg = DSP_REG_Y1;
2822 break;
2823 case 5:
2824 src1reg = DSP_REG_Y0;
2825 src2reg = DSP_REG_X0;
2826 break;
2827 case 6:
2828 src1reg = DSP_REG_X1;
2829 src2reg = DSP_REG_Y0;
2830 break;
2831 case 7:
2832 src1reg = DSP_REG_Y1;
2833 src2reg = DSP_REG_X1;
2834 break;
2835 }
2836 dstreg = (cur_inst>>3) & 1;
2837
2838 registers_changed[DSP_REG_A+dstreg]=1;
2839 registers_changed[DSP_REG_SR]=1;
2840
2841 fprintf(stderr,"Dsp: 0x%04x: macr %s%s,%s,%s %s\n",
2842 dsp_core->pc,
2843 sign_name,
2844 registers_name[src1reg],
2845 registers_name[src2reg],
2846 registers_name[DSP_REG_A+dstreg],
2847 parallelmove_name
2848 );
2849 }
2850
dsp_move(void)2851 static void dsp_move(void)
2852 {
2853 fprintf(stderr,"Dsp: 0x%04x: move %s\n",dsp_core->pc, parallelmove_name);
2854 }
2855
dsp_move_nopm(void)2856 static void dsp_move_nopm(void)
2857 {
2858 dsp_pm();
2859 fprintf(stderr,"Dsp: 0x%04x: move %s\n",dsp_core->pc, parallelmove_name);
2860 }
2861
dsp_mpy(void)2862 static void dsp_mpy(void)
2863 {
2864 const char *sign_name;
2865 Uint32 src1reg=DSP_REG_NULL, src2reg=DSP_REG_NULL, dstreg;
2866
2867 if (cur_inst & (1<<2)) {
2868 sign_name="-";
2869 } else {
2870 sign_name="";
2871 }
2872
2873 switch((cur_inst>>4) & BITMASK(3)) {
2874 case 0:
2875 src1reg = DSP_REG_X0;
2876 src2reg = DSP_REG_X0;
2877 break;
2878 case 1:
2879 src1reg = DSP_REG_Y0;
2880 src2reg = DSP_REG_Y0;
2881 break;
2882 case 2:
2883 src1reg = DSP_REG_X1;
2884 src2reg = DSP_REG_X0;
2885 break;
2886 case 3:
2887 src1reg = DSP_REG_Y1;
2888 src2reg = DSP_REG_Y0;
2889 break;
2890 case 4:
2891 src1reg = DSP_REG_X0;
2892 src2reg = DSP_REG_Y1;
2893 break;
2894 case 5:
2895 src1reg = DSP_REG_Y0;
2896 src2reg = DSP_REG_X0;
2897 break;
2898 case 6:
2899 src1reg = DSP_REG_X1;
2900 src2reg = DSP_REG_Y0;
2901 break;
2902 case 7:
2903 src1reg = DSP_REG_Y1;
2904 src2reg = DSP_REG_X1;
2905 break;
2906 }
2907 dstreg = (cur_inst>>3) & 1;
2908
2909 registers_changed[DSP_REG_A+dstreg]=1;
2910 registers_changed[DSP_REG_SR]=1;
2911
2912 fprintf(stderr,"Dsp: 0x%04x: mpy %s%s,%s,%s %s\n",
2913 dsp_core->pc,
2914 sign_name,
2915 registers_name[src1reg],
2916 registers_name[src2reg],
2917 registers_name[DSP_REG_A+dstreg],
2918 parallelmove_name
2919 );
2920 }
2921
dsp_mpyr(void)2922 static void dsp_mpyr(void)
2923 {
2924 const char *sign_name;
2925 Uint32 src1reg=DSP_REG_NULL, src2reg=DSP_REG_NULL, dstreg;
2926
2927 if (cur_inst & (1<<2)) {
2928 sign_name="-";
2929 } else {
2930 sign_name="";
2931 }
2932
2933 switch((cur_inst>>4) & BITMASK(3)) {
2934 case 0:
2935 src1reg = DSP_REG_X0;
2936 src2reg = DSP_REG_X0;
2937 break;
2938 case 1:
2939 src1reg = DSP_REG_Y0;
2940 src2reg = DSP_REG_Y0;
2941 break;
2942 case 2:
2943 src1reg = DSP_REG_X1;
2944 src2reg = DSP_REG_X0;
2945 break;
2946 case 3:
2947 src1reg = DSP_REG_Y1;
2948 src2reg = DSP_REG_Y0;
2949 break;
2950 case 4:
2951 src1reg = DSP_REG_X0;
2952 src2reg = DSP_REG_Y1;
2953 break;
2954 case 5:
2955 src1reg = DSP_REG_Y0;
2956 src2reg = DSP_REG_X0;
2957 break;
2958 case 6:
2959 src1reg = DSP_REG_X1;
2960 src2reg = DSP_REG_Y0;
2961 break;
2962 case 7:
2963 src1reg = DSP_REG_Y1;
2964 src2reg = DSP_REG_X1;
2965 break;
2966 }
2967 dstreg = (cur_inst>>3) & 1;
2968
2969 registers_changed[DSP_REG_A+dstreg]=1;
2970 registers_changed[DSP_REG_SR]=1;
2971
2972 fprintf(stderr,"Dsp: 0x%04x: mpyr %s%s,%s,%s %s\n",
2973 dsp_core->pc,
2974 sign_name,
2975 registers_name[src1reg],
2976 registers_name[src2reg],
2977 registers_name[DSP_REG_A+dstreg],
2978 parallelmove_name
2979 );
2980 }
2981
dsp_neg(void)2982 static void dsp_neg(void)
2983 {
2984 Uint32 numreg;
2985
2986 numreg = DSP_REG_A+((cur_inst>>3) & 1);
2987
2988 registers_changed[numreg]=1;
2989 registers_changed[DSP_REG_SR]=1;
2990
2991 fprintf(stderr,"Dsp: 0x%04x: neg %s %s\n",
2992 dsp_core->pc,
2993 registers_name[numreg],
2994 parallelmove_name
2995 );
2996 }
2997
dsp_not(void)2998 static void dsp_not(void)
2999 {
3000 Uint32 numreg;
3001
3002 numreg = DSP_REG_A+((cur_inst>>3) & 1);
3003
3004 registers_changed[numreg]=1;
3005 registers_changed[DSP_REG_SR]=1;
3006
3007 fprintf(stderr,"Dsp: 0x%04x: not %s %s\n",
3008 dsp_core->pc,
3009 registers_name[numreg],
3010 parallelmove_name
3011 );
3012 }
3013
dsp_or(void)3014 static void dsp_or(void)
3015 {
3016 Uint32 srcreg, dstreg;
3017
3018 switch((cur_inst>>4) & BITMASK(2)) {
3019 case 1:
3020 srcreg=DSP_REG_Y0;
3021 break;
3022 case 2:
3023 srcreg=DSP_REG_X1;
3024 break;
3025 case 3:
3026 srcreg=DSP_REG_Y1;
3027 break;
3028 case 0:
3029 default:
3030 srcreg=DSP_REG_X0;
3031 }
3032 dstreg = DSP_REG_A+((cur_inst>>3) & 1);
3033
3034 registers_changed[dstreg]=1;
3035 registers_changed[DSP_REG_SR]=1;
3036
3037 fprintf(stderr,"Dsp: 0x%04x: or %s,%s %s\n",
3038 dsp_core->pc,
3039 registers_name[srcreg],
3040 registers_name[dstreg],
3041 parallelmove_name
3042 );
3043 }
3044
dsp_rnd(void)3045 static void dsp_rnd(void)
3046 {
3047 Uint32 numreg;
3048
3049 numreg = DSP_REG_A+((cur_inst>>3) & 1);
3050
3051 registers_changed[numreg]=1;
3052 registers_changed[DSP_REG_SR]=1;
3053
3054 fprintf(stderr,"Dsp: 0x%04x: rnd %s %s\n",
3055 dsp_core->pc,
3056 registers_name[numreg],
3057 parallelmove_name
3058 );
3059 }
3060
dsp_rol(void)3061 static void dsp_rol(void)
3062 {
3063 Uint32 numreg;
3064
3065 numreg = DSP_REG_A+((cur_inst>>3) & 1);
3066
3067 registers_changed[numreg]=1;
3068 registers_changed[DSP_REG_SR]=1;
3069
3070 fprintf(stderr,"Dsp: 0x%04x: rol %s %s\n",
3071 dsp_core->pc,
3072 registers_name[numreg],
3073 parallelmove_name
3074 );
3075 }
3076
dsp_ror(void)3077 static void dsp_ror(void)
3078 {
3079 Uint32 numreg;
3080
3081 numreg = DSP_REG_A+((cur_inst>>3) & 1);
3082
3083 registers_changed[numreg]=1;
3084 registers_changed[DSP_REG_SR]=1;
3085
3086 fprintf(stderr,"Dsp: 0x%04x: ror %s %s\n",
3087 dsp_core->pc,
3088 registers_name[numreg],
3089 parallelmove_name
3090 );
3091 }
3092
dsp_sbc(void)3093 static void dsp_sbc(void)
3094 {
3095 const char *srcname;
3096 Uint32 numreg;
3097
3098 if (cur_inst & (1<<4)) {
3099 srcname="y";
3100 } else {
3101 srcname="x";
3102 }
3103
3104 numreg = DSP_REG_A+((cur_inst>>3) & 1);
3105
3106 registers_changed[numreg]=1;
3107 registers_changed[DSP_REG_SR]=1;
3108
3109 fprintf(stderr,"Dsp: 0x%04x: sbc %s,%s %s\n",
3110 dsp_core->pc,
3111 srcname,
3112 registers_name[numreg],
3113 parallelmove_name
3114 );
3115 }
3116
dsp_sub(void)3117 static void dsp_sub(void)
3118 {
3119 const char *srcname;
3120 Uint32 srcreg, dstreg;
3121
3122 srcreg = (cur_inst>>4) & BITMASK(3);
3123 dstreg = (cur_inst>>3) & 1;
3124
3125 switch(srcreg) {
3126 case 1:
3127 srcreg = dstreg ^ 1;
3128 srcname = registers_name[DSP_REG_A+srcreg];
3129 break;
3130 case 2:
3131 srcname="x";
3132 break;
3133 case 3:
3134 srcname="y";
3135 break;
3136 case 4:
3137 srcname=registers_name[DSP_REG_X0];
3138 break;
3139 case 5:
3140 srcname=registers_name[DSP_REG_Y0];
3141 break;
3142 case 6:
3143 srcname=registers_name[DSP_REG_X1];
3144 break;
3145 case 7:
3146 srcname=registers_name[DSP_REG_Y1];
3147 break;
3148 default:
3149 srcname="???";
3150 break;
3151 }
3152
3153 registers_changed[DSP_REG_A+dstreg]=1;
3154 registers_changed[DSP_REG_SR]=1;
3155
3156 fprintf(stderr,"Dsp: 0x%04x: sub %s,%s %s\n",
3157 dsp_core->pc,
3158 srcname,
3159 registers_name[DSP_REG_A+dstreg],
3160 parallelmove_name
3161 );
3162 }
3163
dsp_subl(void)3164 static void dsp_subl(void)
3165 {
3166 Uint32 numreg;
3167
3168 numreg = (cur_inst>>3) & 1;
3169
3170 registers_changed[DSP_REG_A+numreg]=1;
3171 registers_changed[DSP_REG_SR]=1;
3172
3173 fprintf(stderr,"Dsp: 0x%04x: subl %s,%s %s\n",
3174 dsp_core->pc,
3175 registers_name[DSP_REG_A+(numreg ^ 1)],
3176 registers_name[DSP_REG_A+numreg],
3177 parallelmove_name
3178 );
3179 }
3180
dsp_subr(void)3181 static void dsp_subr(void)
3182 {
3183 Uint32 numreg;
3184
3185 numreg = (cur_inst>>3) & 1;
3186
3187 registers_changed[DSP_REG_A+numreg]=1;
3188 registers_changed[DSP_REG_SR]=1;
3189
3190 fprintf(stderr,"Dsp: 0x%04x: subr %s,%s %s\n",
3191 dsp_core->pc,
3192 registers_name[DSP_REG_A+(numreg ^ 1)],
3193 registers_name[DSP_REG_A+numreg],
3194 parallelmove_name
3195 );
3196 }
3197
dsp_tfr(void)3198 static void dsp_tfr(void)
3199 {
3200 Uint32 srcreg, dstreg;
3201
3202 srcreg = (cur_inst>>4) & BITMASK(3);
3203 dstreg = (cur_inst>>3) & 1;
3204
3205 switch(srcreg) {
3206 case 4:
3207 srcreg = DSP_REG_X0;
3208 break;
3209 case 5:
3210 srcreg = DSP_REG_Y0;
3211 break;
3212 case 6:
3213 srcreg = DSP_REG_X1;
3214 break;
3215 case 7:
3216 srcreg = DSP_REG_Y1;
3217 break;
3218 case 0:
3219 default:
3220 srcreg = DSP_REG_A+(dstreg ^ 1);
3221 break;
3222 }
3223
3224 registers_changed[DSP_REG_A+dstreg]=1;
3225 registers_changed[DSP_REG_SR]=1;
3226
3227 fprintf(stderr,"Dsp: 0x%04x: tfr %s,%s %s\n",
3228 dsp_core->pc,
3229 registers_name[srcreg],
3230 registers_name[DSP_REG_A+dstreg],
3231 parallelmove_name
3232 );
3233 }
3234
dsp_tst(void)3235 static void dsp_tst(void)
3236 {
3237 registers_changed[DSP_REG_SR]=1;
3238
3239 fprintf(stderr,"Dsp: 0x%04x: tst %s %s\n",
3240 dsp_core->pc,
3241 registers_name[DSP_REG_A+((cur_inst>>3) & 1)],
3242 parallelmove_name
3243 );
3244 }
3245