1 /////////////////////////////////////////////////////////////////////////
2 // $Id: apic.h 14086 2021-01-30 08:35:35Z sshwarts $
3 /////////////////////////////////////////////////////////////////////////
4 //
5 // Copyright (c) 2002-2017 Zwane Mwaikambo, Stanislav Shwartsman
6 //
7 // This library is free software; you can redistribute it and/or
8 // modify it under the terms of the GNU Lesser General Public
9 // License as published by the Free Software Foundation; either
10 // version 2 of the License, or (at your option) any later version.
11 //
12 // This library is distributed in the hope that it will be useful,
13 // but WITHOUT ANY WARRANTY; without even the implied warranty of
14 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 // Lesser General Public License for more details.
16 //
17 // You should have received a copy of the GNU Lesser General Public
18 // License along with this library; if not, write to the Free Software
19 // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 //
21 /////////////////////////////////////////////////////////////////////////
22
23 #ifndef BX_CPU_APIC_H
24 #define BX_CPU_APIC_H 1
25
26 #if BX_SUPPORT_APIC
27
28 enum {
29 APIC_EDGE_TRIGGERED = 0,
30 APIC_LEVEL_TRIGGERED = 1
31 };
32
33 const bx_phy_address BX_LAPIC_BASE_ADDR = 0xfee00000; // default Local APIC address
34
35 #define BX_NUM_LOCAL_APICS BX_SMP_PROCESSORS
36
37 enum {
38 BX_APIC_GLOBALLY_DISABLED = 0,
39 BX_APIC_STATE_INVALID = 1,
40 BX_APIC_XAPIC_MODE = 2,
41 BX_APIC_X2APIC_MODE = 3
42 };
43
44 #define BX_XAPIC_EXT_SUPPORT_IER (1 << 0)
45 #define BX_XAPIC_EXT_SUPPORT_SEOI (1 << 1)
46
47 typedef Bit32u apic_dest_t; /* same definition in ioapic.h */
48
49 // local apic registers
50
51 #define BX_LAPIC_ID 0x020
52 #define BX_LAPIC_VERSION 0x030
53 #define BX_LAPIC_TPR 0x080
54 #define BX_LAPIC_ARBITRATION_PRIORITY 0x090
55 #define BX_LAPIC_PPR 0x0A0
56 #define BX_LAPIC_EOI 0x0B0
57 #define BX_LAPIC_RRD 0x0C0
58 #define BX_LAPIC_LDR 0x0D0
59 #define BX_LAPIC_DESTINATION_FORMAT 0x0E0
60 #define BX_LAPIC_SPURIOUS_VECTOR 0x0F0
61 #define BX_LAPIC_ISR1 0x100
62 #define BX_LAPIC_ISR2 0x110
63 #define BX_LAPIC_ISR3 0x120
64 #define BX_LAPIC_ISR4 0x130
65 #define BX_LAPIC_ISR5 0x140
66 #define BX_LAPIC_ISR6 0x150
67 #define BX_LAPIC_ISR7 0x160
68 #define BX_LAPIC_ISR8 0x170
69 #define BX_LAPIC_TMR1 0x180
70 #define BX_LAPIC_TMR2 0x190
71 #define BX_LAPIC_TMR3 0x1A0
72 #define BX_LAPIC_TMR4 0x1B0
73 #define BX_LAPIC_TMR5 0x1C0
74 #define BX_LAPIC_TMR6 0x1D0
75 #define BX_LAPIC_TMR7 0x1E0
76 #define BX_LAPIC_TMR8 0x1F0
77 #define BX_LAPIC_IRR1 0x200
78 #define BX_LAPIC_IRR2 0x210
79 #define BX_LAPIC_IRR3 0x220
80 #define BX_LAPIC_IRR4 0x230
81 #define BX_LAPIC_IRR5 0x240
82 #define BX_LAPIC_IRR6 0x250
83 #define BX_LAPIC_IRR7 0x260
84 #define BX_LAPIC_IRR8 0x270
85 #define BX_LAPIC_ESR 0x280
86 #define BX_LAPIC_LVT_CMCI 0x2F0
87 #define BX_LAPIC_ICR_LO 0x300
88 #define BX_LAPIC_ICR_HI 0x310
89 #define BX_LAPIC_LVT_TIMER 0x320
90 #define BX_LAPIC_LVT_THERMAL 0x330
91 #define BX_LAPIC_LVT_PERFMON 0x340
92 #define BX_LAPIC_LVT_LINT0 0x350
93 #define BX_LAPIC_LVT_LINT1 0x360
94 #define BX_LAPIC_LVT_ERROR 0x370
95 #define BX_LAPIC_TIMER_INITIAL_COUNT 0x380
96 #define BX_LAPIC_TIMER_CURRENT_COUNT 0x390
97 #define BX_LAPIC_TIMER_DIVIDE_CFG 0x3E0
98 #define BX_LAPIC_SELF_IPI 0x3F0
99
100 // extended AMD
101 #define BX_LAPIC_EXT_APIC_FEATURE 0x400
102 #define BX_LAPIC_EXT_APIC_CONTROL 0x410
103 #define BX_LAPIC_SPECIFIC_EOI 0x420
104 #define BX_LAPIC_IER1 0x480
105 #define BX_LAPIC_IER2 0x490
106 #define BX_LAPIC_IER3 0x4A0
107 #define BX_LAPIC_IER4 0x4B0
108 #define BX_LAPIC_IER5 0x4C0
109 #define BX_LAPIC_IER6 0x4D0
110 #define BX_LAPIC_IER7 0x4E0
111 #define BX_LAPIC_IER8 0x4F0
112
113 /* APIC delivery modes */
114 enum {
115 APIC_DM_FIXED = 0,
116 APIC_DM_LOWPRI = 1,
117 APIC_DM_SMI = 2,
118 APIC_DM_RESERVED = 3,
119 APIC_DM_NMI = 4,
120 APIC_DM_INIT = 5,
121 APIC_DM_SIPI = 6,
122 APIC_DM_EXTINT = 7
123 };
124
125 enum {
126 APIC_LVT_TIMER = 0,
127 APIC_LVT_THERMAL = 1,
128 APIC_LVT_PERFMON = 2,
129 APIC_LVT_LINT0 = 3,
130 APIC_LVT_LINT1 = 4,
131 APIC_LVT_ERROR = 5,
132 APIC_LVT_CMCI = 6,
133 APIC_LVT_ENTRIES
134 };
135
136 class BOCHSAPI bx_local_apic_c : public logfunctions
137 {
138 bx_phy_address base_addr;
139 unsigned mode;
140 bool xapic;
141 #if BX_CPU_LEVEL >= 6
142 Bit32u xapic_ext; // enabled extended XAPIC features
143 #endif
144 Bit32u apic_id; // 4 bit in legacy mode, 8 bit in XAPIC mode
145 // 32 bit in X2APIC mode
146 Bit32u apic_version_id;
147
148 bool software_enabled;
149 Bit8u spurious_vector;
150 bool focus_disable;
151
152 Bit32u task_priority; // Task priority (TPR)
153 Bit32u ldr; // Logical destination (LDR)
154 Bit32u dest_format; // Destination format (DFR)
155
156 // ISR=in-service register. When an IRR bit is cleared, the corresponding
157 // bit in ISR is set.
158 Bit32u isr[8];
159 // TMR=trigger mode register. Cleared for edge-triggered interrupts
160 // and set for level-triggered interrupts. If set, local APIC must send
161 // EOI message to all other APICs.
162 Bit32u tmr[8];
163 // IRR=interrupt request register. When an interrupt is triggered by
164 // the I/O APIC or another processor, it sets a bit in irr. The bit is
165 // cleared when the interrupt is acknowledged by the processor.
166 Bit32u irr[8];
167 #if BX_CPU_LEVEL >= 6
168 // IER=interrupt enable register. Only vectors that are enabled in IER
169 // participare in APIC's computation of highest priority pending interrupt.
170 Bit32u ier[8];
171 #endif
172
173 #define APIC_ERR_ILLEGAL_ADDR 0x80
174 #define APIC_ERR_RX_ILLEGAL_VEC 0x40
175 #define APIC_ERR_TX_ILLEGAL_VEC 0x20
176 #define X2APIC_ERR_REDIRECTIBLE_IPI 0x08
177 #define APIC_ERR_RX_ACCEPT_ERR 0x08
178 #define APIC_ERR_TX_ACCEPT_ERR 0x04
179 #define APIC_ERR_RX_CHECKSUM 0x02
180 #define APIC_ERR_TX_CHECKSUM 0x01
181
182 // Error status Register (ESR)
183 Bit32u error_status, shadow_error_status;
184
185 Bit32u icr_hi; // Interrupt command register (ICR)
186 Bit32u icr_lo;
187
188 Bit32u lvt[APIC_LVT_ENTRIES];
189
190 Bit32u timer_initial; // Initial timer count (in order to reload periodic timer)
191 Bit32u timer_current; // Current timer count
192 Bit64u ticksInitial; // Timer value when it started to count, also holds TSC-Deadline value
193
194 Bit32u timer_divconf; // Timer divide configuration register
195 Bit32u timer_divide_factor;
196
197 // Internal timer state, not accessible from bus
198 bool timer_active;
199 int timer_handle;
200
201 #if BX_SUPPORT_VMX >= 2
202 int vmx_timer_handle;
203 Bit32u vmx_preemption_timer_value;
204 Bit64u vmx_preemption_timer_initial; //The value of system tick when set the timer (absolute value)
205 Bit64u vmx_preemption_timer_fire; //The value of system tick when fire the exception (absolute value)
206 Bit32u vmx_preemption_timer_rate; //rate stated in MSR_VMX_MISC
207 bool vmx_timer_active;
208 #endif
209
210 #if BX_SUPPORT_MONITOR_MWAIT
211 int mwaitx_timer_handle;
212 bool mwaitx_timer_active;
213 #endif
214
215 BX_CPU_C *cpu;
216
217 bool get_vector(Bit32u *reg, unsigned vector);
218 void set_vector(Bit32u *reg, unsigned vector);
219 void clear_vector(Bit32u *reg, unsigned vector);
220
221 public:
222 bool INTR;
223 bx_local_apic_c(BX_CPU_C *cpu, unsigned id);
~bx_local_apic_c()224 ~bx_local_apic_c() { }
225 void reset(unsigned type);
get_base(void)226 bx_phy_address get_base(void) const { return base_addr; }
227 void set_base(bx_phy_address newbase);
get_id()228 Bit32u get_id() const { return apic_id; }
is_xapic()229 bool is_xapic() const { return xapic; }
230 bool is_selected(bx_phy_address addr);
231 void read(bx_phy_address addr, void *data, unsigned len);
232 void write(bx_phy_address addr, void *data, unsigned len);
233 void write_aligned(bx_phy_address addr, Bit32u data);
234 Bit32u read_aligned(bx_phy_address address);
235 #if BX_CPU_LEVEL >= 6
236 bool read_x2apic(unsigned index, Bit64u *msr);
237 bool write_x2apic(unsigned index, Bit32u msr_hi, Bit32u msr_lo);
238 #endif
239 // on local APIC, trigger means raise the CPU's INTR line. For now
240 // I also have to raise pc_system.INTR but that should be replaced
241 // with the cpu-specific INTR signals.
242 void trigger_irq(Bit8u vector, unsigned trigger_mode, bool bypass_irr_isr = 0);
243 void untrigger_irq(Bit8u vector, unsigned trigger_mode);
244 Bit8u acknowledge_int(void); // only the local CPU should call this
245 int highest_priority_int(Bit32u *array);
246 void receive_EOI(Bit32u value);
247 void send_ipi(apic_dest_t dest, Bit32u lo_cmd);
248 void write_spurious_interrupt_register(Bit32u value);
249 void service_local_apic(void);
250 void print_status(void);
251 bool match_logical_addr(apic_dest_t address);
252 bool deliver(Bit8u vector, Bit8u delivery_mode, Bit8u trig_mode);
get_tpr(void)253 Bit8u get_tpr(void) { return task_priority; }
254 void set_tpr(Bit8u tpr);
255 Bit8u get_ppr(void);
256 Bit8u get_apr(void);
257 bool is_focus(Bit8u vector);
258 void set_lvt_entry(unsigned apic_reg, Bit32u val);
259
260 static void periodic_smf(void *);
261 void periodic(void);
262 void set_divide_configuration(Bit32u value);
263 void set_initial_timer_count(Bit32u value);
264 Bit32u get_current_timer_count(void);
265
266 #if BX_CPU_LEVEL >= 6
267 Bit64u get_tsc_deadline(void);
268 void set_tsc_deadline(Bit64u value);
269 void receive_SEOI(Bit8u vec);
270 void enable_xapic_extensions(void);
271 #endif
272
273 void startup_msg(Bit8u vector);
274 void register_state(bx_param_c *parent);
275 #if BX_SUPPORT_VMX >= 2
276 Bit32u read_vmx_preemption_timer(void);
277 void set_vmx_preemption_timer(Bit32u value);
278 void deactivate_vmx_preemption_timer(void);
279 static void vmx_preemption_timer_expired(void *);
280 #endif
281
282 #if BX_SUPPORT_MONITOR_MWAIT
283 void set_mwaitx_timer(Bit32u value);
284 void deactivate_mwaitx_timer(void);
285 static void mwaitx_timer_expired(void *);
286 #endif
287 };
288
289 int apic_bus_deliver_lowest_priority(Bit8u vector, apic_dest_t dest, bool trig_mode, bool broadcast);
290 BOCHSAPI_MSVCONLY int apic_bus_deliver_interrupt(Bit8u vector, apic_dest_t dest, Bit8u delivery_mode, bool logical_dest, bool level, bool trig_mode);
291 int apic_bus_broadcast_interrupt(Bit8u vector, Bit8u delivery_mode, bool trig_mode, int exclude_cpu);
292
is_x2apic_msr_range(Bit32u index)293 BX_CPP_INLINE bool is_x2apic_msr_range(Bit32u index) { return index >= 0x800 && index <= 0x8FF; }
294
295 #endif // if BX_SUPPORT_APIC
296
297 #endif
298