1 /////////////////////////////////////////////////////////////////////////
2 // $Id: exception.cc 14133 2021-02-08 13:06:44Z sshwarts $
3 /////////////////////////////////////////////////////////////////////////
4 //
5 // Copyright (C) 2001-2019 The Bochs Project
6 //
7 // This library is free software; you can redistribute it and/or
8 // modify it under the terms of the GNU Lesser General Public
9 // License as published by the Free Software Foundation; either
10 // version 2 of the License, or (at your option) any later version.
11 //
12 // This library is distributed in the hope that it will be useful,
13 // but WITHOUT ANY WARRANTY; without even the implied warranty of
14 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 // Lesser General Public License for more details.
16 //
17 // You should have received a copy of the GNU Lesser General Public
18 // License along with this library; if not, write to the Free Software
19 // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
20 //
21 /////////////////////////////////////////////////////////////////////////
22
23 #define NEED_CPU_REG_SHORTCUTS 1
24 #include "bochs.h"
25 #include "cpu.h"
26 #define LOG_THIS BX_CPU_THIS_PTR
27
28 #include "param_names.h"
29 #include "iodev/iodev.h"
30
31 #if BX_SUPPORT_X86_64==0
32 // Make life easier merging cpu64 & cpu code.
33 #define RIP EIP
34 #define RSP ESP
35 #endif
36
37 #if BX_SUPPORT_X86_64
long_mode_int(Bit8u vector,unsigned soft_int,bool push_error,Bit16u error_code)38 void BX_CPU_C::long_mode_int(Bit8u vector, unsigned soft_int, bool push_error, Bit16u error_code)
39 {
40 bx_descriptor_t gate_descriptor, cs_descriptor;
41 bx_selector_t cs_selector;
42
43 // interrupt vector must be within IDT table limits,
44 // else #GP(vector*8 + 2 + EXT)
45 if ((vector*16 + 15) > BX_CPU_THIS_PTR idtr.limit) {
46 BX_ERROR(("interrupt(long mode): vector must be within IDT table limits, IDT.limit = 0x%x", BX_CPU_THIS_PTR idtr.limit));
47 exception(BX_GP_EXCEPTION, vector*8 + 2);
48 }
49
50 Bit64u desctmp1 = system_read_qword(BX_CPU_THIS_PTR idtr.base + vector*16);
51 Bit64u desctmp2 = system_read_qword(BX_CPU_THIS_PTR idtr.base + vector*16 + 8);
52
53 if (desctmp2 & BX_CONST64(0x00001F0000000000)) {
54 BX_ERROR(("interrupt(long mode): IDT entry extended attributes DWORD4 TYPE != 0"));
55 exception(BX_GP_EXCEPTION, vector*8 + 2);
56 }
57
58 Bit32u dword1 = GET32L(desctmp1);
59 Bit32u dword2 = GET32H(desctmp1);
60 Bit32u dword3 = GET32L(desctmp2);
61
62 parse_descriptor(dword1, dword2, &gate_descriptor);
63
64 if ((gate_descriptor.valid==0) || gate_descriptor.segment)
65 {
66 BX_ERROR(("interrupt(long mode): gate descriptor is not valid sys seg"));
67 exception(BX_GP_EXCEPTION, vector*8 + 2);
68 }
69
70 // descriptor AR byte must indicate interrupt gate, trap gate,
71 // or task gate, else #GP(vector*8 + 2 + EXT)
72 if (gate_descriptor.type != BX_386_INTERRUPT_GATE &&
73 gate_descriptor.type != BX_386_TRAP_GATE)
74 {
75 BX_ERROR(("interrupt(long mode): unsupported gate type %u",
76 (unsigned) gate_descriptor.type));
77 exception(BX_GP_EXCEPTION, vector*8 + 2);
78 }
79
80 // if software interrupt, then gate descriptor DPL must be >= CPL,
81 // else #GP(vector * 8 + 2 + EXT)
82 if (soft_int && gate_descriptor.dpl < CPL)
83 {
84 BX_ERROR(("interrupt(long mode): soft_int && gate.dpl < CPL"));
85 exception(BX_GP_EXCEPTION, vector*8 + 2);
86 }
87
88 // Gate must be present, else #NP(vector * 8 + 2 + EXT)
89 if (! IS_PRESENT(gate_descriptor)) {
90 BX_ERROR(("interrupt(long mode): gate.p == 0"));
91 exception(BX_NP_EXCEPTION, vector*8 + 2);
92 }
93
94 Bit16u gate_dest_selector = gate_descriptor.u.gate.dest_selector;
95 Bit64u gate_dest_offset = ((Bit64u)dword3 << 32) | gate_descriptor.u.gate.dest_offset;
96
97 unsigned ist = gate_descriptor.u.gate.param_count & 0x7;
98
99 // examine CS selector and descriptor given in gate descriptor
100 // selector must be non-null else #GP(EXT)
101 if ((gate_dest_selector & 0xfffc) == 0) {
102 BX_ERROR(("int_trap_gate(long mode): selector null"));
103 exception(BX_GP_EXCEPTION, 0);
104 }
105
106 parse_selector(gate_dest_selector, &cs_selector);
107
108 // selector must be within its descriptor table limits
109 // else #GP(selector+EXT)
110 fetch_raw_descriptor(&cs_selector, &dword1, &dword2, BX_GP_EXCEPTION);
111 parse_descriptor(dword1, dword2, &cs_descriptor);
112
113 // descriptor AR byte must indicate code seg
114 // and code segment descriptor DPL<=CPL, else #GP(selector+EXT)
115 if (cs_descriptor.valid==0 || cs_descriptor.segment==0 ||
116 IS_DATA_SEGMENT(cs_descriptor.type) ||
117 cs_descriptor.dpl > CPL)
118 {
119 BX_ERROR(("interrupt(long mode): not accessible or not code segment"));
120 exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc);
121 }
122
123 // check that it's a 64 bit segment
124 if (! IS_LONG64_SEGMENT(cs_descriptor) || cs_descriptor.u.segment.d_b)
125 {
126 BX_ERROR(("interrupt(long mode): must be 64 bit segment"));
127 exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc);
128 }
129
130 // segment must be present, else #NP(selector + EXT)
131 if (! IS_PRESENT(cs_descriptor)) {
132 BX_ERROR(("interrupt(long mode): segment not present"));
133 exception(BX_NP_EXCEPTION, cs_selector.value & 0xfffc);
134 }
135
136 Bit64u RSP_for_cpl_x;
137 #if BX_SUPPORT_CET
138 bx_address new_SSP = 0; // keep warning silent
139 unsigned old_SS_DPL = BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.dpl;
140 unsigned old_CPL = CPL;
141 bx_address return_LIP = get_laddr(BX_SEG_REG_CS, RIP);
142 bool check_ss_token = true;
143 #endif
144
145 Bit64u old_CS = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value;
146 Bit64u old_RIP = RIP;
147 Bit64u old_SS = BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value;
148 Bit64u old_RSP = RSP;
149
150 // if code segment is non-conforming and DPL < CPL then
151 // INTERRUPT TO INNER PRIVILEGE:
152 if (IS_CODE_SEGMENT_NON_CONFORMING(cs_descriptor.type) && cs_descriptor.dpl < CPL)
153 {
154 BX_DEBUG(("interrupt(long mode): INTERRUPT TO INNER PRIVILEGE"));
155
156 // check selector and descriptor for new stack in current TSS
157 if (ist > 0) {
158 BX_DEBUG(("interrupt(long mode): trap to IST, vector = %d", ist));
159 RSP_for_cpl_x = get_RSP_from_TSS(ist+3);
160 #if BX_SUPPORT_CET
161 if (ShadowStackEnabled(0)) {
162 bx_address new_SSP_addr = BX_CPU_THIS_PTR msr.ia32_interrupt_ssp_table + (ist<<3);
163 new_SSP = system_read_qword(new_SSP_addr);
164 }
165 #endif
166 }
167 else {
168 RSP_for_cpl_x = get_RSP_from_TSS(cs_descriptor.dpl);
169 #if BX_SUPPORT_CET
170 new_SSP = BX_CPU_THIS_PTR msr.ia32_pl_ssp[cs_descriptor.dpl];
171 #endif
172 }
173
174 // align stack
175 RSP_for_cpl_x &= BX_CONST64(0xfffffffffffffff0);
176
177 // push old stack long pointer onto new stack
178 write_new_stack_qword(RSP_for_cpl_x - 8, cs_descriptor.dpl, old_SS);
179 write_new_stack_qword(RSP_for_cpl_x - 16, cs_descriptor.dpl, old_RSP);
180 write_new_stack_qword(RSP_for_cpl_x - 24, cs_descriptor.dpl, read_eflags());
181 // push long pointer to return address onto new stack
182 write_new_stack_qword(RSP_for_cpl_x - 32, cs_descriptor.dpl, old_CS);
183 write_new_stack_qword(RSP_for_cpl_x - 40, cs_descriptor.dpl, old_RIP);
184 RSP_for_cpl_x -= 40;
185
186 if (push_error) {
187 RSP_for_cpl_x -= 8;
188 write_new_stack_qword(RSP_for_cpl_x, cs_descriptor.dpl, error_code);
189 }
190
191 // load CS:RIP (guaranteed to be in 64 bit mode)
192 branch_far(&cs_selector, &cs_descriptor, gate_dest_offset, cs_descriptor.dpl);
193
194 // set up null SS descriptor
195 load_null_selector(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS], cs_descriptor.dpl);
196 }
197 else if(IS_CODE_SEGMENT_CONFORMING(cs_descriptor.type) || cs_descriptor.dpl==CPL)
198 {
199 // if code segment is conforming OR code segment DPL = CPL then
200 // INTERRUPT TO SAME PRIVILEGE LEVEL:
201
202 BX_DEBUG(("interrupt(long mode): INTERRUPT TO SAME PRIVILEGE"));
203
204 // check selector and descriptor for new stack in current TSS
205 if (ist > 0) {
206 BX_DEBUG(("interrupt(long mode): trap to IST, vector = %d", ist));
207 RSP_for_cpl_x = get_RSP_from_TSS(ist+3);
208 #if BX_SUPPORT_CET
209 if (ShadowStackEnabled(CPL)) {
210 bx_address new_SSP_addr = BX_CPU_THIS_PTR msr.ia32_interrupt_ssp_table + (ist<<3);
211 new_SSP = system_read_qword(new_SSP_addr);
212 }
213 #endif
214 }
215 else {
216 RSP_for_cpl_x = RSP;
217 #if BX_SUPPORT_CET
218 new_SSP = SSP;
219 check_ss_token = false;
220 #endif
221 }
222
223 // align stack
224 RSP_for_cpl_x &= BX_CONST64(0xfffffffffffffff0);
225
226 // push flags onto stack
227 // push current CS selector onto stack
228 // push return offset onto stack
229 write_new_stack_qword(RSP_for_cpl_x - 8, cs_descriptor.dpl, old_SS);
230 write_new_stack_qword(RSP_for_cpl_x - 16, cs_descriptor.dpl, old_RSP);
231 write_new_stack_qword(RSP_for_cpl_x - 24, cs_descriptor.dpl, read_eflags());
232 // push long pointer to return address onto new stack
233 write_new_stack_qword(RSP_for_cpl_x - 32, cs_descriptor.dpl, old_CS);
234 write_new_stack_qword(RSP_for_cpl_x - 40, cs_descriptor.dpl, old_RIP);
235 RSP_for_cpl_x -= 40;
236
237 if (push_error) {
238 RSP_for_cpl_x -= 8;
239 write_new_stack_qword(RSP_for_cpl_x, cs_descriptor.dpl, error_code);
240 }
241
242 // set the RPL field of CS to CPL
243 branch_far(&cs_selector, &cs_descriptor, gate_dest_offset, CPL);
244 }
245 else {
246 BX_ERROR(("interrupt(long mode): bad descriptor type %u (CS.DPL=%u CPL=%u)",
247 (unsigned) cs_descriptor.type, (unsigned) cs_descriptor.dpl, (unsigned) CPL));
248 exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc);
249 }
250
251 #if BX_SUPPORT_CET
252 if(ShadowStackEnabled(old_CPL)) {
253 if (old_CPL == 3)
254 BX_CPU_THIS_PTR msr.ia32_pl_ssp[3] = SSP;
255 }
256 if (ShadowStackEnabled(CPL)) {
257 bx_address old_SSP = SSP;
258 if(check_ss_token)
259 shadow_stack_switch(new_SSP);
260 if (old_SS_DPL != 3)
261 call_far_shadow_stack_push(old_CS, return_LIP, old_SSP);
262 }
263 track_indirect(CPL);
264 #endif
265
266 RSP = RSP_for_cpl_x;
267
268 // if interrupt gate then set IF to 0
269 if (!(gate_descriptor.type & 1)) // even is int-gate
270 BX_CPU_THIS_PTR clear_IF();
271 BX_CPU_THIS_PTR clear_TF();
272 //BX_CPU_THIS_PTR clear_VM(); // VM is clear in long mode
273 BX_CPU_THIS_PTR clear_RF();
274 BX_CPU_THIS_PTR clear_NT();
275 }
276 #endif
277
protected_mode_int(Bit8u vector,unsigned soft_int,bool push_error,Bit16u error_code)278 void BX_CPU_C::protected_mode_int(Bit8u vector, unsigned soft_int, bool push_error, Bit16u error_code)
279 {
280 bx_descriptor_t gate_descriptor, cs_descriptor;
281 bx_selector_t cs_selector;
282
283 Bit16u raw_tss_selector;
284 bx_selector_t tss_selector;
285 bx_descriptor_t tss_descriptor;
286
287 // interrupt vector must be within IDT table limits,
288 // else #GP(vector*8 + 2 + EXT)
289 if ((vector*8 + 7) > BX_CPU_THIS_PTR idtr.limit) {
290 BX_ERROR(("interrupt(): vector must be within IDT table limits, IDT.limit = 0x%x", BX_CPU_THIS_PTR idtr.limit));
291 exception(BX_GP_EXCEPTION, vector*8 + 2);
292 }
293
294 Bit64u desctmp = system_read_qword(BX_CPU_THIS_PTR idtr.base + vector*8);
295
296 Bit32u dword1 = GET32L(desctmp);
297 Bit32u dword2 = GET32H(desctmp);
298
299 parse_descriptor(dword1, dword2, &gate_descriptor);
300
301 if ((gate_descriptor.valid==0) || gate_descriptor.segment) {
302 BX_ERROR(("interrupt(): gate descriptor is not valid sys seg (vector=0x%02x)", vector));
303 exception(BX_GP_EXCEPTION, vector*8 + 2);
304 }
305
306 // descriptor AR byte must indicate interrupt gate, trap gate,
307 // or task gate, else #GP(vector*8 + 2 + EXT)
308 switch (gate_descriptor.type) {
309 case BX_TASK_GATE:
310 case BX_286_INTERRUPT_GATE:
311 case BX_286_TRAP_GATE:
312 case BX_386_INTERRUPT_GATE:
313 case BX_386_TRAP_GATE:
314 break;
315 default:
316 BX_ERROR(("interrupt(): gate.type(%u) != {5,6,7,14,15}",
317 (unsigned) gate_descriptor.type));
318 exception(BX_GP_EXCEPTION, vector*8 + 2);
319 }
320
321 // if software interrupt, then gate descriptor DPL must be >= CPL,
322 // else #GP(vector * 8 + 2 + EXT)
323 if (soft_int && gate_descriptor.dpl < CPL) {
324 BX_ERROR(("interrupt(): soft_int && (gate.dpl < CPL)"));
325 exception(BX_GP_EXCEPTION, vector*8 + 2);
326 }
327
328 // Gate must be present, else #NP(vector * 8 + 2 + EXT)
329 if (! IS_PRESENT(gate_descriptor)) {
330 BX_ERROR(("interrupt(): gate not present"));
331 exception(BX_NP_EXCEPTION, vector*8 + 2);
332 }
333
334 switch (gate_descriptor.type) {
335 case BX_TASK_GATE:
336 // examine selector to TSS, given in task gate descriptor
337 raw_tss_selector = gate_descriptor.u.taskgate.tss_selector;
338 parse_selector(raw_tss_selector, &tss_selector);
339
340 // must specify global in the local/global bit,
341 // else #GP(TSS selector)
342 if (tss_selector.ti) {
343 BX_ERROR(("interrupt(): tss_selector.ti=1 from gate descriptor - #GP(tss_selector)"));
344 exception(BX_GP_EXCEPTION, raw_tss_selector & 0xfffc);
345 }
346
347 // index must be within GDT limits, else #TS(TSS selector)
348 fetch_raw_descriptor(&tss_selector, &dword1, &dword2, BX_GP_EXCEPTION);
349
350 parse_descriptor(dword1, dword2, &tss_descriptor);
351
352 // AR byte must specify available TSS,
353 // else #GP(TSS selector)
354 if (tss_descriptor.valid==0 || tss_descriptor.segment) {
355 BX_ERROR(("interrupt(): TSS selector points to invalid or bad TSS - #GP(tss_selector)"));
356 exception(BX_GP_EXCEPTION, raw_tss_selector & 0xfffc);
357 }
358
359 if (tss_descriptor.type!=BX_SYS_SEGMENT_AVAIL_286_TSS &&
360 tss_descriptor.type!=BX_SYS_SEGMENT_AVAIL_386_TSS)
361 {
362 BX_ERROR(("interrupt(): TSS selector points to bad TSS - #GP(tss_selector)"));
363 exception(BX_GP_EXCEPTION, raw_tss_selector & 0xfffc);
364 }
365
366 // TSS must be present, else #NP(TSS selector)
367 if (! IS_PRESENT(tss_descriptor)) {
368 BX_ERROR(("interrupt(): TSS descriptor.p == 0"));
369 exception(BX_NP_EXCEPTION, raw_tss_selector & 0xfffc);
370 }
371
372 // switch tasks with nesting to TSS
373 task_switch(0, &tss_selector, &tss_descriptor,
374 BX_TASK_FROM_INT, dword1, dword2, push_error, error_code);
375 return;
376
377 case BX_286_INTERRUPT_GATE:
378 case BX_286_TRAP_GATE:
379 case BX_386_INTERRUPT_GATE:
380 case BX_386_TRAP_GATE:
381 {
382 Bit16u gate_dest_selector = gate_descriptor.u.gate.dest_selector;
383 Bit32u gate_dest_offset = gate_descriptor.u.gate.dest_offset;
384
385 // examine CS selector and descriptor given in gate descriptor
386 // selector must be non-null else #GP(EXT)
387 if ((gate_dest_selector & 0xfffc) == 0) {
388 BX_ERROR(("int_trap_gate(): selector null"));
389 exception(BX_GP_EXCEPTION, 0);
390 }
391
392 parse_selector(gate_dest_selector, &cs_selector);
393
394 // selector must be within its descriptor table limits
395 // else #GP(selector+EXT)
396 fetch_raw_descriptor(&cs_selector, &dword1, &dword2, BX_GP_EXCEPTION);
397 parse_descriptor(dword1, dword2, &cs_descriptor);
398
399 // descriptor AR byte must indicate code seg
400 // and code segment descriptor DPL<=CPL, else #GP(selector+EXT)
401 if (cs_descriptor.valid==0 || cs_descriptor.segment==0 ||
402 IS_DATA_SEGMENT(cs_descriptor.type) ||
403 cs_descriptor.dpl > CPL)
404 {
405 BX_ERROR(("interrupt(): not accessible or not code segment cs=0x%04x", cs_selector.value));
406 exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc);
407 }
408
409 // segment must be present, else #NP(selector + EXT)
410 if (! IS_PRESENT(cs_descriptor)) {
411 BX_ERROR(("interrupt(): segment not present"));
412 exception(BX_NP_EXCEPTION, cs_selector.value & 0xfffc);
413 }
414
415 Bit32u old_ESP = ESP;
416 Bit16u old_SS = BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value;
417 Bit32u old_EIP = EIP;
418 Bit16u old_CS = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value;
419
420 #if BX_SUPPORT_CET
421 bx_address new_SSP = BX_CPU_THIS_PTR msr.ia32_pl_ssp[cs_descriptor.dpl];
422 Bit32u return_LIP = get_laddr(BX_SEG_REG_CS, EIP);
423 unsigned old_SS_DPL = BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.dpl;
424 unsigned old_CPL = CPL;
425 #endif
426
427 // if code segment is non-conforming and DPL < CPL then
428 // INTERRUPT TO INNER PRIVILEGE
429 if(IS_CODE_SEGMENT_NON_CONFORMING(cs_descriptor.type) && cs_descriptor.dpl < CPL)
430 {
431 Bit16u SS_for_cpl_x;
432 Bit32u ESP_for_cpl_x;
433 bx_descriptor_t ss_descriptor;
434 bx_selector_t ss_selector;
435 int is_v8086_mode = v8086_mode();
436
437 BX_DEBUG(("interrupt(): INTERRUPT TO INNER PRIVILEGE"));
438
439 // check selector and descriptor for new stack in current TSS
440 get_SS_ESP_from_TSS(cs_descriptor.dpl, &SS_for_cpl_x, &ESP_for_cpl_x);
441
442 if (is_v8086_mode && cs_descriptor.dpl != 0) {
443 // if code segment DPL != 0 then #GP(new code segment selector)
444 BX_ERROR(("interrupt(): code segment DPL(%d) != 0 in v8086 mode", cs_descriptor.dpl));
445 exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc);
446 }
447
448 // Selector must be non-null else #TS(EXT)
449 if ((SS_for_cpl_x & 0xfffc) == 0) {
450 BX_ERROR(("interrupt(): SS selector null"));
451 exception(BX_TS_EXCEPTION, 0); /* TS(ext) */
452 }
453
454 // selector index must be within its descriptor table limits
455 // else #TS(SS selector + EXT)
456 parse_selector(SS_for_cpl_x, &ss_selector);
457 // fetch 2 dwords of descriptor; call handles out of limits checks
458 fetch_raw_descriptor(&ss_selector, &dword1, &dword2, BX_TS_EXCEPTION);
459 parse_descriptor(dword1, dword2, &ss_descriptor);
460
461 // selector rpl must = dpl of code segment,
462 // else #TS(SS selector + ext)
463 if (ss_selector.rpl != cs_descriptor.dpl) {
464 BX_ERROR(("interrupt(): SS.rpl != CS.dpl"));
465 exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc);
466 }
467
468 // stack seg DPL must = DPL of code segment,
469 // else #TS(SS selector + ext)
470 if (ss_descriptor.dpl != cs_descriptor.dpl) {
471 BX_ERROR(("interrupt(): SS.dpl != CS.dpl"));
472 exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc);
473 }
474
475 // descriptor must indicate writable data segment,
476 // else #TS(SS selector + EXT)
477 if (ss_descriptor.valid==0 || ss_descriptor.segment==0 ||
478 IS_CODE_SEGMENT(ss_descriptor.type) ||
479 !IS_DATA_SEGMENT_WRITEABLE(ss_descriptor.type))
480 {
481 BX_ERROR(("interrupt(): SS is not writable data segment"));
482 exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc);
483 }
484
485 // seg must be present, else #SS(SS selector + ext)
486 if (! IS_PRESENT(ss_descriptor)) {
487 BX_ERROR(("interrupt(): SS not present"));
488 exception(BX_SS_EXCEPTION, SS_for_cpl_x & 0xfffc);
489 }
490
491 // IP must be within CS segment boundaries, else #GP(0)
492 if (gate_dest_offset > cs_descriptor.u.segment.limit_scaled) {
493 BX_ERROR(("interrupt(): gate EIP > CS.limit"));
494 exception(BX_GP_EXCEPTION, 0);
495 }
496
497 // Prepare new stack segment
498 bx_segment_reg_t new_stack;
499 new_stack.selector = ss_selector;
500 new_stack.cache = ss_descriptor;
501 new_stack.selector.rpl = cs_descriptor.dpl;
502 // add cpl to the selector value
503 new_stack.selector.value = (0xfffc & new_stack.selector.value) | new_stack.selector.rpl;
504
505 if (ss_descriptor.u.segment.d_b) {
506 Bit32u temp_ESP = ESP_for_cpl_x;
507
508 if (is_v8086_mode)
509 {
510 if (gate_descriptor.type>=14) { // 386 int/trap gate
511 write_new_stack_dword(&new_stack, temp_ESP-4, cs_descriptor.dpl,
512 BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value);
513 write_new_stack_dword(&new_stack, temp_ESP-8, cs_descriptor.dpl,
514 BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value);
515 write_new_stack_dword(&new_stack, temp_ESP-12, cs_descriptor.dpl,
516 BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value);
517 write_new_stack_dword(&new_stack, temp_ESP-16, cs_descriptor.dpl,
518 BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value);
519 temp_ESP -= 16;
520 }
521 else {
522 write_new_stack_word(&new_stack, temp_ESP-2, cs_descriptor.dpl,
523 BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value);
524 write_new_stack_word(&new_stack, temp_ESP-4, cs_descriptor.dpl,
525 BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value);
526 write_new_stack_word(&new_stack, temp_ESP-6, cs_descriptor.dpl,
527 BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value);
528 write_new_stack_word(&new_stack, temp_ESP-8, cs_descriptor.dpl,
529 BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value);
530 temp_ESP -= 8;
531 }
532 }
533
534 if (gate_descriptor.type>=14) { // 386 int/trap gate
535 // push long pointer to old stack onto new stack
536 write_new_stack_dword(&new_stack, temp_ESP-4, cs_descriptor.dpl, old_SS);
537 write_new_stack_dword(&new_stack, temp_ESP-8, cs_descriptor.dpl, old_ESP);
538 write_new_stack_dword(&new_stack, temp_ESP-12, cs_descriptor.dpl, read_eflags());
539 write_new_stack_dword(&new_stack, temp_ESP-16, cs_descriptor.dpl, old_CS);
540 write_new_stack_dword(&new_stack, temp_ESP-20, cs_descriptor.dpl, old_EIP);
541 temp_ESP -= 20;
542
543 if (push_error) {
544 temp_ESP -= 4;
545 write_new_stack_dword(&new_stack, temp_ESP, cs_descriptor.dpl, error_code);
546 }
547 }
548 else { // 286 int/trap gate
549 // push long pointer to old stack onto new stack
550 write_new_stack_word(&new_stack, temp_ESP-2, cs_descriptor.dpl, old_SS);
551 write_new_stack_word(&new_stack, temp_ESP-4, cs_descriptor.dpl, (Bit16u) old_ESP);
552 write_new_stack_word(&new_stack, temp_ESP-6, cs_descriptor.dpl, (Bit16u) read_eflags());
553 write_new_stack_word(&new_stack, temp_ESP-8, cs_descriptor.dpl, old_CS);
554 write_new_stack_word(&new_stack, temp_ESP-10, cs_descriptor.dpl, (Bit16u) old_EIP);
555 temp_ESP -= 10;
556
557 if (push_error) {
558 temp_ESP -= 2;
559 write_new_stack_word(&new_stack, temp_ESP, cs_descriptor.dpl, error_code);
560 }
561 }
562
563 ESP = temp_ESP;
564 }
565 else {
566 Bit16u temp_SP = (Bit16u) ESP_for_cpl_x;
567
568 if (is_v8086_mode)
569 {
570 if (gate_descriptor.type>=14) { // 386 int/trap gate
571 write_new_stack_dword(&new_stack, (Bit16u)(temp_SP-4), cs_descriptor.dpl,
572 BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value);
573 write_new_stack_dword(&new_stack, (Bit16u)(temp_SP-8), cs_descriptor.dpl,
574 BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value);
575 write_new_stack_dword(&new_stack, (Bit16u)(temp_SP-12), cs_descriptor.dpl,
576 BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value);
577 write_new_stack_dword(&new_stack, (Bit16u)(temp_SP-16), cs_descriptor.dpl,
578 BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value);
579 temp_SP -= 16;
580 }
581 else {
582 write_new_stack_word(&new_stack, (Bit16u)(temp_SP-2), cs_descriptor.dpl,
583 BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value);
584 write_new_stack_word(&new_stack, (Bit16u)(temp_SP-4), cs_descriptor.dpl,
585 BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value);
586 write_new_stack_word(&new_stack, (Bit16u)(temp_SP-6), cs_descriptor.dpl,
587 BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value);
588 write_new_stack_word(&new_stack, (Bit16u)(temp_SP-8), cs_descriptor.dpl,
589 BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value);
590 temp_SP -= 8;
591 }
592 }
593
594 if (gate_descriptor.type>=14) { // 386 int/trap gate
595 // push long pointer to old stack onto new stack
596 write_new_stack_dword(&new_stack, (Bit16u)(temp_SP-4), cs_descriptor.dpl, old_SS);
597 write_new_stack_dword(&new_stack, (Bit16u)(temp_SP-8), cs_descriptor.dpl, old_ESP);
598 write_new_stack_dword(&new_stack, (Bit16u)(temp_SP-12), cs_descriptor.dpl, read_eflags());
599 write_new_stack_dword(&new_stack, (Bit16u)(temp_SP-16), cs_descriptor.dpl, old_CS);
600 write_new_stack_dword(&new_stack, (Bit16u)(temp_SP-20), cs_descriptor.dpl, old_EIP);
601 temp_SP -= 20;
602
603 if (push_error) {
604 temp_SP -= 4;
605 write_new_stack_dword(&new_stack, temp_SP, cs_descriptor.dpl, error_code);
606 }
607 }
608 else { // 286 int/trap gate
609 // push long pointer to old stack onto new stack
610 write_new_stack_word(&new_stack, (Bit16u)(temp_SP-2), cs_descriptor.dpl, old_SS);
611 write_new_stack_word(&new_stack, (Bit16u)(temp_SP-4), cs_descriptor.dpl, (Bit16u) old_ESP);
612 write_new_stack_word(&new_stack, (Bit16u)(temp_SP-6), cs_descriptor.dpl, (Bit16u) read_eflags());
613 write_new_stack_word(&new_stack, (Bit16u)(temp_SP-8), cs_descriptor.dpl, old_CS);
614 write_new_stack_word(&new_stack, (Bit16u)(temp_SP-10), cs_descriptor.dpl, (Bit16u) old_EIP);
615 temp_SP -= 10;
616
617 if (push_error) {
618 temp_SP -= 2;
619 write_new_stack_word(&new_stack, temp_SP, cs_descriptor.dpl, error_code);
620 }
621 }
622
623 SP = temp_SP;
624 }
625
626 // load new CS:eIP values from gate
627 // set CPL to new code segment DPL
628 // set RPL of CS to CPL
629 load_cs(&cs_selector, &cs_descriptor, cs_descriptor.dpl);
630
631 // load new SS:eSP values from TSS
632 load_ss(&ss_selector, &ss_descriptor, cs_descriptor.dpl);
633
634 #if BX_SUPPORT_CET
635 if(ShadowStackEnabled(old_CPL)) {
636 if (old_CPL == 3)
637 BX_CPU_THIS_PTR msr.ia32_pl_ssp[3] = SSP;
638 }
639 if (ShadowStackEnabled(CPL)) {
640 bx_address old_SSP = SSP;
641 shadow_stack_switch(new_SSP);
642 if (old_SS_DPL != 3) {
643 call_far_shadow_stack_push(old_CS, return_LIP, old_SSP);
644 }
645 }
646 track_indirect(CPL);
647 #endif
648
649 if (is_v8086_mode)
650 {
651 BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.valid = 0;
652 BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value = 0;
653 BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.valid = 0;
654 BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value = 0;
655 BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.valid = 0;
656 BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value = 0;
657 BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.valid = 0;
658 BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value = 0;
659 }
660 }
661 else
662 {
663 BX_DEBUG(("interrupt(): INTERRUPT TO SAME PRIVILEGE"));
664
665 if (v8086_mode() && (IS_CODE_SEGMENT_CONFORMING(cs_descriptor.type) || cs_descriptor.dpl != 0)) {
666 // if code segment DPL != 0 then #GP(new code segment selector)
667 BX_ERROR(("interrupt(): code segment conforming or DPL(%d) != 0 in v8086 mode", cs_descriptor.dpl));
668 exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc);
669 }
670
671 // EIP must be in CS limit else #GP(0)
672 if (gate_dest_offset > cs_descriptor.u.segment.limit_scaled) {
673 BX_ERROR(("interrupt(): IP > CS descriptor limit"));
674 exception(BX_GP_EXCEPTION, 0);
675 }
676
677 // push flags onto stack
678 // push current CS selector onto stack
679 // push return offset onto stack
680 if (gate_descriptor.type >= 14) { // 386 gate
681 push_32(read_eflags());
682 push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
683 push_32(EIP);
684 if (push_error)
685 push_32(error_code);
686 }
687 else { // 286 gate
688 push_16((Bit16u) read_eflags());
689 push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
690 push_16(IP);
691 if (push_error)
692 push_16(error_code);
693 }
694
695 #if BX_SUPPORT_CET
696 if(ShadowStackEnabled(CPL)) {
697 call_far_shadow_stack_push(old_CS, return_LIP, SSP);
698 }
699 track_indirect(CPL);
700 #endif
701
702 // load CS:IP from gate
703 // load CS descriptor
704 // set the RPL field of CS to CPL
705 load_cs(&cs_selector, &cs_descriptor, CPL);
706 }
707
708 EIP = gate_dest_offset;
709
710 // if interrupt gate then set IF to 0
711 if (!(gate_descriptor.type & 1)) // even is int-gate
712 BX_CPU_THIS_PTR clear_IF();
713 BX_CPU_THIS_PTR clear_TF();
714 BX_CPU_THIS_PTR clear_NT();
715 BX_CPU_THIS_PTR clear_VM();
716 BX_CPU_THIS_PTR clear_RF();
717 return;
718 }
719 default:
720 BX_PANIC(("bad descriptor type in interrupt()!"));
721 break;
722 }
723 }
724
real_mode_int(Bit8u vector,bool push_error,Bit16u error_code)725 void BX_CPU_C::real_mode_int(Bit8u vector, bool push_error, Bit16u error_code)
726 {
727 if ((vector*4+3) > BX_CPU_THIS_PTR idtr.limit) {
728 BX_ERROR(("interrupt(real mode) vector > idtr.limit"));
729 exception(BX_GP_EXCEPTION, 0);
730 }
731
732 push_16((Bit16u) read_eflags());
733 push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
734 push_16(IP);
735
736 Bit16u new_ip = system_read_word(BX_CPU_THIS_PTR idtr.base + 4 * vector);
737 // CS.LIMIT can't change when in real/v8086 mode
738 if (new_ip > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled) {
739 BX_ERROR(("interrupt(real mode): instruction pointer not within code segment limits"));
740 exception(BX_GP_EXCEPTION, 0);
741 }
742
743 Bit16u cs_selector = system_read_word(BX_CPU_THIS_PTR idtr.base + 4 * vector + 2);
744 load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_selector);
745 EIP = new_ip;
746
747 /* INT affects the following flags: I,T */
748 BX_CPU_THIS_PTR clear_IF();
749 BX_CPU_THIS_PTR clear_TF();
750 #if BX_CPU_LEVEL >= 4
751 BX_CPU_THIS_PTR clear_AC();
752 #endif
753 BX_CPU_THIS_PTR clear_RF();
754 }
755
interrupt(Bit8u vector,unsigned type,bool push_error,Bit16u error_code)756 void BX_CPU_C::interrupt(Bit8u vector, unsigned type, bool push_error, Bit16u error_code)
757 {
758 #if BX_DEBUGGER
759 BX_CPU_THIS_PTR show_flag |= Flag_intsig;
760 #if BX_DEBUG_LINUX
761 if (bx_dbg.linux_syscall) {
762 if (vector == 0x80) bx_dbg_linux_syscall(BX_CPU_ID);
763 }
764 #endif
765 bx_dbg_interrupt(BX_CPU_ID, vector, error_code);
766 #endif
767
768 BX_INSTR_INTERRUPT(BX_CPU_ID, vector);
769
770 invalidate_prefetch_q();
771
772 bool soft_int = 0;
773 switch(type) {
774 case BX_SOFTWARE_INTERRUPT:
775 case BX_SOFTWARE_EXCEPTION:
776 soft_int = 1;
777 break;
778 case BX_PRIVILEGED_SOFTWARE_INTERRUPT:
779 case BX_EXTERNAL_INTERRUPT:
780 case BX_NMI:
781 case BX_HARDWARE_EXCEPTION:
782 break;
783
784 default:
785 BX_PANIC(("interrupt(): unknown exception type %d", type));
786 }
787
788 BX_DEBUG(("interrupt(): vector = %02x, TYPE = %u, EXT = %u",
789 vector, type, (unsigned) BX_CPU_THIS_PTR EXT));
790
791 // Discard any traps and inhibits for new context; traps will
792 // resume upon return.
793 BX_CPU_THIS_PTR debug_trap = 0;
794 BX_CPU_THIS_PTR inhibit_mask = 0;
795
796 #if BX_SUPPORT_VMX || BX_SUPPORT_SVM
797 BX_CPU_THIS_PTR in_event = 1;
798 #endif
799
800 RSP_SPECULATIVE;
801
802 #if BX_SUPPORT_X86_64
803 if (long_mode()) {
804 long_mode_int(vector, soft_int, push_error, error_code);
805 }
806 else
807 #endif
808 {
809 // software interrupt can be redirected in v8086 mode
810 if (type != BX_SOFTWARE_INTERRUPT || !v8086_mode() || !v86_redirect_interrupt(vector))
811 {
812 if(real_mode()) {
813 real_mode_int(vector, push_error, error_code);
814 }
815 else {
816 protected_mode_int(vector, soft_int, push_error, error_code);
817 }
818 }
819 }
820
821 RSP_COMMIT;
822
823 #if BX_X86_DEBUGGER
824 BX_CPU_THIS_PTR in_repeat = 0;
825 #endif
826
827 #if BX_SUPPORT_VMX || BX_SUPPORT_SVM
828 BX_CPU_THIS_PTR in_event = 0;
829 #endif
830
831 BX_CPU_THIS_PTR EXT = 0;
832 }
833
834 /* Exception classes. These are used as indexes into the 'is_exception_OK'
835 * array below, and are stored in the 'exception' array also
836 */
837 enum {
838 BX_ET_BENIGN = 0,
839 BX_ET_CONTRIBUTORY = 1,
840 BX_ET_PAGE_FAULT = 2,
841 BX_ET_DOUBLE_FAULT = 10
842 };
843
844 static const bool is_exception_OK[3][3] = {
845 { 1, 1, 1 }, /* 1st exception is BENIGN */
846 { 1, 0, 1 }, /* 1st exception is CONTRIBUTORY */
847 { 1, 0, 0 } /* 1st exception is PAGE_FAULT */
848 };
849
850 enum {
851 BX_EXCEPTION_CLASS_TRAP = 0,
852 BX_EXCEPTION_CLASS_FAULT = 1,
853 BX_EXCEPTION_CLASS_ABORT = 2
854 };
855
856 struct BxExceptionInfo exceptions_info[BX_CPU_HANDLED_EXCEPTIONS] = {
857 /* DE */ { BX_ET_CONTRIBUTORY, BX_EXCEPTION_CLASS_FAULT, 0 },
858 /* DB */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
859 /* 02 */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 }, // NMI
860 /* BP */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_TRAP, 0 },
861 /* OF */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_TRAP, 0 },
862 /* BR */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
863 /* UD */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
864 /* NM */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
865 /* DF */ { BX_ET_DOUBLE_FAULT, BX_EXCEPTION_CLASS_FAULT, 1 },
866 // coprocessor segment overrun (286,386 only)
867 /* 09 */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
868 /* TS */ { BX_ET_CONTRIBUTORY, BX_EXCEPTION_CLASS_FAULT, 1 },
869 /* NP */ { BX_ET_CONTRIBUTORY, BX_EXCEPTION_CLASS_FAULT, 1 },
870 /* SS */ { BX_ET_CONTRIBUTORY, BX_EXCEPTION_CLASS_FAULT, 1 },
871 /* GP */ { BX_ET_CONTRIBUTORY, BX_EXCEPTION_CLASS_FAULT, 1 },
872 /* PF */ { BX_ET_PAGE_FAULT, BX_EXCEPTION_CLASS_FAULT, 1 },
873 /* 15 */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 }, // reserved
874 /* MF */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
875 /* AC */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 1 },
876 /* MC */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_ABORT, 0 },
877 /* XM */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
878 /* VE */ { BX_ET_PAGE_FAULT, BX_EXCEPTION_CLASS_FAULT, 0 },
879 /* CP */ { BX_ET_CONTRIBUTORY, BX_EXCEPTION_CLASS_FAULT, 1 },
880 /* 22 */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
881 /* 23 */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
882 /* 24 */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
883 /* 25 */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
884 /* 26 */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
885 /* 27 */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
886 /* 28 */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
887 /* 29 */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 },
888 /* 30 */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 }, // FIXME: SVM #SF
889 /* 31 */ { BX_ET_BENIGN, BX_EXCEPTION_CLASS_FAULT, 0 }
890 };
891
892 // vector: 0..255: vector in IDT
893 // error_code: if exception generates and error, push this error code
exception(unsigned vector,Bit16u error_code)894 void BX_CPU_C::exception(unsigned vector, Bit16u error_code)
895 {
896 unsigned exception_type = 0;
897 unsigned exception_class = BX_EXCEPTION_CLASS_FAULT;
898 bool push_error = 0;
899
900 if (vector < BX_CPU_HANDLED_EXCEPTIONS) {
901 push_error = exceptions_info[vector].push_error;
902 exception_class = exceptions_info[vector].exception_class;
903 exception_type = exceptions_info[vector].exception_type;
904 }
905 else {
906 BX_PANIC(("exception(%u): bad vector", vector));
907 }
908
909 /* Excluding page faults and double faults, error_code may not have the
910 * least significant bit set correctly. This correction is applied first
911 * to make the change transparent to any instrumentation.
912 */
913 if (vector != BX_PF_EXCEPTION && vector != BX_DF_EXCEPTION && vector != BX_CP_EXCEPTION) {
914 // Page faults have different format
915 error_code = (error_code & 0xfffe) | (Bit16u)(BX_CPU_THIS_PTR EXT);
916 }
917
918 BX_INSTR_EXCEPTION(BX_CPU_ID, vector, error_code);
919
920 #if BX_DEBUGGER
921 bx_dbg_exception(BX_CPU_ID, vector, error_code);
922 #endif
923
924 BX_DEBUG(("exception(0x%02x): error_code=%04x", vector, error_code));
925
926 #if BX_SUPPORT_VMX
927 VMexit_Event(BX_HARDWARE_EXCEPTION, vector, error_code, push_error);
928 #endif
929
930 #if BX_SUPPORT_SVM
931 SvmInterceptException(BX_HARDWARE_EXCEPTION, vector, error_code, push_error);
932 #endif
933
934 if (exception_class == BX_EXCEPTION_CLASS_FAULT)
935 {
936 // restore RIP/RSP to value before error occurred
937 RIP = BX_CPU_THIS_PTR prev_rip;
938 if (BX_CPU_THIS_PTR speculative_rsp) {
939 RSP = BX_CPU_THIS_PTR prev_rsp;
940 #if BX_SUPPORT_CET
941 SSP = BX_CPU_THIS_PTR prev_ssp;
942 #endif
943 }
944 BX_CPU_THIS_PTR speculative_rsp = 0;
945
946 if (BX_CPU_THIS_PTR last_exception_type == BX_ET_DOUBLE_FAULT)
947 {
948 debug(BX_CPU_THIS_PTR prev_rip); // print debug information to the log
949 #if BX_SUPPORT_VMX
950 VMexit_TripleFault();
951 #endif
952 #if BX_DEBUGGER
953 // trap into debugger (the same as when a PANIC occurs)
954 bx_debug_break();
955 #endif
956 if (SIM->get_param_bool(BXPN_RESET_ON_TRIPLE_FAULT)->get()) {
957 BX_ERROR(("exception(): 3rd (%d) exception with no resolution, shutdown status is %02xh, resetting", vector, DEV_cmos_get_reg(0x0f)));
958 bx_pc_system.Reset(BX_RESET_HARDWARE);
959 }
960 else {
961 BX_PANIC(("exception(): 3rd (%d) exception with no resolution", vector));
962 BX_ERROR(("WARNING: Any simulation after this point is completely bogus !"));
963 shutdown();
964 }
965 longjmp(BX_CPU_THIS_PTR jmp_buf_env, 1); // go back to main decode loop
966 }
967
968 if (vector != BX_DB_EXCEPTION) BX_CPU_THIS_PTR assert_RF();
969 }
970
971 if (vector == BX_DB_EXCEPTION) {
972 // Commit debug events to DR6: preserve DR5.BS and DR6.BD values,
973 // only software can clear them
974 BX_CPU_THIS_PTR dr6.val32 = (BX_CPU_THIS_PTR dr6.val32 & 0xffff6ff0) |
975 (BX_CPU_THIS_PTR debug_trap & 0x0000e00f);
976
977 // clear GD flag in the DR7 prior entering debug exception handler
978 BX_CPU_THIS_PTR dr7.set_GD(0);
979 }
980
981 BX_CPU_THIS_PTR EXT = 1;
982
983 /* if we've already had 1st exception, see if 2nd causes a
984 * Double Fault instead. Otherwise, just record 1st exception.
985 */
986 if (exception_type != BX_ET_DOUBLE_FAULT) {
987 if (! is_exception_OK[BX_CPU_THIS_PTR last_exception_type][exception_type]) {
988 exception(BX_DF_EXCEPTION, 0);
989 }
990 }
991
992 BX_CPU_THIS_PTR last_exception_type = exception_type;
993
994 if (real_mode()) {
995 push_error = 0; // not INT, no error code pushed
996 error_code = 0;
997 }
998
999 interrupt(vector, BX_HARDWARE_EXCEPTION, push_error, error_code);
1000
1001 BX_CPU_THIS_PTR last_exception_type = 0; // error resolved
1002
1003 longjmp(BX_CPU_THIS_PTR jmp_buf_env, 1); // go back to main decode loop
1004 }
1005