1 /*
2 * Cisco router simulation platform.
3 * Copyright (c) 2007 Christophe Fillot (cf@utc.fr)
4 *
5 * Cisco C6k-MSFC1 I/O FPGA:
6 * - Simulates a NMC93C56 Serial EEPROM.
7 * - Simulates a DALLAS DS1620 for Temperature Sensors.
8 * - Simulates console and AUX ports (SCN2681).
9 *
10 * This is very similar to c7200 platform.
11 */
12
13 #include <stdio.h>
14 #include <stdlib.h>
15 #include <string.h>
16 #include <unistd.h>
17 #include <sys/types.h>
18
19 #include <termios.h>
20 #include <fcntl.h>
21 #include <pthread.h>
22
23 #include "ptask.h"
24 #include "cpu.h"
25 #include "vm.h"
26 #include "dynamips.h"
27 #include "memory.h"
28 #include "device.h"
29 #include "dev_vtty.h"
30 #include "nmc93cX6.h"
31 #include "dev_ds1620.h"
32 #include "dev_c6msfc1.h"
33
34 /* Debugging flags */
35 #define DEBUG_UNKNOWN 1
36 #define DEBUG_ACCESS 0
37 #define DEBUG_LED 0
38 #define DEBUG_IO_CTL 0
39 #define DEBUG_ENVM 0
40
41 /* DUART RX/TX status (SRA/SRB) */
42 #define DUART_RX_READY 0x01
43 #define DUART_TX_READY 0x04
44
45 /* DUART RX/TX Interrupt Status/Mask */
46 #define DUART_TXRDYA 0x01
47 #define DUART_RXRDYA 0x02
48 #define DUART_TXRDYB 0x10
49 #define DUART_RXRDYB 0x20
50
51 /* Definitions for CPU and Midplane Serial EEPROMs */
52 #define EEPROM_CPU_DOUT 6
53 #define EEPROM_CPU_DIN 0
54 #define EEPROM_CPU_CLK 1
55 #define EEPROM_CPU_CS 2
56
57 #define EEPROM_MP_DOUT 7
58 #define EEPROM_MP_DIN 3
59 #define EEPROM_MP_CLK 4
60 #define EEPROM_MP_CS 5
61
62 /* Pack the NVRAM */
63 #define NVRAM_PACKED 0x04
64
65 /* Temperature: 22�C as default value */
66 #define C6MSFC1_DEFAULT_TEMP 22
67 #define DS1620_CHIP(d,id) (&(d)->router->ds1620_sensors[(id)])
68
69 /* IO FPGA structure */
70 struct iofpga_data {
71 vm_obj_t vm_obj;
72 struct vdevice dev;
73 c6msfc1_t *router;
74
75 /* Lock test */
76 pthread_mutex_t lock;
77
78 /* Periodic task to trigger dummy DUART IRQ */
79 ptask_id_t duart_irq_tid;
80
81 /* DUART & Console Management */
82 u_int duart_isr,duart_imr,duart_irq_seq;
83
84 /* IO control register */
85 u_int io_ctrl_reg;
86
87 /* Voltages */
88 u_int mux;
89 };
90
91 #define IOFPGA_LOCK(d) pthread_mutex_lock(&(d)->lock)
92 #define IOFPGA_UNLOCK(d) pthread_mutex_unlock(&(d)->lock)
93
94 /* CPU EEPROM definition */
95 static const struct nmc93cX6_eeprom_def eeprom_cpu_def = {
96 EEPROM_CPU_CLK, EEPROM_CPU_CS, EEPROM_CPU_DIN, EEPROM_CPU_DOUT,
97 };
98
99 /* Midplane EEPROM definition */
100 static const struct nmc93cX6_eeprom_def eeprom_midplane_def = {
101 EEPROM_MP_CLK, EEPROM_MP_CS, EEPROM_MP_DIN, EEPROM_MP_DOUT,
102 };
103
104 /* IOFPGA manages simultaneously CPU and Midplane EEPROM */
105 static const struct nmc93cX6_group eeprom_cpu_midplane = {
106 EEPROM_TYPE_NMC93C56, 2, 0,
107 EEPROM_DORD_NORMAL,
108 EEPROM_DOUT_HIGH,
109 EEPROM_DEBUG_DISABLED,
110 "CPU and Midplane EEPROM",
111 { &eeprom_cpu_def, &eeprom_midplane_def },
112 };
113
114 /* Console port input */
tty_con_input(vtty_t * vtty)115 static void tty_con_input(vtty_t *vtty)
116 {
117 struct iofpga_data *d = vtty->priv_data;
118
119 IOFPGA_LOCK(d);
120 if (d->duart_imr & DUART_RXRDYA) {
121 d->duart_isr |= DUART_RXRDYA;
122 vm_set_irq(d->router->vm,C6MSFC1_DUART_IRQ);
123 }
124 IOFPGA_UNLOCK(d);
125 }
126
127 /* AUX port input */
tty_aux_input(vtty_t * vtty)128 static void tty_aux_input(vtty_t *vtty)
129 {
130 struct iofpga_data *d = vtty->priv_data;
131
132 IOFPGA_LOCK(d);
133 if (d->duart_imr & DUART_RXRDYB) {
134 d->duart_isr |= DUART_RXRDYB;
135 vm_set_irq(d->router->vm,C6MSFC1_DUART_IRQ);
136 }
137 IOFPGA_UNLOCK(d);
138 }
139
140 /* IRQ trickery for Console and AUX ports */
tty_trigger_dummy_irq(struct iofpga_data * d,void * arg)141 static int tty_trigger_dummy_irq(struct iofpga_data *d,void *arg)
142 {
143 u_int mask;
144
145 IOFPGA_LOCK(d);
146 d->duart_irq_seq++;
147
148 if (d->duart_irq_seq == 2) {
149 mask = DUART_TXRDYA|DUART_TXRDYB;
150 if (d->duart_imr & mask) {
151 d->duart_isr |= DUART_TXRDYA|DUART_TXRDYB;
152 vm_set_irq(d->router->vm,C6MSFC1_DUART_IRQ);
153 }
154
155 d->duart_irq_seq = 0;
156 }
157
158 IOFPGA_UNLOCK(d);
159 return(0);
160 }
161
162 /*
163 * dev_c6msfc1_iofpga_access()
164 */
dev_c6msfc1_iofpga_access(cpu_gen_t * cpu,struct vdevice * dev,m_uint32_t offset,u_int op_size,u_int op_type,m_uint64_t * data)165 void *dev_c6msfc1_iofpga_access(cpu_gen_t *cpu,struct vdevice *dev,
166 m_uint32_t offset,u_int op_size,u_int op_type,
167 m_uint64_t *data)
168 {
169 struct iofpga_data *d = dev->priv_data;
170 vm_instance_t *vm = d->router->vm;
171 u_char odata;
172 int i;
173
174 if (op_type == MTS_READ)
175 *data = 0x0;
176
177 #if DEBUG_ACCESS
178 if (op_type == MTS_READ) {
179 cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx\n",
180 offset,cpu_get_pc(cpu));
181 } else {
182 cpu_log(cpu,"IO_FPGA","writing reg 0x%x at pc=0x%llx, data=0x%llx\n",
183 offset,cpu_get_pc(cpu),*data);
184 }
185 #endif
186
187 IOFPGA_LOCK(d);
188
189 switch(offset) {
190 /* I/O control register */
191 case 0x204:
192 if (op_type == MTS_WRITE) {
193 #if DEBUG_IO_CTL
194 vm_log(vm,"IO_FPGA","setting value 0x%llx in io_ctrl_reg\n",*data);
195 #endif
196 d->io_ctrl_reg = *data;
197 } else {
198 *data = d->io_ctrl_reg;
199 *data |= NVRAM_PACKED; /* Packed NVRAM */
200 }
201 break;
202
203 /* CPU/Midplane EEPROMs */
204 case 0x21c:
205 if (op_type == MTS_WRITE)
206 nmc93cX6_write(&d->router->sys_eeprom_g1,(u_int)(*data));
207 else
208 *data = nmc93cX6_read(&d->router->sys_eeprom_g1);
209 break;
210
211 /* Watchdog */
212 case 0x234:
213 break;
214
215 /*
216 * FPGA release/presence ? Flash SIMM size:
217 * 0x0001: 2048K Flash (2 banks)
218 * 0x0504: 8192K Flash (2 banks)
219 * 0x0704: 16384K Flash (2 banks)
220 * 0x0904: 32768K Flash (2 banks)
221 * 0x0B04: 65536K Flash (2 banks)
222 * 0x2001: 1024K Flash (1 bank)
223 * 0x2504: 4096K Flash (1 bank)
224 * 0x2704: 8192K Flash (1 bank)
225 * 0x2904: 16384K Flash (1 bank)
226 * 0x2B04: 32768K Flash (1 bank)
227 *
228 * Number of Flash SIMM banks + size.
229 * Touching some lower bits causes problems with environmental monitor.
230 *
231 * It is displayed by command "sh bootflash: chips"
232 */
233 case 0x23c:
234 if (op_type == MTS_READ)
235 *data = 0x2704;
236 break;
237
238 /* LEDs */
239 case 0x244:
240 #if DEBUG_LED
241 vm_log(vm,"IO_FPGA","LED register is now 0x%x (0x%x)\n",
242 *data,(~*data) & 0x0F);
243 #endif
244 break;
245
246 /* ==== DUART SCN2681 (console/aux) ==== */
247 case 0x404: /* Mode Register A (MRA) */
248 break;
249
250 case 0x40c: /* Status Register A (SRA) */
251 if (op_type == MTS_READ) {
252 odata = 0;
253
254 if (vtty_is_char_avail(vm->vtty_con))
255 odata |= DUART_RX_READY;
256
257 odata |= DUART_TX_READY;
258
259 vm_clear_irq(vm,C6MSFC1_DUART_IRQ);
260 *data = odata;
261 }
262 break;
263
264 case 0x414: /* Command Register A (CRA) */
265 /* Disable TX = High */
266 if ((op_type == MTS_WRITE) && (*data & 0x8)) {
267 vm->vtty_con->managed_flush = TRUE;
268 vtty_flush(vm->vtty_con);
269 }
270 break;
271
272 case 0x41c: /* RX/TX Holding Register A (RHRA/THRA) */
273 if (op_type == MTS_WRITE) {
274 vtty_put_char(vm->vtty_con,(char)*data);
275 d->duart_isr &= ~DUART_TXRDYA;
276 } else {
277 *data = vtty_get_char(vm->vtty_con);
278 d->duart_isr &= ~DUART_RXRDYA;
279 }
280 break;
281
282 case 0x424: /* WRITE: Aux Control Register (ACR) */
283 break;
284
285 case 0x42c: /* Interrupt Status/Mask Register (ISR/IMR) */
286 if (op_type == MTS_WRITE) {
287 d->duart_imr = *data;
288 } else
289 *data = d->duart_isr;
290 break;
291
292 case 0x434: /* Counter/Timer Upper Value (CTU) */
293 case 0x43c: /* Counter/Timer Lower Value (CTL) */
294 case 0x444: /* Mode Register B (MRB) */
295 break;
296
297 case 0x44c: /* Status Register B (SRB) */
298 if (op_type == MTS_READ) {
299 odata = 0;
300
301 if (vtty_is_char_avail(vm->vtty_aux))
302 odata |= DUART_RX_READY;
303
304 odata |= DUART_TX_READY;
305
306 //vm_clear_irq(vm,C6MSFC1_DUART_IRQ);
307 *data = odata;
308 }
309 break;
310
311 case 0x454: /* Command Register B (CRB) */
312 /* Disable TX = High */
313 if ((op_type == MTS_WRITE) && (*data & 0x8)) {
314 vm->vtty_aux->managed_flush = TRUE;
315 vtty_flush(vm->vtty_aux);
316 }
317 break;
318
319 case 0x45c: /* RX/TX Holding Register B (RHRB/THRB) */
320 if (op_type == MTS_WRITE) {
321 vtty_put_char(vm->vtty_aux,(char)*data);
322 d->duart_isr &= ~DUART_TXRDYA;
323 } else {
324 *data = vtty_get_char(vm->vtty_aux);
325 d->duart_isr &= ~DUART_RXRDYB;
326 }
327 break;
328
329 case 0x46c: /* WRITE: Output Port Configuration Register (OPCR) */
330 case 0x474: /* READ: Start Counter Command; */
331 /* WRITE: Set Output Port Bits Command */
332 case 0x47c: /* WRITE: Reset Output Port Bits Command */
333 break;
334
335 /* ==== DS 1620 (temp sensors) ==== */
336 case 0x20c: /* Temperature Control */
337 if (op_type == MTS_WRITE) {
338 for(i=0;i<C6MSFC1_TEMP_SENSORS;i++) {
339 ds1620_set_rst_bit(DS1620_CHIP(d,i),(*data >> i) & 0x01);
340 ds1620_set_clk_bit(DS1620_CHIP(d,i),(*data >> 4) & 0x01);
341 }
342 }
343 break;
344
345 case 0x214: /* Temperature data write */
346 if (op_type == MTS_WRITE) {
347 d->mux = *data;
348
349 for(i=0;i<C6MSFC1_TEMP_SENSORS;i++)
350 ds1620_write_data_bit(DS1620_CHIP(d,i),*data & 0x01);
351 }
352 break;
353
354 case 0x22c: /* Temperature data read */
355 if (op_type == MTS_READ) {
356 *data = 0;
357
358 for(i=0;i<C6MSFC1_TEMP_SENSORS;i++)
359 *data |= ds1620_read_data_bit(DS1620_CHIP(d,i)) << i;
360 }
361 break;
362
363 #if DEBUG_UNKNOWN
364 default:
365 if (op_type == MTS_READ) {
366 cpu_log(cpu,"IO_FPGA","read from addr 0x%x, pc=0x%llx (size=%u)\n",
367 offset,cpu_get_pc(cpu),op_size);
368 } else {
369 cpu_log(cpu,"IO_FPGA","write to addr 0x%x, value=0x%llx, "
370 "pc=0x%llx (size=%u)\n",
371 offset,*data,cpu_get_pc(cpu),op_size);
372 }
373 #endif
374 }
375
376 IOFPGA_UNLOCK(d);
377 return NULL;
378 }
379
380 /* Initialize EEPROM groups */
c6msfc1_init_eeprom_groups(c6msfc1_t * router)381 void c6msfc1_init_eeprom_groups(c6msfc1_t *router)
382 {
383 router->sys_eeprom_g1 = eeprom_cpu_midplane;
384 router->sys_eeprom_g1.eeprom[0] = &router->cpu_eeprom;
385 router->sys_eeprom_g1.eeprom[1] = &router->mp_eeprom;
386 }
387
388 /* Shutdown the IO FPGA device */
dev_c6msfc1_iofpga_shutdown(vm_instance_t * vm,struct iofpga_data * d)389 void dev_c6msfc1_iofpga_shutdown(vm_instance_t *vm,struct iofpga_data *d)
390 {
391 if (d != NULL) {
392 IOFPGA_LOCK(d);
393 vm->vtty_con->read_notifier = NULL;
394 vm->vtty_aux->read_notifier = NULL;
395 IOFPGA_UNLOCK(d);
396
397 /* Remove the dummy IRQ periodic task */
398 ptask_remove(d->duart_irq_tid);
399
400 /* Remove the device */
401 dev_remove(vm,&d->dev);
402
403 /* Free the structure itself */
404 free(d);
405 }
406 }
407
408 /*
409 * dev_c6msfc1_iofpga_init()
410 */
dev_c6msfc1_iofpga_init(c6msfc1_t * router,m_uint64_t paddr,m_uint32_t len)411 int dev_c6msfc1_iofpga_init(c6msfc1_t *router,m_uint64_t paddr,m_uint32_t len)
412 {
413 vm_instance_t *vm = router->vm;
414 struct iofpga_data *d;
415 u_int i;
416
417 /* Allocate private data structure */
418 if (!(d = malloc(sizeof(*d)))) {
419 fprintf(stderr,"IO_FPGA: out of memory\n");
420 return(-1);
421 }
422
423 memset(d,0,sizeof(*d));
424
425 pthread_mutex_init(&d->lock,NULL);
426 d->router = router;
427
428 for(i=0;i<C6MSFC1_TEMP_SENSORS;i++)
429 ds1620_init(DS1620_CHIP(d,i),C6MSFC1_DEFAULT_TEMP);
430
431 vm_object_init(&d->vm_obj);
432 d->vm_obj.name = "io_fpga";
433 d->vm_obj.data = d;
434 d->vm_obj.shutdown = (vm_shutdown_t)dev_c6msfc1_iofpga_shutdown;
435
436 /* Set device properties */
437 dev_init(&d->dev);
438 d->dev.name = "io_fpga";
439 d->dev.phys_addr = paddr;
440 d->dev.phys_len = len;
441 d->dev.handler = dev_c6msfc1_iofpga_access;
442 d->dev.priv_data = d;
443
444 /* Set console and AUX port notifying functions */
445 vm->vtty_con->priv_data = d;
446 vm->vtty_aux->priv_data = d;
447 vm->vtty_con->read_notifier = tty_con_input;
448 vm->vtty_aux->read_notifier = tty_aux_input;
449
450 /* Trigger periodically a dummy IRQ to flush buffers */
451 d->duart_irq_tid = ptask_add((ptask_callback)tty_trigger_dummy_irq,
452 d,NULL);
453
454 /* Map this device to the VM */
455 vm_bind_device(vm,&d->dev);
456 vm_object_add(vm,&d->vm_obj);
457 return(0);
458 }
459