1 /* 2 * Cisco router simulation platform. 3 * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr) 4 */ 5 6 #ifndef __MIPS_64_H__ 7 #define __MIPS_64_H__ 8 9 #include <pthread.h> 10 11 #include "utils.h" 12 #include "rbtree.h" 13 14 /* 15 * MIPS General Purpose Registers 16 */ 17 #define MIPS_GPR_ZERO 0 /* zero */ 18 #define MIPS_GPR_AT 1 /* at */ 19 #define MIPS_GPR_V0 2 /* v0 */ 20 #define MIPS_GPR_V1 3 /* v1 */ 21 #define MIPS_GPR_A0 4 /* a0 */ 22 #define MIPS_GPR_A1 5 /* a1 */ 23 #define MIPS_GPR_A2 6 /* a2 */ 24 #define MIPS_GPR_A3 7 /* a3 */ 25 #define MIPS_GPR_T0 8 /* t0 */ 26 #define MIPS_GPR_T1 9 /* t1 */ 27 #define MIPS_GPR_T2 10 /* t2 */ 28 #define MIPS_GPR_T3 11 /* t3 */ 29 #define MIPS_GPR_T4 12 /* t4 */ 30 #define MIPS_GPR_T5 13 /* t5 */ 31 #define MIPS_GPR_T6 14 /* t6 */ 32 #define MIPS_GPR_T7 15 /* t7 */ 33 #define MIPS_GPR_S0 16 /* s0 */ 34 #define MIPS_GPR_S1 17 /* s1 */ 35 #define MIPS_GPR_S2 18 /* s2 */ 36 #define MIPS_GPR_S3 19 /* s3 */ 37 #define MIPS_GPR_S4 20 /* s4 */ 38 #define MIPS_GPR_S5 21 /* s5 */ 39 #define MIPS_GPR_S6 22 /* s6 */ 40 #define MIPS_GPR_S7 23 /* s7 */ 41 #define MIPS_GPR_T8 24 /* t8 */ 42 #define MIPS_GPR_T9 25 /* t9 */ 43 #define MIPS_GPR_K0 26 /* k0 */ 44 #define MIPS_GPR_K1 27 /* k1 */ 45 #define MIPS_GPR_GP 28 /* gp */ 46 #define MIPS_GPR_SP 29 /* sp */ 47 #define MIPS_GPR_FP 30 /* fp */ 48 #define MIPS_GPR_RA 31 /* ra */ 49 50 /* 51 * Coprocessor 0 (System Coprocessor) Register definitions 52 */ 53 #define MIPS_CP0_INDEX 0 /* TLB Index */ 54 #define MIPS_CP0_RANDOM 1 /* TLB Random */ 55 #define MIPS_CP0_TLB_LO_0 2 /* TLB Entry Lo0 */ 56 #define MIPS_CP0_TLB_LO_1 3 /* TLB Entry Lo1 */ 57 #define MIPS_CP0_CONTEXT 4 /* Kernel PTE pointer */ 58 #define MIPS_CP0_PAGEMASK 5 /* TLB Page Mask */ 59 #define MIPS_CP0_WIRED 6 /* TLB Wired */ 60 #define MIPS_CP0_INFO 7 /* Info (RM7000) */ 61 #define MIPS_CP0_BADVADDR 8 /* Bad Virtual Address */ 62 #define MIPS_CP0_COUNT 9 /* Count */ 63 #define MIPS_CP0_TLB_HI 10 /* TLB Entry Hi */ 64 #define MIPS_CP0_COMPARE 11 /* Timer Compare */ 65 #define MIPS_CP0_STATUS 12 /* Status */ 66 #define MIPS_CP0_CAUSE 13 /* Cause */ 67 #define MIPS_CP0_EPC 14 /* Exception PC */ 68 #define MIPS_CP0_PRID 15 /* Proc Rev ID */ 69 #define MIPS_CP0_CONFIG 16 /* Configuration */ 70 #define MIPS_CP0_LLADDR 17 /* Load/Link address */ 71 #define MIPS_CP0_WATCHLO 18 /* Low Watch address */ 72 #define MIPS_CP0_WATCHHI 19 /* High Watch address */ 73 #define MIPS_CP0_XCONTEXT 20 /* Extended context */ 74 #define MIPS_CP0_ECC 26 /* ECC and parity */ 75 #define MIPS_CP0_CACHERR 27 /* Cache Err/Status */ 76 #define MIPS_CP0_TAGLO 28 /* Cache Tag Lo */ 77 #define MIPS_CP0_TAGHI 29 /* Cache Tag Hi */ 78 #define MIPS_CP0_ERR_EPC 30 /* Error exception PC */ 79 80 /* 81 * CP0 Set 1 Registers (R7000) 82 */ 83 #define MIPS_CP0_S1_CONFIG 16 /* Configuration Register */ 84 #define MIPS_CP0_S1_IPLLO 18 /* Priority level for IRQ [7:0] */ 85 #define MIPS_CP0_S1_IPLHI 19 /* Priority level for IRQ [15:8] */ 86 #define MIPS_CP0_S1_INTCTL 20 /* Interrupt Control */ 87 #define MIPS_CP0_S1_DERRADDR0 26 /* Imprecise Error Address */ 88 #define MIPS_CP0_S1_DERRADDR1 27 /* Imprecise Error Address */ 89 90 /* 91 * CP0 Status Register 92 */ 93 #define MIPS_CP0_STATUS_CU0 0x10000000 94 #define MIPS_CP0_STATUS_CU1 0x20000000 95 #define MIPS_CP0_STATUS_BEV 0x00400000 96 #define MIPS_CP0_STATUS_TS 0x00200000 97 #define MIPS_CP0_STATUS_SR 0x00100000 98 #define MIPS_CP0_STATUS_CH 0x00040000 99 #define MIPS_CP0_STATUS_CE 0x00020000 100 #define MIPS_CP0_STATUS_DE 0x00010000 101 #define MIPS_CP0_STATUS_RP 0x08000000 102 #define MIPS_CP0_STATUS_FR 0x04000000 103 #define MIPS_CP0_STATUS_RE 0x02000000 104 #define MIPS_CP0_STATUS_KX 0x00000080 105 #define MIPS_CP0_STATUS_SX 0x00000040 106 #define MIPS_CP0_STATUS_UX 0x00000020 107 #define MIPS_CP0_STATUS_KSU 0x00000018 108 #define MIPS_CP0_STATUS_ERL 0x00000004 109 #define MIPS_CP0_STATUS_EXL 0x00000002 110 #define MIPS_CP0_STATUS_IE 0x00000001 111 #define MIPS_CP0_STATUS_IMASK7 0x00008000 112 #define MIPS_CP0_STATUS_IMASK6 0x00004000 113 #define MIPS_CP0_STATUS_IMASK5 0x00002000 114 #define MIPS_CP0_STATUS_IMASK4 0x00001000 115 #define MIPS_CP0_STATUS_IMASK3 0x00000800 116 #define MIPS_CP0_STATUS_IMASK2 0x00000400 117 #define MIPS_CP0_STATUS_IMASK1 0x00000200 118 #define MIPS_CP0_STATUS_IMASK0 0x00000100 119 120 #define MIPS_CP0_STATUS_DS_MASK 0x00770000 121 #define MIPS_CP0_STATUS_CU_MASK 0xF0000000 122 #define MIPS_CP0_STATUS_IMASK 0x0000FF00 123 124 /* Addressing mode: Kernel, Supervisor and User */ 125 #define MIPS_CP0_STATUS_KSU_SHIFT 0x03 126 #define MIPS_CP0_STATUS_KSU_MASK 0x03 127 128 #define MIPS_CP0_STATUS_KM 0x00 129 #define MIPS_CP0_STATUS_SM 0x01 130 #define MIPS_CP0_STATUS_UM 0x10 131 132 133 /* 134 * CP0 Cause register 135 */ 136 #define MIPS_CP0_CAUSE_BD_SLOT 0x80000000 137 138 #define MIPS_CP0_CAUSE_MASK 0x0000007C 139 #define MIPS_CP0_CAUSE_CEMASK 0x30000000 140 #define MIPS_CP0_CAUSE_IMASK 0x0000FF00 141 142 #define MIPS_CP0_CAUSE_SHIFT 2 143 #define MIPS_CP0_CAUSE_CESHIFT 28 144 #define MIPS_CP0_CAUSE_ISHIFT 8 145 146 #define MIPS_CP0_CAUSE_INTERRUPT 0 147 #define MIPS_CP0_CAUSE_TLB_MOD 1 148 #define MIPS_CP0_CAUSE_TLB_LOAD 2 149 #define MIPS_CP0_CAUSE_TLB_SAVE 3 150 #define MIPS_CP0_CAUSE_ADDR_LOAD 4 /* ADEL */ 151 #define MIPS_CP0_CAUSE_ADDR_SAVE 5 /* ADES */ 152 #define MIPS_CP0_CAUSE_BUS_INSTR 6 153 #define MIPS_CP0_CAUSE_BUS_DATA 7 154 #define MIPS_CP0_CAUSE_SYSCALL 8 155 #define MIPS_CP0_CAUSE_BP 9 156 #define MIPS_CP0_CAUSE_ILLOP 10 157 #define MIPS_CP0_CAUSE_CP_UNUSABLE 11 158 #define MIPS_CP0_CAUSE_OVFLW 12 159 #define MIPS_CP0_CAUSE_TRAP 13 160 #define MIPS_CP0_CAUSE_VC_INSTR 14 /* Virtual Coherency */ 161 #define MIPS_CP0_CAUSE_FPE 15 162 #define MIPS_CP0_CAUSE_WATCH 23 163 #define MIPS_CP0_CAUSE_VC_DATA 31 /* Virtual Coherency */ 164 165 #define MIPS_CP0_CAUSE_IBIT7 0x00008000 166 #define MIPS_CP0_CAUSE_IBIT6 0x00004000 167 #define MIPS_CP0_CAUSE_IBIT5 0x00002000 168 #define MIPS_CP0_CAUSE_IBIT4 0x00001000 169 #define MIPS_CP0_CAUSE_IBIT3 0x00000800 170 #define MIPS_CP0_CAUSE_IBIT2 0x00000400 171 #define MIPS_CP0_CAUSE_IBIT1 0x00000200 172 #define MIPS_CP0_CAUSE_IBIT0 0x00000100 173 174 /* CP0 Context register */ 175 #define MIPS_CP0_CONTEXT_VPN2_MASK 0xffffe000ULL /* applied to addr */ 176 #define MIPS_CP0_CONTEXT_BADVPN2_MASK 0x7fffffULL 177 #define MIPS_CP0_CONTEXT_BADVPN2_SHIFT 4 178 179 /* CP0 XContext register */ 180 #define MIPS_CP0_XCONTEXT_VPN2_MASK 0xffffffe000ULL 181 #define MIPS_CP0_XCONTEXT_RBADVPN2_MASK 0x1ffffffffULL 182 #define MIPS_CP0_XCONTEXT_BADVPN2_SHIFT 4 183 #define MIPS_CP0_XCONTEXT_R_SHIFT 31 184 185 /* TLB masks and shifts */ 186 #define MIPS_TLB_PAGE_MASK 0x01ffe000ULL 187 #define MIPS_TLB_PAGE_SHIFT 13 188 #define MIPS_TLB_VPN2_MASK_32 0xffffe000ULL 189 #define MIPS_TLB_VPN2_MASK_64 0xc00000ffffffe000ULL 190 #define MIPS_TLB_PFN_MASK 0x3fffffc0ULL 191 #define MIPS_TLB_ASID_MASK 0x000000ff /* "asid" in EntryHi */ 192 #define MIPS_TLB_G_MASK 0x00001000ULL /* "Global" in EntryHi */ 193 #define MIPS_TLB_V_MASK 0x2ULL /* "Valid" in EntryLo */ 194 #define MIPS_TLB_D_MASK 0x4ULL /* "Dirty" in EntryLo */ 195 #define MIPS_TLB_C_MASK 0x38ULL /* Page Coherency Attribute */ 196 #define MIPS_TLB_C_SHIFT 3 197 198 #define MIPS_CP0_LO_G_MASK 0x00000001ULL /* "Global" in Lo0/1 reg */ 199 #define MIPS_CP0_LO_SAFE_MASK 0x3fffffffULL /* Safety mask for Lo reg */ 200 #define MIPS_CP0_HI_SAFE_MASK 0xc00000ffffffe0ffULL /* Same for EntryHi */ 201 202 /* results for TLB lookups */ 203 enum { 204 MIPS_TLB_LOOKUP_OK = 0, /* Entry found */ 205 MIPS_TLB_LOOKUP_INVALID, /* Invalid entry found */ 206 MIPS_TLB_LOOKUP_MISS, /* No matching entry found */ 207 MIPS_TLB_LOOKUP_MOD, /* Read-only */ 208 }; 209 210 /* Exceptions vectors */ 211 enum { 212 MIPS_EXCVECT_RST = 0, /* Soft Reset, Reset, NMI */ 213 MIPS_EXCVECT_TLB_REFILL, /* TLB Refill (32-bit) */ 214 MIPS_EXCVECT_XTLB_REFILL, /* TLB Refill (64-bit) */ 215 MIPS_EXCVECT_CACHE_ERR, /* Cache Error */ 216 MIPS_EXCVECT_INT_IV0, /* Interrupt, IV=0 */ 217 MIPS_EXCVECT_INT_IV1, /* Interrupt, IV=1 */ 218 MIPS_EXCVECT_OTHERS, /* Other exceptions */ 219 }; 220 221 /* MIPS "jr ra" instruction */ 222 #define MIPS_INSN_JR_RA 0x03e00008 223 224 /* Minimum page size: 4 Kb */ 225 #define MIPS_MIN_PAGE_SHIFT 12 226 #define MIPS_MIN_PAGE_SIZE (1 << MIPS_MIN_PAGE_SHIFT) 227 #define MIPS_MIN_PAGE_IMASK (MIPS_MIN_PAGE_SIZE - 1) 228 #define MIPS_MIN_PAGE_MASK 0xfffffffffffff000ULL 229 230 /* Addressing mode: Kernel, Supervisor and User */ 231 #define MIPS_MODE_KERNEL 00 232 233 /* Segments in 32-bit User mode */ 234 #define MIPS_USEG_BASE 0x00000000 235 #define MIPS_USEG_SIZE 0x80000000 236 237 /* Segments in 32-bit Supervisor mode */ 238 #define MIPS_SUSEG_BASE 0x00000000 239 #define MIPS_SUSEG_SIZE 0x80000000 240 #define MIPS_SSEG_BASE 0xc0000000 241 #define MIPS_SSEG_SIZE 0x20000000 242 243 /* Segments in 32-bit Kernel mode */ 244 #define MIPS_KUSEG_BASE 0x00000000 245 #define MIPS_KUSEG_SIZE 0x80000000 246 247 #define MIPS_KSEG0_BASE 0x80000000 248 #define MIPS_KSEG0_SIZE 0x20000000 249 250 #define MIPS_KSEG1_BASE 0xa0000000 251 #define MIPS_KSEG1_SIZE 0x20000000 252 253 #define MIPS_KSSEG_BASE 0xc0000000 254 #define MIPS_KSSEG_SIZE 0x20000000 255 256 #define MIPS_KSEG3_BASE 0xe0000000 257 #define MIPS_KSEG3_SIZE 0x20000000 258 259 /* xkphys mask (36-bit physical address) */ 260 #define MIPS64_XKPHYS_ZONE_MASK 0xF800000000000000ULL 261 #define MIPS64_XKPHYS_PHYS_SIZE (1ULL << 36) 262 #define MIPS64_XKPHYS_PHYS_MASK (MIPS64_XKPHYS_PHYS_SIZE - 1) 263 #define MIPS64_XKPHYS_CCA_SHIFT 59 264 265 /* Initial Program Counter and Stack pointer for ROM */ 266 #define MIPS_ROM_PC 0xffffffffbfc00000ULL 267 #define MIPS_ROM_SP 0xffffffff80004000ULL 268 269 /* Number of GPR (general purpose registers) */ 270 #define MIPS64_GPR_NR 32 271 272 /* Number of registers in CP0 */ 273 #define MIPS64_CP0_REG_NR 32 274 275 /* Number of registers in CP1 */ 276 #define MIPS64_CP1_REG_NR 32 277 278 /* Number of TLB entries */ 279 #define MIPS64_TLB_STD_ENTRIES 48 280 #define MIPS64_TLB_MAX_ENTRIES 64 281 #define MIPS64_TLB_IDX_MASK 0x3f /* 6 bits */ 282 283 /* Enable the 64 TLB entries for R7000 CPU */ 284 #define MIPS64_R7000_TLB64_ENABLE 0x20000000 285 286 /* Number of instructions per page */ 287 #define MIPS_INSN_PER_PAGE (MIPS_MIN_PAGE_SIZE/sizeof(mips_insn_t)) 288 289 /* MIPS CPU Identifiers */ 290 #define MIPS_PRID_R4600 0x00002012 291 #define MIPS_PRID_R4700 0x00002112 292 #define MIPS_PRID_R5000 0x00002312 293 #define MIPS_PRID_R7000 0x00002721 294 #define MIPS_PRID_R527x 0x00002812 295 #define MIPS_PRID_BCM1250 0x00040102 296 297 /* Memory operations */ 298 enum { 299 MIPS_MEMOP_LOOKUP = 0, 300 MIPS_MEMOP_IFETCH, 301 302 MIPS_MEMOP_LB, 303 MIPS_MEMOP_LBU, 304 MIPS_MEMOP_LH, 305 MIPS_MEMOP_LHU, 306 MIPS_MEMOP_LW, 307 MIPS_MEMOP_LWU, 308 MIPS_MEMOP_LD, 309 MIPS_MEMOP_SB, 310 MIPS_MEMOP_SH, 311 MIPS_MEMOP_SW, 312 MIPS_MEMOP_SD, 313 314 MIPS_MEMOP_LWL, 315 MIPS_MEMOP_LWR, 316 MIPS_MEMOP_LDL, 317 MIPS_MEMOP_LDR, 318 MIPS_MEMOP_SWL, 319 MIPS_MEMOP_SWR, 320 MIPS_MEMOP_SDL, 321 MIPS_MEMOP_SDR, 322 323 MIPS_MEMOP_LL, 324 MIPS_MEMOP_SC, 325 326 MIPS_MEMOP_LDC1, 327 MIPS_MEMOP_SDC1, 328 329 MIPS_MEMOP_CACHE, 330 331 MIPS_MEMOP_MAX, 332 }; 333 334 /* Maximum number of breakpoints */ 335 #define MIPS64_MAX_BREAKPOINTS 8 336 337 /* MIPS CPU type */ 338 typedef struct cpu_mips cpu_mips_t; 339 340 /* Memory operation function prototype */ 341 typedef fastcall void (*mips_memop_fn)(cpu_mips_t *cpu,m_uint64_t vaddr, 342 u_int reg); 343 344 /* TLB entry definition */ 345 typedef struct { 346 m_uint64_t mask; 347 m_uint64_t hi; 348 m_uint64_t lo0; 349 m_uint64_t lo1; 350 }tlb_entry_t; 351 352 /* System Coprocessor (CP0) definition */ 353 typedef struct { 354 m_uint64_t reg[MIPS64_CP0_REG_NR]; 355 tlb_entry_t tlb[MIPS64_TLB_MAX_ENTRIES]; 356 357 /* Number of TLB entries */ 358 u_int tlb_entries; 359 360 /* Extensions for R7000 CP0 Set1 */ 361 m_uint32_t ipl_lo,ipl_hi,int_ctl; 362 m_uint32_t derraddr0,derraddr1; 363 }mips_cp0_t; 364 365 /* FPU Coprocessor (CP1) definition */ 366 typedef struct { 367 m_uint64_t reg[MIPS64_CP1_REG_NR]; 368 }mips_cp1_t; 369 370 /* MIPS CPU definition */ 371 struct cpu_mips { 372 /* MTS32/MTS64 caches */ 373 union { 374 mts32_entry_t *mts32_cache; 375 mts64_entry_t *mts64_cache; 376 }mts_u; 377 378 /* Virtual version of CP0 Compare Register */ 379 m_uint32_t cp0_virt_cnt_reg,cp0_virt_cmp_reg; 380 381 /* General Purpose Registers, Pointer Counter, LO/HI, IRQ */ 382 m_uint32_t irq_pending,irq_cause,ll_bit; 383 m_uint64_t pc,gpr[MIPS64_GPR_NR]; 384 m_uint64_t lo,hi,ret_pc; 385 m_uint32_t exec_state; 386 u_int bd_slot; 387 388 /* Virtual address to physical page translation */ 389 fastcall int (*translate)(cpu_mips_t *cpu,m_uint64_t vaddr, 390 m_uint32_t *phys_page); 391 392 /* Memory access functions */ 393 mips_memop_fn mem_op_fn[MIPS_MEMOP_MAX]; 394 395 /* Memory lookup function (to load ELF image,...) and instruction fetch */ 396 void *(*mem_op_lookup)(cpu_mips_t *cpu,m_uint64_t vaddr); 397 void *(*mem_op_ifetch)(cpu_mips_t *cpu,m_uint64_t vaddr); 398 399 /* System coprocessor (CP0) */ 400 mips_cp0_t cp0; 401 402 /* FPU (CP1) */ 403 mips_cp1_t fpu; 404 405 /* Address bus mask for physical addresses */ 406 m_uint64_t addr_bus_mask; 407 408 /* IRQ counters and cause */ 409 m_uint64_t irq_count,timer_irq_count,irq_fp_count; 410 pthread_mutex_t irq_lock; 411 412 /* Current and free lists of translated code blocks */ 413 mips64_jit_tcb_t *tcb_list,*tcb_last,*tcb_free_list; 414 415 /* Executable page area */ 416 void *exec_page_area; 417 size_t exec_page_area_size; 418 size_t exec_page_count,exec_page_alloc; 419 insn_exec_page_t *exec_page_free_list; 420 insn_exec_page_t *exec_page_array; 421 422 /* Idle PC value */ 423 volatile m_uint64_t idle_pc; 424 425 /* Timer IRQs */ 426 volatile u_int timer_irq_pending; 427 u_int timer_irq_freq; 428 u_int timer_irq_check_itv; 429 u_int timer_drift; 430 431 /* IRQ disable flag */ 432 volatile u_int irq_disable; 433 434 /* IRQ idling preemption */ 435 u_int irq_idle_preempt[8]; 436 437 /* Generic CPU instance pointer */ 438 cpu_gen_t *gen; 439 440 /* VM instance */ 441 vm_instance_t *vm; 442 443 /* non-JIT mode instruction counter */ 444 m_uint64_t insn_exec_count; 445 446 /* MTS invalidate/shutdown operations */ 447 void (*mts_invalidate)(cpu_mips_t *cpu); 448 void (*mts_shutdown)(cpu_mips_t *cpu); 449 450 /* MTS cache statistics */ 451 m_uint64_t mts_misses,mts_lookups; 452 453 /* JIT flush method */ 454 u_int jit_flush_method; 455 456 /* Number of compiled pages */ 457 u_int compiled_pages; 458 459 /* Fast memory operations use */ 460 u_int fast_memop; 461 462 /* Direct block jump */ 463 u_int exec_blk_direct_jump; 464 465 /* Address mode (32 or 64 bits) */ 466 u_int addr_mode; 467 468 /* Current exec page (non-JIT) info */ 469 m_uint64_t njm_exec_page; 470 mips_insn_t *njm_exec_ptr; 471 472 /* Performance counter (number of instructions executed by CPU) */ 473 m_uint32_t perf_counter; 474 475 /* Breakpoints */ 476 m_uint64_t breakpoints[MIPS64_MAX_BREAKPOINTS]; 477 u_int breakpoints_enabled; 478 479 /* Symtrace */ 480 int sym_trace; 481 rbtree_tree *sym_tree; 482 483 /* XXX */ 484 cpu_tb_t *current_tb; 485 }; 486 487 #define MIPS64_IRQ_LOCK(cpu) pthread_mutex_lock(&(cpu)->irq_lock) 488 #define MIPS64_IRQ_UNLOCK(cpu) pthread_mutex_unlock(&(cpu)->irq_lock) 489 490 /* Register names */ 491 extern char *mips64_gpr_reg_names[]; 492 493 /* Get cacheability info */ 494 int mips64_cca_cached(m_uint8_t val); 495 496 /* Reset a MIPS64 CPU */ 497 int mips64_reset(cpu_mips_t *cpu); 498 499 /* Initialize a MIPS64 processor */ 500 int mips64_init(cpu_mips_t *cpu); 501 502 /* Delete a MIPS64 processor */ 503 void mips64_delete(cpu_mips_t *cpu); 504 505 /* Set the CPU PRID register */ 506 void mips64_set_prid(cpu_mips_t *cpu,m_uint32_t prid); 507 508 /* Set idle PC value */ 509 void mips64_set_idle_pc(cpu_gen_t *cpu,m_uint64_t addr); 510 511 /* Timer IRQ */ 512 void *mips64_timer_irq_run(cpu_mips_t *cpu); 513 514 /* Determine an "idling" PC */ 515 int mips64_get_idling_pc(cpu_gen_t *cpu); 516 517 /* Set an IRQ (VM IRQ standard routing) */ 518 void mips64_vm_set_irq(vm_instance_t *vm,u_int irq); 519 520 /* Clear an IRQ (VM IRQ standard routing) */ 521 void mips64_vm_clear_irq(vm_instance_t *vm,u_int irq); 522 523 /* Update the IRQ flag */ 524 void mips64_update_irq_flag(cpu_mips_t *cpu); 525 526 /* Generate a general exception */ 527 void mips64_general_exception(cpu_mips_t *cpu,u_int exc_code); 528 529 /* Generate a general exception that updates BadVaddr */ 530 void mips64_gen_exception_badva(cpu_mips_t *cpu,u_int exc_code, 531 m_uint64_t bad_vaddr); 532 533 /* Generate a TLB/XTLB exception */ 534 void mips64_tlb_miss_exception(cpu_mips_t *cpu,u_int exc_code, 535 m_uint64_t bad_vaddr); 536 537 /* Prepare a TLB exception */ 538 void mips64_prepare_tlb_exception(cpu_mips_t *cpu,m_uint64_t vaddr); 539 540 /* 541 * Increment count register and trigger the timer IRQ if value in compare 542 * register is the same. 543 */ 544 fastcall void mips64_exec_inc_cp0_cnt(cpu_mips_t *cpu); 545 546 /* Trigger the Timer IRQ */ 547 fastcall void mips64_trigger_timer_irq(cpu_mips_t *cpu); 548 549 /* Execute ERET instruction */ 550 fastcall void mips64_exec_eret(cpu_mips_t *cpu); 551 552 /* Execute SYSCALL instruction */ 553 fastcall void mips64_exec_syscall(cpu_mips_t *cpu); 554 555 /* Execute BREAK instruction */ 556 fastcall void mips64_exec_break(cpu_mips_t *cpu,u_int code); 557 558 /* Trigger a Trap Exception */ 559 fastcall void mips64_trigger_trap_exception(cpu_mips_t *cpu); 560 561 /* Trigger IRQs */ 562 fastcall void mips64_trigger_irq(cpu_mips_t *cpu); 563 564 /* Set an IRQ */ 565 void mips64_set_irq(cpu_mips_t *cpu,m_uint8_t irq); 566 567 /* Clear an IRQ */ 568 void mips64_clear_irq(cpu_mips_t *cpu,m_uint8_t irq); 569 570 /* DMFC1 */ 571 fastcall void mips64_exec_dmfc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg); 572 573 /* DMTC1 */ 574 fastcall void mips64_exec_dmtc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg); 575 576 /* MFC1 */ 577 fastcall void mips64_exec_mfc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg); 578 579 /* MTC1 */ 580 fastcall void mips64_exec_mtc1(cpu_mips_t *cpu,u_int gp_reg,u_int cp1_reg); 581 582 /* Virtual breakpoint */ 583 fastcall void mips64_run_breakpoint(cpu_mips_t *cpu); 584 585 /* Add a virtual breakpoint */ 586 int mips64_add_breakpoint(cpu_gen_t *cpu,m_uint64_t pc); 587 588 /* Remove a virtual breakpoint */ 589 void mips64_remove_breakpoint(cpu_gen_t *cpu,m_uint64_t pc); 590 591 /* Debugging for register-jump to address 0 */ 592 fastcall void mips64_debug_jr0(cpu_mips_t *cpu); 593 594 /* Set a register */ 595 void mips64_reg_set(cpu_gen_t *cpu,u_int reg,m_uint64_t val); 596 597 /* Dump registers of a MIPS64 processor */ 598 void mips64_dump_regs(cpu_gen_t *cpu); 599 600 /* Dump a memory block */ 601 void mips64_dump_memory(cpu_mips_t *cpu,m_uint64_t vaddr,u_int count); 602 603 /* Dump the stack */ 604 void mips64_dump_stack(cpu_mips_t *cpu,u_int count); 605 606 /* Save the CPU state into a file */ 607 int mips64_save_state(cpu_mips_t *cpu,char *filename); 608 609 /* Load a raw image into the simulated memory */ 610 int mips64_load_raw_image(cpu_mips_t *cpu,char *filename,m_uint64_t vaddr); 611 612 /* Load an ELF image into the simulated memory */ 613 int mips64_load_elf_image(cpu_mips_t *cpu,char *filename,int skip_load, 614 m_uint32_t *entry_point); 615 616 /* Symbol lookup */ 617 struct symbol *mips64_sym_lookup(cpu_mips_t *cpu,m_uint64_t addr); 618 619 /* Insert a new symbol */ 620 struct symbol *mips64_sym_insert(cpu_mips_t *cpu,char *name,m_uint64_t addr); 621 622 /* Create the symbol tree */ 623 int mips64_sym_create_tree(cpu_mips_t *cpu); 624 625 /* Load a symbol file */ 626 int mips64_sym_load_file(cpu_mips_t *cpu,char *filename); 627 628 #endif 629