1 /*
2 * Copyright (C) 2005-2009 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * COMMENT: DEC 21143 "Tulip" ethernet controller
29 *
30 * Implemented from Intel document 278074-001 ("21143 PC/CardBus 10/100Mb/s
31 * Ethernet LAN Controller") and by reverse-engineering OpenBSD and NetBSD
32 * sources.
33 *
34 * This device emulates several sub-components:
35 *
36 * 21143: This is the actual ethernet controller.
37 *
38 * MII: The "physical" network interface.
39 *
40 * SROM: A ROM area containing setting such as which MAC address to
41 * use, and info about the MII.
42 *
43 *
44 * TODO:
45 * o) Handle _writes_ to MII registers.
46 * o) Make it work with modern Linux kernels (as a guest OS).
47 * o) Endianness for descriptors? If necessary.
48 * o) Don't hardcode as many values.
49 */
50
51 #include <stdio.h>
52 #include <stdlib.h>
53 #include <string.h>
54
55 #include "cpu.h"
56 #include "device.h"
57 #include "devices.h"
58 #include "emul.h"
59 #include "interrupt.h"
60 #include "machine.h"
61 #include "memory.h"
62 #include "misc.h"
63 #include "net.h"
64
65 #include "thirdparty/mii.h"
66 #include "thirdparty/tulipreg.h"
67
68
69 /* #define debug fatal */
70
71 #define DEC21143_TICK_SHIFT 16
72
73 #define N_REGS 32
74 #define ROM_WIDTH 6
75
76 struct dec21143_data {
77 /* NIC common data */
78 struct nic_data nic;
79
80 struct interrupt irq;
81 int irq_was_asserted;
82
83 /* PCI: */
84 int pci_little_endian;
85
86 /* SROM emulation: */
87 uint8_t srom[1 << (ROM_WIDTH + 1)];
88 int srom_curbit;
89 int srom_opcode;
90 int srom_opcode_has_started;
91 int srom_addr;
92
93 /* MII PHY emulation: */
94 uint16_t mii_phy_reg[MII_NPHY * 32];
95 int mii_state;
96 int mii_bit;
97 int mii_opcode;
98 int mii_phyaddr;
99 int mii_regaddr;
100
101 /* 21143 registers: */
102 uint32_t reg[N_REGS];
103
104 /* Internal TX state: */
105 uint32_t cur_tx_addr;
106 unsigned char *cur_tx_buf;
107 int cur_tx_buf_len;
108 int tx_idling;
109 int tx_idling_threshold;
110
111 /* Internal RX state: */
112 uint32_t cur_rx_addr;
113 unsigned char *cur_rx_buf;
114 int cur_rx_buf_len;
115 int cur_rx_offset;
116
117 /*
118 * Receive filter information. We keep our own copy of
119 * the promiscuous flag because to implement some of the
120 * filtering modes, we need to tell the network layer that
121 * we want all packets.
122 */
123 int (*drop_packet)(struct net *, struct dec21143_data *);
124 int allmulti;
125 int promiscuous;
126 int filter_needs_promiscuous;
127 uint8_t perfect_filter[6 * TULIP_MAXADDRS];
128
129 /* Only 16 bits are used per filter word. */
130 #define MCHASH_NWORDS (TULIP_MCHASHSIZE / 16)
131 uint32_t hash_filter[MCHASH_NWORDS];
132 int hash_filter_saturated;
133
134 /*
135 * XXX XXX XXX
136 * XXX UGLY HACK. Need a proper way to deal with
137 * XXX different PCI vs. CPU views of RAM.
138 * XXX XXX XXX
139 */
140 uint32_t xxx_dma_to_phys_mask;
141 };
142
143 /* XXX This is an UGLY hack. */
dma_to_phys(const struct dec21143_data * d,uint32_t dma_addr)144 static uint64_t dma_to_phys(const struct dec21143_data *d, uint32_t dma_addr)
145 {
146 return dma_addr & d->xxx_dma_to_phys_mask;
147 }
148
149
load_le32(const uint8_t * buf)150 static inline uint32_t load_le32(const uint8_t *buf)
151 {
152 return buf[0] | ((uint32_t)buf[1] << 8) |
153 ((uint32_t)buf[2] << 16) | ((uint32_t)buf[3] << 24);
154 }
155
156
store_le32(uint8_t * buf,uint32_t val)157 static inline void store_le32(uint8_t *buf, uint32_t val)
158 {
159 buf[0] = (uint8_t)val;
160 buf[1] = (uint8_t)(val >> 8);
161 buf[2] = (uint8_t)(val >> 16);
162 buf[3] = (uint8_t)(val >> 24);
163 }
164
165
166 /* Internal states during MII data stream decode: */
167 #define MII_STATE_RESET 0
168 #define MII_STATE_START_WAIT 1
169 #define MII_STATE_READ_OP 2
170 #define MII_STATE_READ_PHYADDR_REGADDR 3
171 #define MII_STATE_A 4
172 #define MII_STATE_D 5
173 #define MII_STATE_IDLE 6
174
175
176 /*
177 * The 21143 has multiple address matching modes:
178 *
179 * - Perfect Filtering: The chip interprets the descriptor buffer
180 * as a table of 16 MAC addresses that it should match. The
181 * station address and broadcast must be included in the list.
182 *
183 * - Hash Perfect Filtering: The chip interprets the descriptor buffer
184 * as a 512-bit hash table plus one perfect filter match. Multicast
185 * addresses only are matched against the hash table.
186 *
187 * - Inverse Filtering: Like Perfect Filtering, but the table is
188 * addresses NOT to match.
189 *
190 * - Hash-only Filtering: Like Hash Perfect, except without the Perfect.
191 * All addresses are matched against the hash table.
192 *
193 * The mode seleted by the TDCTL descriptor field is reflected in 3
194 * read-only bits in the OPMODE register.
195 *
196 * We implement all 4 (NetBSD, at least, is known to use Perfect and
197 * Hash Perfect on the 21143; it also uses Hash-only on the 21140).
198 */
199
200 #define TDCTL_Tx_FT_MASK (TDCTL_Tx_FT1|TDCTL_Tx_FT0)
201
202 #define dec21143_mchash(addr) \
203 (net_ether_crc32_le((addr), 6) & (TULIP_MCHASHSIZE - 1))
204
dec21143_drop_packet_perfect(struct net * net,struct dec21143_data * d)205 static int dec21143_drop_packet_perfect(struct net *net,
206 struct dec21143_data *d)
207 {
208 int i;
209
210 for (i = 0; i < TULIP_MAXADDRS; i++) {
211 if (net_ether_eq(d->cur_rx_buf, &d->perfect_filter[6 * i])) {
212 /* Match! */
213 return 0;
214 }
215 }
216
217 return 1;
218 }
219
dec21143_drop_packet_hashperfect(struct net * net,struct dec21143_data * d)220 static int dec21143_drop_packet_hashperfect(struct net *net,
221 struct dec21143_data *d)
222 {
223
224 /*
225 * In this mode, we have the network layer match our station
226 * address, and we reflect the true promiscuous status there
227 * as well. This means that if it's not a multicast address,
228 * then it's already been sufficiently matched.
229 */
230 if (! net_ether_multicast(d->cur_rx_buf))
231 return 0;
232
233 /*
234 * Note that the broadcast address is also checked against
235 * the hash table in this mode!
236 */
237
238 const uint32_t hash = dec21143_mchash(d->cur_rx_buf);
239 if (d->hash_filter[hash >> 4] & (1U << (hash & 0xf))) {
240 /* Match! */
241 return 0;
242 }
243
244 return 1;
245 }
246
dec21143_drop_packet_inverse(struct net * net,struct dec21143_data * d)247 static int dec21143_drop_packet_inverse(struct net *net,
248 struct dec21143_data *d)
249 {
250 return !dec21143_drop_packet_perfect(net, d);
251 }
252
dec21143_drop_packet_hashonly(struct net * net,struct dec21143_data * d)253 static int dec21143_drop_packet_hashonly(struct net *net,
254 struct dec21143_data *d)
255 {
256 const uint32_t hash = dec21143_mchash(d->cur_rx_buf);
257 if (d->hash_filter[hash >> 4] & (1U << (hash & 0xf))) {
258 /* Match! */
259 return 0;
260 }
261
262 return 1;
263 }
264
265
266 /*
267 * dec21143_rx_drop_packet():
268 *
269 * Implement the logic to determine if we should drop a packet
270 * before paassing it to the guest. Returns 1 if the packet
271 * was dropped.
272 */
dec21143_rx_drop_packet(struct net * net,struct dec21143_data * d)273 static int dec21143_rx_drop_packet(struct net *net, struct dec21143_data *d)
274 {
275 /* Only implement filtering if using a tap device. */
276 if (net->tapdev == NULL)
277 return 0;
278
279 /*
280 * We might have told the network layer that we're promiscuous
281 * due to the chosen filtering mode, so check the truth here.
282 */
283 if (d->promiscuous)
284 return 0;
285
286 /*
287 * If the guest wants all multicast (either all the bits are
288 * set or the OPMODE_PM bit is set), then check to see if we
289 * can short-circuit the checks.
290 */
291 if (d->allmulti && net_ether_multicast(d->cur_rx_buf))
292 return 0;
293
294 /*
295 * Note that if we haven't gotten a setup packet yet, then
296 * d->drop_packet will be NULL. If this happens, we always
297 * drop. This is akin to the real hardware defaulting to
298 * Perfect filtering mode but not having any valid addresses
299 * in the list to match against.
300 */
301 if (d->drop_packet == NULL || d->drop_packet(net, d)) {
302 /* Not for us; drop the packet. */
303 free(d->cur_rx_buf);
304 d->cur_rx_buf = NULL;
305 d->cur_rx_buf_len = 0;
306 return 1;
307 }
308
309 return 0;
310 }
311
312
313 /*
314 * dec21143_update_rx_mode():
315 *
316 * Update promiscuous / allmulti indicators based on OPMODE
317 * and filter state.
318 */
dec21143_update_rx_mode(struct dec21143_data * d)319 static void dec21143_update_rx_mode(struct dec21143_data *d)
320 {
321 int opmode_pr = (d->reg[CSR_OPMODE / 8] & OPMODE_PR) != 0;
322 int opmode_pm = (d->reg[CSR_OPMODE / 8] & OPMODE_PM) != 0;
323
324 debug("[ dec21143 rx mode: opmode_pr = %d ]\n",
325 opmode_pr);
326 debug("[ dec21143 rx mode: filter_needs_promiscuous = %d ]\n",
327 d->filter_needs_promiscuous);
328 debug("[ dec21143 rx mode: opmode_pm = %d ]\n",
329 opmode_pm);
330 debug("[ dec21143 rx mode: filter_saturated = %d ]\n",
331 d->hash_filter_saturated);
332
333 d->promiscuous = opmode_pr;
334 d->nic.promiscuous_mode =
335 d->promiscuous || d->filter_needs_promiscuous;
336
337 d->allmulti = opmode_pm || d->hash_filter_saturated;
338 }
339
340
341 /*
342 * dec21143_rx():
343 *
344 * Receive a packet. (If there is no current packet, then check for newly
345 * arrived ones. If the current packet couldn't be fully transfered the
346 * last time, then continue on that packet.)
347 */
dec21143_rx(struct cpu * cpu,struct dec21143_data * d)348 int dec21143_rx(struct cpu *cpu, struct dec21143_data *d)
349 {
350 uint32_t addr = d->cur_rx_addr, bufaddr;
351 unsigned char descr[16];
352 uint32_t rdes0, rdes1, rdes2, rdes3;
353 int bufsize, buf1_size, buf2_size, i, writeback_len = 4, to_xfer;
354
355 /* No current packet? Then check for new ones. */
356 while (d->cur_rx_buf == NULL) {
357 /* Nothing available? Then abort. */
358 if (!net_ethernet_rx_avail(d->nic.net, &d->nic))
359 return 0;
360
361 /* Get the next packet into our buffer: */
362 net_ethernet_rx(d->nic.net, &d->nic,
363 &d->cur_rx_buf, &d->cur_rx_buf_len);
364
365 if (dec21143_rx_drop_packet(d->nic.net, d))
366 continue;
367
368 /* Append a 4 byte CRC: */
369 d->cur_rx_buf_len += 4;
370 CHECK_ALLOCATION(d->cur_rx_buf = (unsigned char *) realloc(d->cur_rx_buf,
371 d->cur_rx_buf_len));
372
373 /* Well... the CRC is just zeros, for now. */
374 memset(d->cur_rx_buf + d->cur_rx_buf_len - 4, 0, 4);
375
376 d->cur_rx_offset = 0;
377 }
378
379 /* fatal("{ dec21143_rx: base = 0x%08x }\n", (int)addr); */
380
381 if (!cpu->memory_rw(cpu, cpu->mem, dma_to_phys(d, addr),
382 descr, sizeof(uint32_t), MEM_READ, PHYSICAL | NO_EXCEPTIONS)) {
383 fatal("[ dec21143_rx: memory_rw failed! ]\n");
384 return 0;
385 }
386
387 rdes0 = load_le32(&descr[0]);
388
389 /* Only use descriptors owned by the 21143: */
390 if (!(rdes0 & TDSTAT_OWN)) {
391 d->reg[CSR_STATUS/8] |= STATUS_RU;
392 return 0;
393 }
394
395 if (!cpu->memory_rw(cpu, cpu->mem,
396 dma_to_phys(d, addr + sizeof(uint32_t)),
397 descr + sizeof(uint32_t), sizeof(uint32_t) * 3, MEM_READ,
398 PHYSICAL | NO_EXCEPTIONS)) {
399 fatal("[ dec21143_rx: memory_rw failed! ]\n");
400 return 0;
401 }
402
403 rdes1 = load_le32(&descr[4]);
404 rdes2 = load_le32(&descr[8]);
405 rdes3 = load_le32(&descr[12]);
406
407 buf1_size = rdes1 & TDCTL_SIZE1;
408 buf2_size = (rdes1 & TDCTL_SIZE2) >> TDCTL_SIZE2_SHIFT;
409 bufaddr = buf1_size? rdes2 : rdes3;
410 bufsize = buf1_size? buf1_size : buf2_size;
411
412 d->reg[CSR_STATUS/8] &= ~STATUS_RS;
413
414 if (rdes1 & TDCTL_ER)
415 d->cur_rx_addr = d->reg[CSR_RXLIST / 8];
416 else {
417 if (rdes1 & TDCTL_CH)
418 d->cur_rx_addr = rdes3;
419 else
420 d->cur_rx_addr += 4 * sizeof(uint32_t);
421 }
422
423 debug("{ RX (%llx): 0x%08x 0x%08x 0x%x 0x%x: buf %i bytes at 0x%x }\n",
424 (long long)addr, rdes0, rdes1, rdes2, rdes3, bufsize, (int)bufaddr);
425
426 /* Turn off all status bits, and give up ownership: */
427 rdes0 = 0x00000000;
428
429 to_xfer = d->cur_rx_buf_len - d->cur_rx_offset;
430 if (to_xfer > bufsize)
431 to_xfer = bufsize;
432
433 /* DMA bytes from the packet into emulated physical memory: */
434 for (i=0; i<to_xfer; i++) {
435 cpu->memory_rw(cpu, cpu->mem, dma_to_phys(d, bufaddr + i),
436 d->cur_rx_buf + d->cur_rx_offset + i, 1, MEM_WRITE,
437 PHYSICAL | NO_EXCEPTIONS);
438 /* fatal(" %02x", d->cur_rx_buf[d->cur_rx_offset + i]); */
439 }
440
441 /* Was this the first buffer in a frame? Then mark it as such. */
442 if (d->cur_rx_offset == 0)
443 rdes0 |= TDSTAT_Rx_FS;
444
445 d->cur_rx_offset += to_xfer;
446
447 /* Frame completed? */
448 if (d->cur_rx_offset >= d->cur_rx_buf_len) {
449 rdes0 |= TDSTAT_Rx_LS;
450
451 /* Set the frame length: */
452 rdes0 |= (d->cur_rx_buf_len << 16) & TDSTAT_Rx_FL;
453
454 /* Frame too long? (1518 is max ethernet frame length) */
455 if (d->cur_rx_buf_len > 1518)
456 rdes0 |= TDSTAT_Rx_TL;
457
458 /* Cause a receiver interrupt: */
459 d->reg[CSR_STATUS/8] |= STATUS_RI;
460
461 free(d->cur_rx_buf);
462 d->cur_rx_buf = NULL;
463 d->cur_rx_buf_len = 0;
464 }
465
466 /* Descriptor writeback: */
467 store_le32(&descr[0], rdes0);
468 if (writeback_len > 1) {
469 store_le32(&descr[4], rdes1);
470 store_le32(&descr[8], rdes2);
471 store_le32(&descr[12], rdes3);
472 }
473
474 if (!cpu->memory_rw(cpu, cpu->mem, dma_to_phys(d, addr), descr,
475 sizeof(uint32_t) * writeback_len, MEM_WRITE,
476 PHYSICAL | NO_EXCEPTIONS)) {
477 fatal("[ dec21143_rx: memory_rw failed! ]\n");
478 return 0;
479 }
480
481 return 1;
482 }
483
484
485 /*
486 * dec21143_setup_copy_enaddr():
487 *
488 * Copy an Ethernet address out of the setup packet.
489 */
dec21143_setup_copy_enaddr(uint8_t * enaddr,const uint32_t * setup_packet)490 static void dec21143_setup_copy_enaddr(uint8_t *enaddr,
491 const uint32_t *setup_packet)
492 {
493 int i;
494
495 for (i = 0; i < 3; i++) {
496 enaddr[i*2 ] = (uint8_t)setup_packet[i];
497 enaddr[i*2 + 1] = (uint8_t)(setup_packet[i] >> 8);
498 }
499 }
500
501
502 /*
503 * dec21143_setup_perfect():
504 *
505 * Setup perfect filtering mode.
506 */
dec21143_setup_perfect(struct dec21143_data * d,const uint32_t * setup_packet)507 static void dec21143_setup_perfect(struct dec21143_data *d,
508 const uint32_t *setup_packet)
509 {
510 int i;
511
512 for (i = 0; i < TULIP_MAXADDRS; i++) {
513 dec21143_setup_copy_enaddr(&d->perfect_filter[i * 6],
514 &setup_packet[i * 3]);
515 debug("dec21143 PERFECT[%d] %02x:%02x:%02x:%02x:%02x:%02x\n",
516 i,
517 d->perfect_filter[i*6 + 0],
518 d->perfect_filter[i*6 + 1],
519 d->perfect_filter[i*6 + 2],
520 d->perfect_filter[i*6 + 3],
521 d->perfect_filter[i*6 + 4],
522 d->perfect_filter[i*6 + 5]);
523 }
524
525 d->drop_packet = dec21143_drop_packet_perfect;
526 }
527
528
529 /*
530 * dec21143_setup_hashperfect():
531 *
532 * Setup hash-perfect filtering mode.
533 */
dec21143_setup_hashperfect(struct dec21143_data * d,const uint32_t * setup_packet)534 static void dec21143_setup_hashperfect(struct dec21143_data *d,
535 const uint32_t *setup_packet)
536 {
537 int i;
538
539 debug("dec21143 HASHPERFECT:");
540 for (i = 0; i < MCHASH_NWORDS; i++) {
541 if ((i % 8) == 0)
542 debug("\n\t");
543 debug(" %04x", setup_packet[i]);
544 d->hash_filter[i] = setup_packet[i];
545 d->hash_filter_saturated |= (d->hash_filter[i] == 0xffff);
546 }
547 debug("\n");
548
549 dec21143_setup_copy_enaddr(d->nic.mac_address, &setup_packet[39]);
550 debug("dec21143 HASHPERFECT %02x:%02x:%02x:%02x:%02x:%02x\n",
551 d->nic.mac_address[0],
552 d->nic.mac_address[1],
553 d->nic.mac_address[2],
554 d->nic.mac_address[3],
555 d->nic.mac_address[4],
556 d->nic.mac_address[5]);
557
558 d->filter_needs_promiscuous = 0;
559 d->drop_packet = dec21143_drop_packet_hashperfect;
560 }
561
562
563 /*
564 * dec21143_setup_inverse():
565 *
566 * Setup inverse filtering mode.
567 */
dec21143_setup_inverse(struct dec21143_data * d,const uint32_t * setup_packet)568 static void dec21143_setup_inverse(struct dec21143_data *d,
569 const uint32_t *setup_packet)
570 {
571 dec21143_setup_perfect(d, setup_packet);
572 debug("dec21143 INVERSE ^^^^\n");
573 d->drop_packet = dec21143_drop_packet_inverse;
574 }
575
576
577 /*
578 * dec21143_setup_hashonly():
579 *
580 * Setup hash-only filtering mode.
581 */
dec21143_setup_hashonly(struct dec21143_data * d,const uint32_t * setup_packet)582 static void dec21143_setup_hashonly(struct dec21143_data *d,
583 const uint32_t *setup_packet)
584 {
585 int i;
586
587 debug("dec21143 HASHONLY:");
588 for (i = 0; i < MCHASH_NWORDS; i++) {
589 if ((i % 8) == 0)
590 fatal("\n\t");
591 debug(" %04x", setup_packet[i]);
592 d->hash_filter[i] = setup_packet[i];
593 d->hash_filter_saturated |= (d->hash_filter[i] == 0xffff);
594 }
595 debug("\n");
596
597 d->drop_packet = dec21143_drop_packet_hashonly;
598 }
599
600
601 /*
602 * dec21143_process_setup_packet():
603 *
604 * Process the address filter setup packet.
605 */
dec21143_process_setup_packet(struct cpu * cpu,struct dec21143_data * d,uint32_t tdctl,uint32_t bufaddr)606 static void dec21143_process_setup_packet(struct cpu *cpu,
607 struct dec21143_data *d, uint32_t tdctl, uint32_t bufaddr)
608 {
609 uint32_t setup_packet[TULIP_SETUP_PACKET_LEN / sizeof(uint32_t)];
610 uint8_t *cp = (uint8_t *)setup_packet;
611 uint32_t tmp;
612 int i;
613
614 if (!cpu->memory_rw(cpu, cpu->mem, dma_to_phys(d, bufaddr), cp,
615 TULIP_SETUP_PACKET_LEN, MEM_READ, PHYSICAL | NO_EXCEPTIONS)) {
616 fatal("[ dec21143_process_setup_packet: memory_rw failed! ]\n");
617 return;
618 }
619
620 /* Ensure host order of each word. */
621 for (i = 0; i < TULIP_SETUP_PACKET_LEN; i += sizeof(uint32_t)) {
622 tmp = load_le32(&cp[i]);
623 setup_packet[i / sizeof(uint32_t)] = tmp;
624 }
625
626 /* Defaults. */
627 d->hash_filter_saturated = 0;
628 d->filter_needs_promiscuous = 1;
629
630 d->reg[CSR_OPMODE / 8] &= ~(OPMODE_HP | OPMODE_HO | OPMODE_IF);
631
632 switch (tdctl & TDCTL_Tx_FT_MASK) {
633 case TDCTL_Tx_FT_PERFECT:
634 dec21143_setup_perfect(d, setup_packet);
635 break;
636
637 case TDCTL_Tx_FT_HASH:
638 dec21143_setup_hashperfect(d, setup_packet);
639 d->reg[CSR_OPMODE / 8] |= OPMODE_HP;
640 break;
641
642 case TDCTL_Tx_FT_INVERSE:
643 dec21143_setup_inverse(d, setup_packet);
644 d->reg[CSR_OPMODE / 8] |= OPMODE_IF;
645 break;
646
647 case TDCTL_Tx_FT_HASHONLY:
648 dec21143_setup_hashonly(d, setup_packet);
649 d->reg[CSR_OPMODE / 8] |= OPMODE_HO;
650 break;
651 }
652
653 dec21143_update_rx_mode(d);
654 }
655
656
657 /*
658 * dec21143_tx():
659 *
660 * Transmit a packet, if the guest OS has marked a descriptor as containing
661 * data to transmit.
662 */
dec21143_tx(struct cpu * cpu,struct dec21143_data * d)663 int dec21143_tx(struct cpu *cpu, struct dec21143_data *d)
664 {
665 uint32_t addr = d->cur_tx_addr, bufaddr;
666 unsigned char descr[16];
667 uint32_t tdes0, tdes1, tdes2, tdes3;
668 int bufsize, buf1_size, buf2_size, i;
669
670 if (!cpu->memory_rw(cpu, cpu->mem, dma_to_phys(d, addr), descr,
671 sizeof(uint32_t), MEM_READ, PHYSICAL | NO_EXCEPTIONS)) {
672 fatal("[ dec21143_tx: memory_rw failed! ]\n");
673 return 0;
674 }
675
676 tdes0 = load_le32(&descr[0]);
677
678 /* fatal("{ dec21143_tx: base=0x%08x, tdes0=0x%08x }\n",
679 (int)addr, (int)tdes0); */
680
681 /* Only process packets owned by the 21143: */
682 if (!(tdes0 & TDSTAT_OWN)) {
683 if (d->tx_idling > d->tx_idling_threshold) {
684 d->reg[CSR_STATUS/8] |= STATUS_TU;
685 d->tx_idling = 0;
686 } else
687 d->tx_idling ++;
688 return 0;
689 }
690
691 if (!cpu->memory_rw(cpu, cpu->mem,
692 dma_to_phys(d, addr + sizeof(uint32_t)),
693 descr + sizeof(uint32_t), sizeof(uint32_t) * 3, MEM_READ,
694 PHYSICAL | NO_EXCEPTIONS)) {
695 fatal("[ dec21143_tx: memory_rw failed! ]\n");
696 return 0;
697 }
698
699 tdes1 = load_le32(&descr[4]);
700 tdes2 = load_le32(&descr[8]);
701 tdes3 = load_le32(&descr[12]);
702
703 buf1_size = tdes1 & TDCTL_SIZE1;
704 buf2_size = (tdes1 & TDCTL_SIZE2) >> TDCTL_SIZE2_SHIFT;
705 bufaddr = buf1_size? tdes2 : tdes3;
706 bufsize = buf1_size? buf1_size : buf2_size;
707
708 d->reg[CSR_STATUS/8] &= ~STATUS_TS;
709
710 if (tdes1 & TDCTL_ER)
711 d->cur_tx_addr = d->reg[CSR_TXLIST / 8];
712 else {
713 if (tdes1 & TDCTL_CH)
714 d->cur_tx_addr = tdes3;
715 else
716 d->cur_tx_addr += 4 * sizeof(uint32_t);
717 }
718
719 /*
720 fatal("{ TX (%x): 0x%08x 0x%08x 0x%x 0x%x: buf %i bytes at 0x%x }\n",
721 addr, tdes0, tdes1, tdes2, tdes3, bufsize, bufaddr);
722 */
723
724 /* Assume no error: */
725 tdes0 &= ~ (TDSTAT_Tx_UF | TDSTAT_Tx_EC | TDSTAT_Tx_LC
726 | TDSTAT_Tx_NC | TDSTAT_Tx_LO | TDSTAT_Tx_TO | TDSTAT_ES);
727
728 if (tdes1 & TDCTL_Tx_SET) {
729 /*
730 * Setup Packet.
731 */
732 /* fatal("{ TX: setup packet }\n"); */
733 if (bufsize != TULIP_SETUP_PACKET_LEN)
734 fatal("[ dec21143: setup packet len = %i, should be"
735 " %d! ]\n", (int)bufsize, TULIP_SETUP_PACKET_LEN);
736 else
737 dec21143_process_setup_packet(cpu, d, tdes1, bufaddr);
738 if (tdes1 & TDCTL_Tx_IC)
739 d->reg[CSR_STATUS/8] |= STATUS_TI;
740 /* New descriptor values, according to the docs: */
741 tdes0 = 0x7fffffff; tdes1 = 0xffffffff;
742 tdes2 = 0xffffffff; tdes3 = 0xffffffff;
743 } else {
744 /*
745 * Data Packet.
746 */
747 /* fatal("{ TX: data packet: "); */
748 if (tdes1 & TDCTL_Tx_FS) {
749 /* First segment. Let's allocate a new buffer: */
750 /* fatal("new frame }\n"); */
751
752 CHECK_ALLOCATION(d->cur_tx_buf = (unsigned char *) malloc(bufsize));
753 d->cur_tx_buf_len = 0;
754 } else {
755 /* Not first segment. Increase the length of
756 the current buffer: */
757 /* fatal("continuing last frame }\n"); */
758
759 if (d->cur_tx_buf == NULL)
760 fatal("[ dec21143: WARNING! tx: middle "
761 "segment, but no first segment?! ]\n");
762
763 CHECK_ALLOCATION(d->cur_tx_buf = (unsigned char *) realloc(d->cur_tx_buf,
764 d->cur_tx_buf_len + bufsize));
765 }
766
767 /* "DMA" data from emulated physical memory into the buf: */
768 for (i=0; i<bufsize; i++) {
769 cpu->memory_rw(cpu, cpu->mem,
770 dma_to_phys(d, bufaddr + i),
771 d->cur_tx_buf + d->cur_tx_buf_len + i, 1, MEM_READ,
772 PHYSICAL | NO_EXCEPTIONS);
773 /* fatal(" %02x", d->cur_tx_buf[
774 d->cur_tx_buf_len + i]); */
775 }
776
777 d->cur_tx_buf_len += bufsize;
778
779 /* Last segment? Then actually transmit it: */
780 if (tdes1 & TDCTL_Tx_LS) {
781 /* fatal("{ TX: data frame complete. }\n"); */
782 if (d->nic.net != NULL) {
783 net_ethernet_tx(d->nic.net, &d->nic,
784 d->cur_tx_buf, d->cur_tx_buf_len);
785 } else {
786 static int warn = 0;
787 if (!warn)
788 fatal("[ dec21143: WARNING! Not "
789 "connected to a network! ]\n");
790 warn = 1;
791 }
792
793 free(d->cur_tx_buf);
794 d->cur_tx_buf = NULL;
795 d->cur_tx_buf_len = 0;
796
797 /* Interrupt, if Tx_IC is set: */
798 if (tdes1 & TDCTL_Tx_IC)
799 d->reg[CSR_STATUS/8] |= STATUS_TI;
800 }
801
802 /* We are done with this segment. */
803 tdes0 &= ~TDSTAT_OWN;
804 }
805
806 /* Error summary: */
807 if (tdes0 & (TDSTAT_Tx_UF | TDSTAT_Tx_EC | TDSTAT_Tx_LC
808 | TDSTAT_Tx_NC | TDSTAT_Tx_LO | TDSTAT_Tx_TO))
809 tdes0 |= TDSTAT_ES;
810
811 /* Descriptor writeback: */
812 store_le32(&descr[0], tdes0);
813 store_le32(&descr[4], tdes1);
814 store_le32(&descr[8], tdes2);
815 store_le32(&descr[12], tdes3);
816
817 if (!cpu->memory_rw(cpu, cpu->mem, dma_to_phys(d, addr), descr,
818 sizeof(uint32_t) * 4, MEM_WRITE, PHYSICAL | NO_EXCEPTIONS)) {
819 fatal("[ dec21143_tx: memory_rw failed! ]\n");
820 return 0;
821 }
822
823 return 1;
824 }
825
826
DEVICE_TICK(dec21143)827 DEVICE_TICK(dec21143)
828 {
829 struct dec21143_data *d = (struct dec21143_data *) extra;
830 int asserted;
831
832 if (d->reg[CSR_OPMODE / 8] & OPMODE_ST)
833 while (dec21143_tx(cpu, d))
834 ;
835
836 if (d->reg[CSR_OPMODE / 8] & OPMODE_SR)
837 while (dec21143_rx(cpu, d))
838 ;
839
840 /* Normal and Abnormal interrupt summary: */
841 d->reg[CSR_STATUS / 8] &= ~(STATUS_NIS | STATUS_AIS);
842 if (d->reg[CSR_STATUS / 8] & 0x00004845)
843 d->reg[CSR_STATUS / 8] |= STATUS_NIS;
844 if (d->reg[CSR_STATUS / 8] & 0x0c0037ba)
845 d->reg[CSR_STATUS / 8] |= STATUS_AIS;
846
847 asserted = d->reg[CSR_STATUS / 8] & d->reg[CSR_INTEN / 8] & 0x0c01ffff;
848
849 if (asserted)
850 INTERRUPT_ASSERT(d->irq);
851 if (!asserted && d->irq_was_asserted)
852 INTERRUPT_DEASSERT(d->irq);
853
854 /* Remember assertion flag: */
855 d->irq_was_asserted = asserted;
856 }
857
858
859 /*
860 * mii_access():
861 *
862 * This function handles accesses to the MII. Data streams seem to be of the
863 * following format:
864 *
865 * vv---- starting delimiter
866 * ... 01 xx yyyyy zzzzz a[a] dddddddddddddddd
867 * ^---- I am starting with mii_bit = 0 here
868 *
869 * where x = opcode (10 = read, 01 = write)
870 * y = PHY address
871 * z = register address
872 * a = on Reads: ACK bit (returned, should be 0)
873 * on Writes: _TWO_ dummy bits (10)
874 * d = 16 bits of data (MSB first)
875 */
mii_access(struct cpu * cpu,struct dec21143_data * d,uint32_t oldreg,uint32_t idata)876 static void mii_access(struct cpu *cpu, struct dec21143_data *d,
877 uint32_t oldreg, uint32_t idata)
878 {
879 int obit, ibit = 0;
880 uint16_t tmp;
881
882 /* Only care about data during clock cycles: */
883 if (!(idata & MIIROM_MDC))
884 return;
885
886 if (idata & MIIROM_MDC && oldreg & MIIROM_MDC)
887 return;
888
889 /* fatal("[ mii_access(): 0x%08x ]\n", (int)idata); */
890
891 if (idata & MIIROM_BR) {
892 fatal("[ mii_access(): MIIROM_BR: TODO ]\n");
893 return;
894 }
895
896 obit = idata & MIIROM_MDO? 1 : 0;
897
898 if (d->mii_state >= MII_STATE_START_WAIT &&
899 d->mii_state <= MII_STATE_READ_PHYADDR_REGADDR &&
900 idata & MIIROM_MIIDIR)
901 fatal("[ mii_access(): bad dir? ]\n");
902
903 switch (d->mii_state) {
904
905 case MII_STATE_RESET:
906 /* Wait for a starting delimiter (0 followed by 1). */
907 if (obit)
908 return;
909 if (idata & MIIROM_MIIDIR)
910 return;
911 /* fatal("[ mii_access(): got a 0 delimiter ]\n"); */
912 d->mii_state = MII_STATE_START_WAIT;
913 d->mii_opcode = 0;
914 d->mii_phyaddr = 0;
915 d->mii_regaddr = 0;
916 break;
917
918 case MII_STATE_START_WAIT:
919 /* Wait for a starting delimiter (0 followed by 1). */
920 if (!obit)
921 return;
922 if (idata & MIIROM_MIIDIR) {
923 d->mii_state = MII_STATE_RESET;
924 return;
925 }
926 /* fatal("[ mii_access(): got a 1 delimiter ]\n"); */
927 d->mii_state = MII_STATE_READ_OP;
928 d->mii_bit = 0;
929 break;
930
931 case MII_STATE_READ_OP:
932 if (d->mii_bit == 0) {
933 d->mii_opcode = obit << 1;
934 /* fatal("[ mii_access(): got first opcode bit "
935 "(%i) ]\n", obit); */
936 } else {
937 d->mii_opcode |= obit;
938 /* fatal("[ mii_access(): got opcode = %i ]\n",
939 d->mii_opcode); */
940 d->mii_state = MII_STATE_READ_PHYADDR_REGADDR;
941 }
942 d->mii_bit ++;
943 break;
944
945 case MII_STATE_READ_PHYADDR_REGADDR:
946 /* fatal("[ mii_access(): got phy/reg addr bit nr %i (%i)"
947 " ]\n", d->mii_bit - 2, obit); */
948 if (d->mii_bit <= 6)
949 d->mii_phyaddr |= obit << (6-d->mii_bit);
950 else
951 d->mii_regaddr |= obit << (11-d->mii_bit);
952 d->mii_bit ++;
953 if (d->mii_bit >= 12) {
954 /* fatal("[ mii_access(): phyaddr=0x%x regaddr=0x"
955 "%x ]\n", d->mii_phyaddr, d->mii_regaddr); */
956 d->mii_state = MII_STATE_A;
957 }
958 break;
959
960 case MII_STATE_A:
961 switch (d->mii_opcode) {
962 case MII_COMMAND_WRITE:
963 if (d->mii_bit >= 13)
964 d->mii_state = MII_STATE_D;
965 break;
966 case MII_COMMAND_READ:
967 ibit = 0;
968 d->mii_state = MII_STATE_D;
969 break;
970 default:debug("[ mii_access(): UNIMPLEMENTED MII opcode "
971 "%i (probably just a bug in GXemul's "
972 "MII data stream handling) ]\n", d->mii_opcode);
973 d->mii_state = MII_STATE_RESET;
974 }
975 d->mii_bit ++;
976 break;
977
978 case MII_STATE_D:
979 switch (d->mii_opcode) {
980 case MII_COMMAND_WRITE:
981 if (idata & MIIROM_MIIDIR)
982 fatal("[ mii_access(): write: bad dir? ]\n");
983 obit = obit? (0x8000 >> (d->mii_bit - 14)) : 0;
984 tmp = d->mii_phy_reg[(d->mii_phyaddr << 5) +
985 d->mii_regaddr] | obit;
986 if (d->mii_bit >= 29) {
987 d->mii_state = MII_STATE_IDLE;
988 debug("[ mii_access(): WRITE to phyaddr=0x%x "
989 "regaddr=0x%x: 0x%04x ]\n", d->mii_phyaddr,
990 d->mii_regaddr, tmp);
991 }
992 break;
993 case MII_COMMAND_READ:
994 if (!(idata & MIIROM_MIIDIR))
995 break;
996 tmp = d->mii_phy_reg[(d->mii_phyaddr << 5) +
997 d->mii_regaddr];
998 if (d->mii_bit == 13)
999 debug("[ mii_access(): READ phyaddr=0x%x "
1000 "regaddr=0x%x: 0x%04x ]\n", d->mii_phyaddr,
1001 d->mii_regaddr, tmp);
1002 ibit = tmp & (0x8000 >> (d->mii_bit - 13));
1003 if (d->mii_bit >= 28)
1004 d->mii_state = MII_STATE_IDLE;
1005 break;
1006 }
1007 d->mii_bit ++;
1008 break;
1009
1010 case MII_STATE_IDLE:
1011 d->mii_bit ++;
1012 if (d->mii_bit >= 31)
1013 d->mii_state = MII_STATE_RESET;
1014 break;
1015 }
1016
1017 d->reg[CSR_MIIROM / 8] &= ~MIIROM_MDI;
1018 if (ibit)
1019 d->reg[CSR_MIIROM / 8] |= MIIROM_MDI;
1020 }
1021
1022
1023 /*
1024 * srom_access():
1025 *
1026 * This function handles reads from the Ethernet Address ROM. This is not a
1027 * 100% correct implementation, as it was reverse-engineered from OpenBSD
1028 * sources; it seems to work with OpenBSD, NetBSD, and Linux, though.
1029 *
1030 * Each transfer (if I understood this correctly) is of the following format:
1031 *
1032 * 1xx yyyyyy zzzzzzzzzzzzzzzz
1033 *
1034 * where 1xx = operation (6 means a Read),
1035 * yyyyyy = ROM address
1036 * zz...z = data
1037 *
1038 * y and z are _both_ read and written to at the same time; this enables the
1039 * operating system to sense the number of bits in y (when reading, all y bits
1040 * are 1 except the last one).
1041 */
srom_access(struct cpu * cpu,struct dec21143_data * d,uint32_t oldreg,uint32_t idata)1042 static void srom_access(struct cpu *cpu, struct dec21143_data *d,
1043 uint32_t oldreg, uint32_t idata)
1044 {
1045 int obit, ibit;
1046
1047 /* debug("CSR9 WRITE! 0x%08x\n", (int)idata); */
1048
1049 /* New selection? Then reset internal state. */
1050 if (idata & MIIROM_SR && !(oldreg & MIIROM_SR)) {
1051 d->srom_curbit = 0;
1052 d->srom_opcode = 0;
1053 d->srom_opcode_has_started = 0;
1054 d->srom_addr = 0;
1055 }
1056
1057 /* Only care about data during clock cycles: */
1058 if (!(idata & MIIROM_SROMSK))
1059 return;
1060
1061 obit = 0;
1062 ibit = idata & MIIROM_SROMDI? 1 : 0;
1063 /* debug("CLOCK CYCLE! (bit %i): ", d->srom_curbit); */
1064
1065 /*
1066 * Linux sends more zeroes before starting the actual opcode, than
1067 * OpenBSD and NetBSD. Hopefully this is correct. (I'm just guessing
1068 * that all opcodes should start with a 1, perhaps that's not really
1069 * the case.)
1070 */
1071 if (!ibit && !d->srom_opcode_has_started)
1072 return;
1073
1074 if (d->srom_curbit < 3) {
1075 d->srom_opcode_has_started = 1;
1076 d->srom_opcode <<= 1;
1077 d->srom_opcode |= ibit;
1078 /* debug("opcode input '%i'\n", ibit); */
1079 } else {
1080 switch (d->srom_opcode) {
1081 case TULIP_SROM_OPC_READ:
1082 if (d->srom_curbit < ROM_WIDTH + 3) {
1083 obit = d->srom_curbit < ROM_WIDTH + 2;
1084 d->srom_addr <<= 1;
1085 d->srom_addr |= ibit;
1086 } else {
1087 uint16_t romword = d->srom[d->srom_addr*2]
1088 + (d->srom[d->srom_addr*2+1] << 8);
1089 if (d->srom_curbit == ROM_WIDTH + 3)
1090 debug("[ dec21143: ROM read from offset"
1091 " 0x%03x: 0x%04x ]\n",
1092 d->srom_addr, romword);
1093 obit = romword & (0x8000 >>
1094 (d->srom_curbit - ROM_WIDTH - 3))? 1 : 0;
1095 }
1096 break;
1097 default:fatal("[ dec21243: unimplemented SROM/EEPROM "
1098 "opcode %i ]\n", d->srom_opcode);
1099 }
1100 d->reg[CSR_MIIROM / 8] &= ~MIIROM_SROMDO;
1101 if (obit)
1102 d->reg[CSR_MIIROM / 8] |= MIIROM_SROMDO;
1103 /* debug("input '%i', output '%i'\n", ibit, obit); */
1104 }
1105
1106 d->srom_curbit ++;
1107
1108 /*
1109 * Done opcode + addr + data? Then restart. (At least NetBSD does
1110 * sequential reads without turning selection off and then on.)
1111 */
1112 if (d->srom_curbit >= 3 + ROM_WIDTH + 16) {
1113 d->srom_curbit = 0;
1114 d->srom_opcode = 0;
1115 d->srom_opcode_has_started = 0;
1116 d->srom_addr = 0;
1117 }
1118 }
1119
1120
1121 /*
1122 * dec21143_reset():
1123 *
1124 * Set the 21143 registers, SROM, and MII data to reasonable values.
1125 */
dec21143_reset(struct cpu * cpu,struct dec21143_data * d)1126 static void dec21143_reset(struct cpu *cpu, struct dec21143_data *d)
1127 {
1128
1129 if (d->cur_rx_buf != NULL)
1130 free(d->cur_rx_buf);
1131 if (d->cur_tx_buf != NULL)
1132 free(d->cur_tx_buf);
1133 d->cur_rx_buf = d->cur_tx_buf = NULL;
1134
1135 memset(d->reg, 0, sizeof(uint32_t) * N_REGS);
1136 memset(d->mii_phy_reg, 0, sizeof(d->mii_phy_reg));
1137
1138 /* Register values at reset, according to the manual: */
1139 d->reg[CSR_BUSMODE / 8] = 0xfe000000; /* csr0 */
1140 d->reg[CSR_MIIROM / 8] = 0xfff483ff; /* csr9 */
1141 d->reg[CSR_SIACONN / 8] = 0xffff0000; /* csr13 */
1142 d->reg[CSR_SIATXRX / 8] = 0xffffffff; /* csr14 */
1143 d->reg[CSR_SIAGEN / 8] = 0x8ff00000; /* csr15 */
1144
1145 d->tx_idling_threshold = 10;
1146 d->cur_rx_addr = d->cur_tx_addr = 0;
1147
1148 /* Set the MAC address: */
1149 memcpy(d->nic.mac_address, d->srom + TULIP_ROM_IEEE_NETWORK_ADDRESS, 6);
1150
1151 /* MII PHY initial state: */
1152 d->mii_state = MII_STATE_RESET;
1153
1154 /* PHY #0: */
1155 d->mii_phy_reg[MII_BMSR] = BMSR_100TXFDX | BMSR_10TFDX |
1156 BMSR_ACOMP | BMSR_ANEG | BMSR_LINK;
1157 }
1158
1159
DEVICE_ACCESS(dec21143)1160 DEVICE_ACCESS(dec21143)
1161 {
1162 struct dec21143_data *d = (struct dec21143_data *) extra;
1163 uint32_t idata = 0, odata = 0;
1164 uint32_t oldreg = 0;
1165 int regnr = relative_addr >> 3;
1166
1167 if (writeflag == MEM_WRITE)
1168 idata = (uint32_t)memory_readmax64(cpu, data,
1169 len | d->pci_little_endian);
1170
1171 if ((relative_addr & 7) == 0 && regnr < N_REGS) {
1172 if (writeflag == MEM_READ) {
1173 odata = d->reg[regnr];
1174 } else {
1175 oldreg = d->reg[regnr];
1176 switch (regnr) {
1177 case CSR_STATUS / 8: /* Zero-on-write */
1178 d->reg[regnr] &= ~(idata & 0x0c01ffff);
1179 break;
1180 case CSR_MISSED / 8: /* Read only */
1181 break;
1182 default:d->reg[regnr] = idata;
1183 }
1184 }
1185 } else
1186 fatal("[ dec21143: WARNING! unaligned access (0x%x) ]\n",
1187 (int)relative_addr);
1188
1189 switch (relative_addr) {
1190
1191 case CSR_BUSMODE: /* csr0 */
1192 if (writeflag == MEM_WRITE) {
1193 /* Software reset takes effect immediately. */
1194 if (idata & BUSMODE_SWR) {
1195 dec21143_reset(cpu, d);
1196 idata &= ~BUSMODE_SWR;
1197 }
1198 }
1199 break;
1200
1201 case CSR_TXPOLL: /* csr1 */
1202 if (writeflag == MEM_READ)
1203 fatal("[ dec21143: UNIMPLEMENTED READ from "
1204 "txpoll ]\n");
1205 d->tx_idling = d->tx_idling_threshold;
1206 dev_dec21143_tick(cpu, extra);
1207 break;
1208
1209 case CSR_RXPOLL: /* csr2 */
1210 if (writeflag == MEM_READ)
1211 fatal("[ dec21143: UNIMPLEMENTED READ from "
1212 "rxpoll ]\n");
1213 dev_dec21143_tick(cpu, extra);
1214 break;
1215
1216 case CSR_RXLIST: /* csr3 */
1217 if (writeflag == MEM_WRITE) {
1218 debug("[ dec21143: setting RXLIST to 0x%x ]\n",
1219 (int)idata);
1220 if (idata & 0x3)
1221 fatal("[ dec21143: WARNING! RXLIST not aligned"
1222 "? (0x%llx) ]\n", (long long)idata);
1223 idata &= ~0x3;
1224 d->cur_rx_addr = idata;
1225 }
1226 break;
1227
1228 case CSR_TXLIST: /* csr4 */
1229 if (writeflag == MEM_WRITE) {
1230 debug("[ dec21143: setting TXLIST to 0x%x ]\n",
1231 (int)idata);
1232 if (idata & 0x3)
1233 fatal("[ dec21143: WARNING! TXLIST not aligned"
1234 "? (0x%llx) ]\n", (long long)idata);
1235 idata &= ~0x3;
1236 d->cur_tx_addr = idata;
1237 }
1238 break;
1239
1240 case CSR_STATUS: /* csr5 */
1241 case CSR_INTEN: /* csr7 */
1242 if (writeflag == MEM_WRITE) {
1243 /* Recalculate interrupt assertion. */
1244 dev_dec21143_tick(cpu, extra);
1245 }
1246 break;
1247
1248 case CSR_OPMODE: /* csr6: */
1249 if (writeflag == MEM_WRITE) {
1250 if (idata & 0x02000000) {
1251 /* A must-be-one bit. */
1252 idata &= ~0x02000000;
1253 }
1254 if (idata & OPMODE_ST) {
1255 idata &= ~OPMODE_ST;
1256 } else {
1257 /* Turned off TX? Then idle: */
1258 d->reg[CSR_STATUS/8] |= STATUS_TPS;
1259 }
1260 if (idata & OPMODE_SR) {
1261 idata &= ~OPMODE_SR;
1262 } else {
1263 /* Turned off RX? Then go to stopped state: */
1264 d->reg[CSR_STATUS/8] &= ~STATUS_RS;
1265 }
1266 /* Maintain r/o filter mode bits: */
1267 d->reg[CSR_OPMODE/8] &=
1268 ~(OPMODE_HP | OPMODE_HO | OPMODE_IF);
1269 d->reg[CSR_OPMODE/8] |= oldreg &
1270 (OPMODE_HP | OPMODE_HO | OPMODE_IF);
1271 idata &= ~(OPMODE_HBD | OPMODE_SCR | OPMODE_PCS
1272 | OPMODE_PS | OPMODE_SF | OPMODE_TTM | OPMODE_FD
1273 | OPMODE_IF | OPMODE_HO | OPMODE_HP | OPMODE_PR
1274 | OPMODE_PM);
1275 if (idata & OPMODE_PNIC_IT) {
1276 idata &= ~OPMODE_PNIC_IT;
1277 d->tx_idling = d->tx_idling_threshold;
1278 }
1279 if (idata != 0) {
1280 fatal("[ dec21143: UNIMPLEMENTED OPMODE bits"
1281 ": 0x%08x ]\n", (int)idata);
1282 }
1283 dec21143_update_rx_mode(d);
1284 dev_dec21143_tick(cpu, extra);
1285 }
1286 break;
1287
1288 case CSR_MISSED: /* csr8 */
1289 break;
1290
1291 case CSR_MIIROM: /* csr9 */
1292 if (writeflag == MEM_WRITE) {
1293 if (idata & MIIROM_MDC)
1294 mii_access(cpu, d, oldreg, idata);
1295 else
1296 srom_access(cpu, d, oldreg, idata);
1297 }
1298 break;
1299
1300 case CSR_SIASTAT: /* csr12 */
1301 /* Auto-negotiation status = Good. */
1302 odata = SIASTAT_ANS_FLPGOOD;
1303 break;
1304
1305 case CSR_SIATXRX: /* csr14 */
1306 /* Auto-negotiation Enabled */
1307 odata = SIATXRX_ANE;
1308 break;
1309
1310 case CSR_SIACONN: /* csr13 */
1311 case CSR_SIAGEN: /* csr15 */
1312 /* Don't print warnings for these, for now. */
1313 break;
1314
1315 default:if (writeflag == MEM_READ)
1316 fatal("[ dec21143: read from unimplemented 0x%02x ]\n",
1317 (int)relative_addr);
1318 else
1319 fatal("[ dec21143: write to unimplemented 0x%02x: "
1320 "0x%02x ]\n", (int)relative_addr, (int)idata);
1321 }
1322
1323 if (writeflag == MEM_READ)
1324 memory_writemax64(cpu, data, len | d->pci_little_endian, odata);
1325
1326 return 1;
1327 }
1328
1329
DEVINIT(dec21143)1330 DEVINIT(dec21143)
1331 {
1332 struct dec21143_data *d;
1333 char name2[100];
1334 int leaf;
1335
1336 CHECK_ALLOCATION(d = (struct dec21143_data *) malloc(sizeof(struct dec21143_data)));
1337 memset(d, 0, sizeof(struct dec21143_data));
1338
1339 INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
1340 d->pci_little_endian = devinit->pci_little_endian;
1341
1342 /* XXX XXX XXX */
1343 switch (devinit->machine->machine_type) {
1344 /*
1345 * Footbridge systems -- this is actually configurable by
1346 * system software, but this is the window setting that
1347 * NetBSD uses.
1348 */
1349 case MACHINE_CATS:
1350 case MACHINE_NETWINDER:
1351 d->xxx_dma_to_phys_mask = ~0x20000000;
1352 break;
1353
1354 /*
1355 * V3 Semi PCI bus controller -- this is actually configurable
1356 * by system sofware, but this is the value previously hard-coded
1357 * for all platforms that did not work on Footbridge systems.
1358 */
1359 case MACHINE_ALGOR:
1360 /* FALLTHROUGH */
1361
1362 /* Other known users of dc21143 that came along for the ride. */
1363 case MACHINE_COBALT:
1364 case MACHINE_PMPPC:
1365 case MACHINE_PREP:
1366 case MACHINE_MACPPC:
1367 case MACHINE_MVMEPPC:
1368 d->xxx_dma_to_phys_mask = 0x7fffffff;
1369 break;
1370
1371 default:
1372 fatal("[ dec21143: default DMA mask for unhandled machine %d\n",
1373 devinit->machine->machine_type);
1374 d->xxx_dma_to_phys_mask = 0xffffffff;
1375 }
1376
1377 memset(d->srom, 0, sizeof(d->srom));
1378
1379 /* Version (= 1) and Chip count (= 1): */
1380 d->srom[TULIP_ROM_SROM_FORMAT_VERION] = 1;
1381 d->srom[TULIP_ROM_CHIP_COUNT] = 1;
1382
1383 leaf = 30;
1384 d->srom[TULIP_ROM_CHIPn_DEVICE_NUMBER(0)] = 0;
1385 d->srom[TULIP_ROM_CHIPn_INFO_LEAF_OFFSET(0)] = leaf & 255;
1386 d->srom[TULIP_ROM_CHIPn_INFO_LEAF_OFFSET(0)+1] = leaf >> 8;
1387
1388 d->srom[leaf+TULIP_ROM_IL_SELECT_CONN_TYPE] = 0; /* Not used? */
1389 d->srom[leaf+TULIP_ROM_IL_MEDIA_COUNT] = 2;
1390 leaf += TULIP_ROM_IL_MEDIAn_BLOCK_BASE;
1391
1392 d->srom[leaf] = 7; /* descriptor length */
1393 d->srom[leaf+1] = TULIP_ROM_MB_21142_SIA;
1394 d->srom[leaf+2] = TULIP_ROM_MB_MEDIA_100TX;
1395 /* here comes 4 bytes of GPIO control/data settings */
1396 leaf += d->srom[leaf];
1397
1398 d->srom[leaf] = 15; /* descriptor length */
1399 d->srom[leaf+1] = TULIP_ROM_MB_21142_MII;
1400 d->srom[leaf+2] = 0; /* PHY nr */
1401 d->srom[leaf+3] = 0; /* len of select sequence */
1402 d->srom[leaf+4] = 0; /* len of reset sequence */
1403 /* 5,6, 7,8, 9,10, 11,12, 13,14 = unused by GXemul */
1404 leaf += d->srom[leaf];
1405
1406 net_generate_unique_mac(devinit->machine, d->nic.mac_address);
1407 memcpy(d->srom + TULIP_ROM_IEEE_NETWORK_ADDRESS, d->nic.mac_address, 6);
1408 net_add_nic(devinit->machine->emul->net, &d->nic);
1409
1410 dec21143_reset(devinit->machine->cpus[0], d);
1411
1412 snprintf(name2, sizeof(name2), "%s [%02x:%02x:%02x:%02x:%02x:%02x]",
1413 devinit->name, d->nic.mac_address[0], d->nic.mac_address[1],
1414 d->nic.mac_address[2], d->nic.mac_address[3],
1415 d->nic.mac_address[4], d->nic.mac_address[5]);
1416
1417 memory_device_register(devinit->machine->memory, name2,
1418 devinit->addr, 0x100, dev_dec21143_access, d, DM_DEFAULT, NULL);
1419
1420 machine_add_tickfunction(devinit->machine,
1421 dev_dec21143_tick, d, DEC21143_TICK_SHIFT);
1422
1423 /*
1424 * NetBSD/cats uses memory accesses, OpenBSD/cats uses I/O registers.
1425 * Let's make a mirror from the memory range to the I/O range:
1426 */
1427 dev_ram_init(devinit->machine, devinit->addr2, 0x100, DEV_RAM_MIRROR
1428 | DEV_RAM_MIGHT_POINT_TO_DEVICES, devinit->addr);
1429
1430 return 1;
1431 }
1432
1433