1 // license:BSD-3-Clause 2 // copyright-holders:Aaron Giles 3 /*************************************************************************** 4 5 mips3com.h 6 7 Common MIPS III/IV definitions and functions 8 9 ***************************************************************************/ 10 #ifndef MAME_CPU_MIPS_MIPS3COM_H 11 #define MAME_CPU_MIPS_MIPS3COM_H 12 13 #pragma once 14 15 #include "mips3.h" 16 17 18 /*************************************************************************** 19 DEBUGGING 20 ***************************************************************************/ 21 22 #define PRINTF_TLB (0) 23 #define USE_ABI_REG_NAMES (1) 24 25 #define DISABLE_FAST_REGISTERS (0) 26 #define SINGLE_INSTRUCTION_MODE (0) 27 28 #define PRINTF_EXCEPTIONS (0) 29 #define PRINTF_MMU (0) 30 31 #define PROBE_ADDRESS ~0 32 33 #define LL_BREAK (0) 34 35 /*************************************************************************** 36 CONSTANTS 37 ***************************************************************************/ 38 39 /* map variables */ 40 #define MAPVAR_PC uml::M0 41 #define MAPVAR_CYCLES uml::M1 42 43 /* modes */ 44 #define MODE_KERNEL 0 45 #define MODE_SUPER 1 46 #define MODE_USER 2 47 48 /* compilation boundaries -- how far back/forward does the analysis extend? */ 49 #define COMPILE_BACKWARDS_BYTES 128 50 #define COMPILE_FORWARDS_BYTES 512 51 #define COMPILE_MAX_INSTRUCTIONS ((COMPILE_BACKWARDS_BYTES/4) + (COMPILE_FORWARDS_BYTES/4)) 52 #define COMPILE_MAX_SEQUENCE 64 53 54 /* exit codes */ 55 #define EXECUTE_OUT_OF_CYCLES 0 56 #define EXECUTE_MISSING_CODE 1 57 #define EXECUTE_UNMAPPED_CODE 2 58 #define EXECUTE_RESET_CACHE 3 59 60 61 62 #define LOPTR(x) ((uint32_t *)(x) + NATIVE_ENDIAN_VALUE_LE_BE(0,1)) 63 64 65 /*************************************************************************** 66 CONSTANTS 67 ***************************************************************************/ 68 69 /* core parameters */ 70 #define MIPS3_MIN_PAGE_SHIFT 12 71 #define MIPS3_MIN_PAGE_SIZE (1 << MIPS3_MIN_PAGE_SHIFT) 72 #define MIPS3_MIN_PAGE_MASK (MIPS3_MIN_PAGE_SIZE - 1) 73 #define MIPS3_MAX_PADDR_SHIFT 32 74 75 /* cycle parameters */ 76 #define MIPS3_COUNT_READ_CYCLES 1 77 #define MIPS3_CAUSE_READ_CYCLES 1 78 79 /* TLB bits */ 80 #define TLB_GLOBAL 0x01 81 #define TLB_VALID 0x02 82 #define TLB_DIRTY 0x04 83 #define TLB_PRESENT 0x08 84 85 /* COP0 registers */ 86 #define COP0_Index 0 87 #define COP0_Random 1 88 #define COP0_EntryLo 2 89 #define COP0_EntryLo0 2 90 #define COP0_EntryLo1 3 91 #define COP0_Context 4 92 #define COP0_PageMask 5 93 #define COP0_Wired 6 94 #define COP0_BadVAddr 8 95 #define COP0_Count 9 96 #define COP0_EntryHi 10 97 #define COP0_Compare 11 98 #define COP0_Status 12 99 #define COP0_Cause 13 100 #define COP0_EPC 14 101 #define COP0_PRId 15 102 #define COP0_Config 16 103 #define COP0_LLAddr 17 104 #define COP0_XContext 20 105 #define COP0_ECC 26 106 #define COP0_CacheErr 27 107 #define COP0_TagLo 28 108 #define COP0_TagHi 29 109 #define COP0_ErrorPC 30 110 111 /* Status register bits */ 112 #define SR_IE 0x00000001 113 #define SR_EXL 0x00000002 114 #define SR_ERL 0x00000004 115 #define SR_KSU_MASK 0x00000018 116 #define SR_KSU_KERNEL 0x00000000 117 #define SR_KSU_SUPERVISOR 0x00000008 118 #define SR_KSU_USER 0x00000010 119 #define SR_IMSW0 0x00000100 120 #define SR_IMSW1 0x00000200 121 #define SR_IMEX0 0x00000400 122 #define SR_IMEX1 0x00000800 123 #define SR_IMEX2 0x00001000 124 #define SR_IMEX3 0x00002000 125 #define SR_IMEX4 0x00004000 126 #define SR_IMEX5 0x00008000 127 #define SR_DE 0x00010000 128 #define SR_EIE 0x00010000 /* R5900/EE only, Enable IE bit */ 129 #define SR_CE 0x00020000 130 #define SR_EDI 0x00020000 /* R5900/EE only, EI/DI instruction enable */ 131 #define SR_CH 0x00040000 132 #define SR_SR 0x00100000 133 #define SR_TS 0x00200000 134 #define SR_BEV 0x00400000 135 #define SR_ITS 0x01000000 /* VR4300 only, Application Note doesn't give purpose */ 136 #define SR_RE 0x02000000 137 #define SR_FR 0x04000000 138 #define SR_RP 0x08000000 139 #define SR_COP0 0x10000000 140 #define SR_COP1 0x20000000 141 #define SR_COP2 0x40000000 142 #define SR_COP3 0x80000000 143 144 /* exception types */ 145 #define EXCEPTION_INTERRUPT 0 146 #define EXCEPTION_TLBMOD 1 147 #define EXCEPTION_TLBLOAD 2 148 #define EXCEPTION_TLBSTORE 3 149 #define EXCEPTION_ADDRLOAD 4 150 #define EXCEPTION_ADDRSTORE 5 151 #define EXCEPTION_BUSINST 6 152 #define EXCEPTION_BUSDATA 7 153 #define EXCEPTION_SYSCALL 8 154 #define EXCEPTION_BREAK 9 155 #define EXCEPTION_INVALIDOP 10 156 #define EXCEPTION_BADCOP 11 157 #define EXCEPTION_OVERFLOW 12 158 #define EXCEPTION_TRAP 13 159 #define EXCEPTION_FPE 15 160 #define EXCEPTION_TLBLOAD_FILL 16 161 #define EXCEPTION_TLBSTORE_FILL 17 162 #define EXCEPTION_COUNT 18 163 164 #define FCR31_FLAGS 2 // FLAGS start bit 165 #define FCR31_ENABLE 7 // Enable start bit 166 #define FCR31_CAUSE 12 // Cause start bit 167 #define FPE_DIV0 3 // Divide by zero bit index 168 169 170 /*************************************************************************** 171 HELPER MACROS 172 ***************************************************************************/ 173 174 #define REG_LO 32 175 #define REG_HI 33 176 177 #define RSREG ((op >> 21) & 31) 178 #define RTREG ((op >> 16) & 31) 179 #define RDREG ((op >> 11) & 31) 180 #define SHIFT ((op >> 6) & 31) 181 182 #define FRREG ((op >> 21) & 31) 183 #define FTREG ((op >> 16) & 31) 184 #define FSREG ((op >> 11) & 31) 185 #define FDREG ((op >> 6) & 31) 186 187 #define IS_SINGLE(o) (((o) & (1 << 21)) == 0) 188 #define IS_DOUBLE(o) (((o) & (1 << 21)) != 0) 189 #define IS_FLOAT(o) (((o) & (1 << 23)) == 0) 190 #define IS_INTEGRAL(o) (((o) & (1 << 23)) != 0) 191 192 #define SIMMVAL ((int16_t)op) 193 #define UIMMVAL ((uint16_t)op) 194 #define LIMMVAL (op & 0x03ffffff) 195 196 #define CACHE_TYPE ((op >> 16) & 3) 197 #define CACHE_OP ((op >> 18) & 7) 198 199 #endif // MAME_CPU_MIPS_MIPS3COM_H 200