1 // license:BSD-3-Clause 2 // copyright-holders: Joakim Larsson Edström 3 /*************************************************************************** 4 5 Motorola 6844 emulation 6 7 **************************************************************************** 8 _____ _____ 9 VSS 1 |* \_/ | 40 E 10 *CS / Tx AKBW 2 | | 39 *RESET 11 R / *W 3 | | 38 DGRNT 12 A0 4 | | 37 *DRQ1 13 A1 5 | | 36 *DRQ2 14 A2 6 | | 35 Tx AKA 15 A3 7 | | 34 *TX STB 16 A4 8 | | 33 *IRQ / *DEND 17 A5 9 | | 32 Tx RQ0 18 A6 10 | MC6844 | 31 Tx RQ1 19 A7 11 | | 30 Tx RQ2 20 A8 12 | | 29 Tx RQ3 21 A9 13 | | 28 D0 22 A10 14 | | 27 D1 23 A11 15 | | 26 D2 24 A12 16 | | 25 D3 25 A13 17 | | 24 D4 26 A14 18 | | 23 D5 27 A15 19 | | 22 D6 28 VCC 20 |_____________| 21 D7 29 30 ***************************************************************************/ 31 32 #ifndef MAME_MACHINE_MC6844_H 33 #define MAME_MACHINE_MC6844_H 34 35 #pragma once 36 37 //************************************************************************** 38 // INTERFACE CONFIGURATION MACROS 39 //************************************************************************** 40 41 //************************************************************************** 42 // TYPE DEFINITIONS 43 //************************************************************************** 44 45 // ======================> mc6844_device 46 47 class mc6844_device : public device_t, public device_execute_interface 48 { 49 public: 50 // construction/destruction 51 mc6844_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); 52 out_int_callback()53 auto out_int_callback() { return m_out_int_cb.bind(); } out_txak_callback()54 auto out_txak_callback() { return m_out_txak_cb.bind(); } out_drq1_callback()55 auto out_drq1_callback() { return m_out_drq1_cb.bind(); } out_drq2_callback()56 auto out_drq2_callback() { return m_out_drq2_cb.bind(); } in_memr_callback()57 auto in_memr_callback() { return m_in_memr_cb.bind(); } out_memw_callback()58 auto out_memw_callback() { return m_out_memw_cb.bind(); } 59 60 // I/O operations 61 void write(offs_t offset, uint8_t data); 62 uint8_t read(offs_t offset); in_ior_callback()63 template <unsigned CH> auto in_ior_callback() { return m_in_ior_cb[CH].bind(); } out_iow_callback()64 template <unsigned CH> auto out_iow_callback() { return m_out_iow_cb[CH].bind(); } 65 DECLARE_WRITE_LINE_MEMBER(dreq_w)66 template <unsigned CH> DECLARE_WRITE_LINE_MEMBER( dreq_w ) { dma_request(CH, state); } 67 DECLARE_WRITE_LINE_MEMBER(dgrnt_w)68 DECLARE_WRITE_LINE_MEMBER( dgrnt_w ){ m_dgrnt = state; trigger(1); } 69 70 protected: 71 // device-level overrides 72 //virtual void device_validity_check(validity_checker &valid) const override; 73 virtual void device_resolve_objects() override; 74 virtual void device_start() override; 75 virtual void device_reset() override; 76 virtual void execute_run() override; 77 78 devcb_write_line m_out_int_cb; 79 devcb_write8 m_out_txak_cb; 80 devcb_write_line m_out_drq1_cb; 81 devcb_write_line m_out_drq2_cb; 82 devcb_read8 m_in_memr_cb; 83 devcb_write8 m_out_memw_cb; 84 devcb_read8::array<4> m_in_ior_cb; 85 devcb_write8::array<4> m_out_iow_cb; 86 87 /* channel_data structure holds info about each 6844 DMA channel */ 88 struct m6844_channel_data 89 { 90 int active; 91 int address; 92 int counter; 93 // Channel control register. 94 // bit 0: Read / Write mode 95 // bit 1: Mode control B 96 // bit 2: Mode control A 97 // bit 3: Address up (0) / down (1). 98 // bit 4: Not used 99 // bit 5: Not used 100 // bit 6: Busy / Ready. Read only. Set when request 101 // made. Cleared when transfer completed. 102 // bit 7: DMA end flag. Read only? Set when transfer 103 // completed. Cleared when control register 104 // read. Sets IRQ. 105 // Mode control A,B: 0,0 Mode2; 0,1 Mode 3; 1,0 Mode 0; 106 // 1,1 Undefined. 107 uint8_t control; 108 int start_address; 109 int start_counter; 110 }; 111 112 /* 6844 description */ 113 m6844_channel_data m_m6844_channel[4]; 114 uint8_t m_m6844_priority; 115 // Interrupt control register. 116 // Bit 0-3: channel interrupt enable, 1 enabled, 0 masked. 117 // Bit 4-6: unused 118 // Bit 7: Read only. Set to 1 when IRQ asserted. Clear when the 119 // control register associated with the channel that caused the 120 // interrut is read. 121 uint8_t m_m6844_interrupt; 122 uint8_t m_m6844_chain; 123 void m6844_update_interrupt(); 124 125 // State machine 126 enum { 127 STATE_SI, 128 STATE_S0, 129 STATE_S1, 130 STATE_S2 131 }; 132 133 int m_state; 134 int m_icount; 135 int m_current_channel; 136 int m_last_channel; 137 138 // input states 139 bool m_dgrnt; 140 bool m_dreq[4]; 141 private: 142 void dma_request(int channel, int state); 143 }; 144 145 // device type definition 146 DECLARE_DEVICE_TYPE(MC6844, mc6844_device) 147 148 #endif // MAME_MACHINE_MC6844_H 149