1 // license:BSD-3-Clause
2 // copyright-holders:Philip Bennett
3 /***************************************************************************
4
5 Magic the Gathering: Armageddon
6
7 preliminary driver by Phil Bennett
8
9
10 PCB Information (needs tidying:)
11
12
13 TOP Board
14 .20u 27c4001 stickered U20
15 #1537 V1.0 a 1 was hadwritten over the 0
16
17 .u7 stamped (c) 1997
18 ACCLAIM COINOP
19 ARMAGEDDON
20 SND3 P/N 1605
21 9806 D
22
23
24 .u8 stamped (c) 1997 11/25/97
25 ACCLAIM COINOP
26 ARMAGEDDON
27 1534 SND0
28 9752 D
29
30 .u13 stamped (c) 1997 11/25/97
31 ACCLAIM COINOP
32 ARMAGEDDON
33 1536 SND2
34 9752 D
35
36 .u14 stamped (c) 1997 11/25/97
37 ACCLAIM COINOP
38 ARMAGEDDON
39 1535 SND1
40 9752 D
41
42 Analog devices ADSP 2181
43 Xilinx XC5202
44 dt71256 x2
45 Analog Devices AD1866R
46
47 Bottom board
48 .u32 27c801 stickered 4
49 .u33 27c801 stickered 3
50 .u34 27c801 stickered 2
51 .u35 27c801 stickered 1
52 .u58 AT17C128 stickered CC3E
53 .u66 GAL16V8D
54
55 Xilinx XC4005E
56 Xilinx XC95108 stickered ACCLAIM COIN-OP
57 CSC2_10.JED
58 B710/0B84
59 U40 p/N 1611
60
61 3dFX 500-0003-03 x2
62 BF1684.1
63 TI TVP3409
64 V53C16258HK40 x24
65 V53C511816500K60 x4
66
67 U38 and U97 on main board 3DFX
68 500-0004-02
69 BF2733.1 TMU
70 9748 20001
71 TAIWAN 1001
72
73 U4 on daughter board Zoran ZR36050PQC
74 -29.5
75 85 GF7B9726E
76
77 U11 on main board Removed heatsink, Couldn't see anything...
78
79
80 U71 on main board Galileo
81 GT-64010A-B-0
82 BB8018.1
83 TAIWAN
84 14.31818 Oscillator by the TI part
85 50.0000 Oscillator by EPROMS
86 33.0000 Oscillator by the V53C511816500K60
87 KM622560LG-7 by Battery
88
89 Bottom daughter board
90 All read as 29F800B
91 .u9 stamped (c) 1997
92 ACCLAIM COINOP
93 ARMAGEDDON S0
94 1514 11/25/97
95 9803 D
96
97
98 .u10 stamped (c) 1997
99 ACCLAIM COINOP
100 ARMAGEDDON S1
101 1515 11/25/97
102 9803 D
103
104 .u11 stamped (c) 1997
105 ACCLAIM COINOP
106 ARMAGEDDON S3
107 1517 11/25/97
108 9803 D
109
110 .u12 stamped (c) 1997
111 ACCLAIM COINOP
112 ARMAGEDDON S2
113 1516 11/25/97
114 9803 D
115
116 .u20 stamped (c) 1997
117 ACCLAIM COINOP
118 ARMAGEDDON K0
119 1543 11/25/97
120 9752 D
121
122 Xilinx XC4010E
123 Zoran ZR36120PQC
124 Zoran ZR36016PQC
125 Xilinx XC3120A
126 DT72811
127 DT71256 x2
128 DT72271
129 29.500000 osciallator by ZR36120PQC
130 Medium size chip with heat sink on it
131
132 ***************************************************************************/
133
134 #include "emu.h"
135 #include "cpu/adsp2100/adsp2100.h"
136 #include "cpu/mips/mips3.h"
137 #include "machine/lpci.h"
138 #include "sound/dmadac.h"
139 #include "video/voodoo.h"
140 #include "screen.h"
141 #include "speaker.h"
142
143
144 /* TODO: Two 3Dfx Voodoo chipsets are used in SLI configuration */
145 // #define USE_TWO_3DFX
146
147 class magictg_state : public driver_device
148 {
149 public:
magictg_state(const machine_config & mconfig,device_type type,const char * tag)150 magictg_state(const machine_config &mconfig, device_type type, const char *tag)
151 : driver_device(mconfig, type, tag)
152 , m_mips(*this, "mips")
153 , m_adsp(*this, "adsp")
154 , m_pci(*this, "pcibus")
155 , m_adsp_pram(*this, "adsp_pram")
156 , m_voodoo(*this, "voodoo_%u", 0U)
157 { }
158
159 void magictg(machine_config &config);
160
161 private:
162 required_device<mips3_device> m_mips;
163 required_device<adsp2181_device> m_adsp;
164 required_device<pci_bus_legacy_device> m_pci;
165
166
167 /* ASIC */
168 struct
169 {
170 uint32_t src_addr;
171 uint32_t dst_addr;
172 uint32_t ctrl;
173 uint32_t count;
174 } m_dma_ch[3];
175
176
177 /* ADSP-2181 */
178 required_shared_ptr<uint32_t> m_adsp_pram;
179
180 struct
181 {
182 uint16_t bdma_internal_addr;
183 uint16_t bdma_external_addr;
184 uint16_t bdma_control;
185 uint16_t bdma_word_count;
186 } m_adsp_regs;
187
188
189 /* 3Dfx Voodoo */
190 required_device_array<voodoo_device, 2> m_voodoo;
191
192 struct
193 {
194 /* PCI */
195 uint32_t command;
196 uint32_t base_addr;
197
198 uint32_t init_enable;
199 } m_voodoo_pci_regs[2];
200
201
202 struct
203 {
204 /* PCI */
205 uint32_t command;
206 uint32_t base_addr;
207
208 /* Memory-mapped */
209 uint32_t as_regs[19];
210 } m_zr36120;
211
212
213 uint32_t zr36120_r(offs_t offset);
214 void zr36120_w(offs_t offset, uint32_t data);
215
216 uint32_t f0_r(offs_t offset, uint32_t mem_mask = ~0);
217 void f0_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
218
219 uint32_t unk_r();
220 uint32_t unk2_r();
221
222 void serial_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
223
224 uint32_t adsp_idma_data_r(offs_t offset, uint32_t mem_mask = ~0);
225 void adsp_idma_data_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
226 void adsp_idma_addr_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
227
228 uint32_t adsp_status_r();
229 uint16_t adsp_control_r(offs_t offset);
230 void adsp_control_w(offs_t offset, uint16_t data);
231
232 void zr36120_reset();
233
234 void adsp_data_map(address_map &map);
235 void adsp_io_map(address_map &map);
236 void adsp_program_map(address_map &map);
237 void magictg_map(address_map &map);
238 protected:
239 virtual void machine_start() override;
240 virtual void machine_reset() override;
241 virtual void video_start() override;
242
243 uint32_t pci_dev0_r(int function, int reg, uint32_t mem_mask);
244 void pci_dev0_w(int function, int reg, uint32_t data, uint32_t mem_mask);
245 uint32_t voodoo_0_pci_r(int function, int reg, uint32_t mem_mask);
246 void voodoo_0_pci_w(int function, int reg, uint32_t data, uint32_t mem_mask);
247 #if defined(USE_TWO_3DFX)
248 uint32_t voodoo_1_pci_r(int function, int reg, uint32_t mem_mask);
249 void voodoo_1_pci_w(int function, int reg, uint32_t data, uint32_t mem_mask);
250 #endif
251 uint32_t zr36120_pci_r(int function, int reg, uint32_t mem_mask);
252 void zr36120_pci_w(int function, int reg, uint32_t data, uint32_t mem_mask);
253 public:
254 uint32_t screen_update_magictg(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
255 };
256
257
258 /*************************************
259 *
260 * Machine initialization
261 *
262 *************************************/
263
machine_start()264 void magictg_state::machine_start()
265 {
266 }
267
268
machine_reset()269 void magictg_state::machine_reset()
270 {
271 uint8_t *adsp_boot = (uint8_t*)memregion("adsp")->base();
272
273 zr36120_reset();
274
275 /* Load 32 program words (96 bytes) via BDMA */
276 for (int i = 0; i < 32; i ++)
277 {
278 uint32_t word;
279
280 word = adsp_boot[i*3 + 0] << 16;
281 word |= adsp_boot[i*3 + 1] << 8;
282 word |= adsp_boot[i*3 + 2];
283
284 m_adsp_pram[i] = word;
285 }
286 }
287
288
289 /*************************************
290 *
291 * Video
292 *
293 *************************************/
294
video_start()295 void magictg_state::video_start()
296 {
297 }
298
screen_update_magictg(screen_device & screen,bitmap_rgb32 & bitmap,const rectangle & cliprect)299 uint32_t magictg_state::screen_update_magictg(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
300 {
301 return m_voodoo[0]->voodoo_update(bitmap, cliprect) ? 0 : UPDATE_HAS_NOT_CHANGED;
302 }
303
304
305 /*************************************
306 *
307 * 3Dfx Voodoo
308 *
309 *************************************/
310
pci_dev0_r(int function,int reg,uint32_t mem_mask)311 uint32_t magictg_state::pci_dev0_r(int function, int reg, uint32_t mem_mask)
312 {
313 logerror("PCI[0] READ: %x\n", reg);
314 return 0x00000000; // TODO
315 }
316
pci_dev0_w(int function,int reg,uint32_t data,uint32_t mem_mask)317 void magictg_state::pci_dev0_w(int function, int reg, uint32_t data, uint32_t mem_mask)
318 {
319 }
320
321
voodoo_0_pci_r(int function,int reg,uint32_t mem_mask)322 uint32_t magictg_state::voodoo_0_pci_r(int function, int reg, uint32_t mem_mask)
323 {
324 uint32_t val = 0;
325
326 switch (reg)
327 {
328 case 0:
329 val = 0x0001121a;
330 break;
331 case 0x10:
332 val = m_voodoo_pci_regs[0].base_addr;
333 break;
334 case 0x40:
335 val = m_voodoo_pci_regs[0].init_enable;
336 break;
337 default:
338 logerror("Voodoo[0] PCI R: %x\n", reg);
339 }
340 return val;
341 }
342
voodoo_0_pci_w(int function,int reg,uint32_t data,uint32_t mem_mask)343 void magictg_state::voodoo_0_pci_w(int function, int reg, uint32_t data, uint32_t mem_mask)
344 {
345 switch (reg)
346 {
347 case 0x04:
348 m_voodoo_pci_regs[0].command = data & 0x3;
349 break;
350 case 0x10:
351 if (data == 0xffffffff)
352 m_voodoo_pci_regs[0].base_addr = 0xff000000;
353 else
354 m_voodoo_pci_regs[0].base_addr = data;
355 break;
356 case 0x40:
357 m_voodoo_pci_regs[0].init_enable = data;
358 m_voodoo[0]->voodoo_set_init_enable(data);
359 break;
360
361 default:
362 logerror("Voodoo [%x]: %x\n", reg, data);
363 }
364 }
365
366 #if defined(USE_TWO_3DFX)
voodoo_1_pci_r(int function,int reg,uint32_t mem_mask)367 uint32_t magictg_state::voodoo_1_pci_r(int function, int reg, uint32_t mem_mask)
368 {
369 uint32_t val = 0;
370
371 switch (reg)
372 {
373 case 0:
374 val = 0x0001121a;
375 break;
376 case 0x10:
377 val = m_voodoo_pci_regs[1].base_addr;
378 break;
379 case 0x40:
380 val = m_voodoo_pci_regs[1].init_enable;
381 break;
382 default:
383 logerror("Voodoo[1] PCI R: %x\n", reg);
384 }
385 return val;
386 }
387
voodoo_1_pci_w(int function,int reg,uint32_t data,uint32_t mem_mask)388 void magictg_state::voodoo_1_pci_w(int function, int reg, uint32_t data, uint32_t mem_mask)
389 {
390 switch (reg)
391 {
392 case 0x04:
393 voodoo_pci_regs[1].command = data & 0x3;
394 break;
395 case 0x10:
396 if (data == 0xffffffff)
397 m_voodoo_pci_regs[1].base_addr = 0xff000000;
398 else
399 m_voodoo_pci_regs[1].base_addr = data;
400 break;
401 case 0x40:
402 m_voodoo_pci_regs[1].init_enable = data;
403 voodoo_set_init_enable(state->m_voodoo[1], data);
404 break;
405
406 default:
407 logerror("Voodoo [%x]: %x\n", reg, data);
408 }
409 }
410 #endif
411
412
413 /*************************************
414 *
415 * PinkEye (JPEG decoder)
416 *
417 *************************************/
418
zr36120_reset()419 void magictg_state::zr36120_reset()
420 {
421 /* Reset PCI registers */
422 m_zr36120.base_addr = 0;
423
424 /* Reset application-specific registers */
425 m_zr36120.as_regs[0x00/4] = (1 << 10) | 0x3ff;
426 m_zr36120.as_regs[0x04/4] = (1 << 10) | 0x3ff;
427 m_zr36120.as_regs[0x08/4] = (1 << 25) | (2 << 3) | 1;
428 m_zr36120.as_regs[0x0c/4] = 0xfffffffc;
429 m_zr36120.as_regs[0x10/4] = 0xfffffffc;
430 m_zr36120.as_regs[0x14/4] = 0x00000000;
431 m_zr36120.as_regs[0x18/4] = (7 << 25) | (0xf0 << 12) | 0x3ff;
432 m_zr36120.as_regs[0x1c/4] = 0xfffffffc;
433 m_zr36120.as_regs[0x20/4] = 0xfffffffc;
434 m_zr36120.as_regs[0x24/4] = 0x000000ff;
435 m_zr36120.as_regs[0x28/4] = 0x000000ff;
436 m_zr36120.as_regs[0x2c/4] = 0xf0000000;
437 m_zr36120.as_regs[0x30/4] = 0xfffffffc;
438 m_zr36120.as_regs[0x34/4] = (1 << 29) | (1 << 28) | (3 << 12) | (1 << 8) | (6 << 1);
439 m_zr36120.as_regs[0x38/4] = 0x00000000;
440 m_zr36120.as_regs[0x3c/4] = 0x00000000;
441 m_zr36120.as_regs[0x40/4] = 0x00000000;
442 m_zr36120.as_regs[0x44/4] = 0x00000003;
443 m_zr36120.as_regs[0x48/4] = 1 << 23;
444 }
445
zr36120_pci_r(int function,int reg,uint32_t mem_mask)446 uint32_t magictg_state::zr36120_pci_r(int function, int reg, uint32_t mem_mask)
447 {
448 uint32_t val = 0;
449
450 switch (reg)
451 {
452 case 0x00:
453 val = 0x612011de;
454 break;
455 case 0x04:
456 val = m_zr36120.command;
457 break;
458 case 0x08:
459 val = 0x04000002;
460 break;
461 case 0x10:
462 val = m_zr36120.base_addr;
463 break;
464 default:
465 logerror("ZR36120 R[%x]\n", reg);
466 }
467 return val;
468 }
469
zr36120_pci_w(int function,int reg,uint32_t data,uint32_t mem_mask)470 void magictg_state::zr36120_pci_w(int function, int reg, uint32_t data, uint32_t mem_mask)
471 {
472 switch (reg)
473 {
474 case 0x04:
475 m_zr36120.command = data & 0x6;
476 break;
477 case 0x10:
478 m_zr36120.base_addr = data & 0xfffff000;
479 break;
480 default:
481 logerror("ZR36120 [%x]: %x\n", reg, data);
482 }
483 }
484
zr36120_r(offs_t offset)485 uint32_t magictg_state::zr36120_r(offs_t offset)
486 {
487 uint32_t res = 0;
488
489 offset <<= 2;
490
491 if (offset < 0x200)
492 {
493 switch (offset)
494 {
495 default:
496 res = m_zr36120.as_regs[offset];
497 }
498 }
499 else
500 {
501 /* Post office */
502 res = 0;//mame_rand(machine);//m_zr36120.as_regs[0x48/4];
503 }
504 logerror("PINKEYE_R[%x]\n", offset);
505 return res;
506 }
507
zr36120_w(offs_t offset,uint32_t data)508 void magictg_state::zr36120_w(offs_t offset, uint32_t data)
509 {
510 offset <<= 2;
511
512 if (offset < 0x200)
513 {
514 logerror("PINKEYE_W[%x] %x\n", offset, data);
515 switch (offset)
516 {
517 case 0x00/4:
518 m_zr36120.as_regs[0] = data & 0x400fffff;
519 break;
520 case 0x04/4:
521 m_zr36120.as_regs[1] = data & 0x400003ff;
522 break;
523 default:
524 m_zr36120.as_regs[offset] = data;
525 }
526 }
527 else
528 {
529 uint32_t guest = (data >> 20) & 3;
530 uint32_t g_data = data & 0xff;
531 uint32_t g_reg = (data >> 16) & 7;
532
533 /* Direction - 0 for read, 1 for write */
534 // zr36120_guest_write(guest, g_data, g_reg);
535 // 2 - ZR36050 JPEG decoder
536 // 3 - ZR36016 color-space converter
537 logerror("GUEST (%.8x): %d REG: %d DATA: %x\n", data, guest, g_reg, g_data);
538 }
539 }
540
541
542 /*************************************
543 *
544 * System stuff
545 *
546 *************************************/
547
unk_r()548 uint32_t magictg_state::unk_r()
549 {
550 /* Will not boot otherwise */
551 return 0x6000;
552 }
553
unk2_r()554 uint32_t magictg_state::unk2_r()
555 {
556 return 0xffffffff;
557 }
558
serial_w(offs_t offset,uint32_t data,uint32_t mem_mask)559 void magictg_state::serial_w(offs_t offset, uint32_t data, uint32_t mem_mask)
560 {
561 if (offset == 0)
562 {
563 if (mem_mask == 0xff000000)
564 printf("%c", data >> 24);
565 }
566 }
567
f0_w(offs_t offset,uint32_t data,uint32_t mem_mask)568 void magictg_state::f0_w(offs_t offset, uint32_t data, uint32_t mem_mask)
569 {
570 int ch;
571
572 offset *= 4;
573
574 data = swapendian_int32(data);
575 mem_mask = swapendian_int32(mem_mask);
576
577 ch = ((offset >> 2) & 3) - 1;
578
579 switch (offset)
580 {
581 case 0x804:
582 case 0x808:
583 case 0x80c:
584 m_dma_ch[ch].count = data;
585 // logerror("DMA%d COUNT: %.8x\n", ch, data);
586 break;
587
588 case 0x814:
589 case 0x818:
590 case 0x81c:
591 m_dma_ch[ch].src_addr = data;
592 // logerror("DMA%d SRC: %.8x\n", ch, data);
593 break;
594
595 case 0x824:
596 case 0x828:
597 case 0x82c:
598 m_dma_ch[ch].dst_addr = data;
599 // logerror("DMA%d DST: %.8x\n", ch, data);
600 break;
601
602 case 0x844:
603 case 0x848:
604 case 0x84c:
605 {
606 m_dma_ch[ch].ctrl = data;
607 // logerror("DMA%d CTRL: %.8x\n", ch, data);
608
609 if (data & 0x1000)
610 {
611 uint32_t src_addr = m_dma_ch[ch].src_addr;
612 uint32_t dst_addr = m_dma_ch[ch].dst_addr;
613 //device_t *voodoo = dst_addr > 0xa000000 voodoo0 : voodoo1;
614
615 assert((src_addr & 3) == 0);
616 assert((dst_addr & 3) == 0);
617
618 while (m_dma_ch[ch].count > 3)
619 {
620 uint32_t src_dword = swapendian_int32(m_mips->space(AS_PROGRAM).read_dword(src_addr));
621 m_mips->space(AS_PROGRAM).write_dword(dst_addr, src_dword);
622 src_addr += 4;
623 dst_addr += 4;
624 m_dma_ch[ch].count -=4;
625 }
626
627 // FIXME!
628 if (m_dma_ch[ch].count & 3)
629 {
630 uint32_t src_dword = swapendian_int32(m_mips->space(AS_PROGRAM).read_dword(src_addr));
631 uint32_t dst_dword = m_mips->space(AS_PROGRAM).read_dword(dst_addr);
632 uint32_t mask = 0xffffffff >> ((m_dma_ch[ch].count & 3) << 3);
633
634 dst_dword = (dst_dword & ~mask) | (src_dword & mask);
635 m_mips->space(AS_PROGRAM).write_dword(dst_addr, dst_dword);
636 m_dma_ch[ch].count = 0;
637 }
638 }
639
640 break;
641 }
642 case 0xcf8:
643 {
644 m_pci->write(0, data, mem_mask);
645 break;
646 }
647 case 0xcfc:
648 {
649 m_pci->write(1, data, mem_mask);
650 break;
651 }
652 // default:
653 // logerror("W: %.8x: %.8x\n", 0x0f000000 + offset, data);
654 }
655 }
656
f0_r(offs_t offset,uint32_t mem_mask)657 uint32_t magictg_state::f0_r(offs_t offset, uint32_t mem_mask)
658 {
659 int ch;
660 uint32_t val = 0;
661 offset *= 4;
662
663 ch = ((offset >> 2) & 3) - 1;
664
665 switch (offset)
666 {
667 case 0x804:
668 case 0x808:
669 case 0x80c:
670 val = m_dma_ch[ch].count;
671 break;
672
673 case 0x844:
674 case 0x848:
675 case 0x84c:
676 val = 0x00000040; // Status of some sort
677 break;
678
679 case 0xcf8:
680 {
681 val = m_pci->read(0, swapendian_int32(mem_mask));
682 break;
683 }
684 case 0xcfc:
685 {
686 val = m_pci->read(1, swapendian_int32(mem_mask));
687 break;
688 }
689 // default:
690 // logerror("R: %.8x\n", 0x0f000000 + offset);
691 }
692
693 return swapendian_int32(val);
694 }
695
696
697 /*************************************
698 *
699 * ADSP-2181 internals
700 *
701 *************************************/
702
adsp_idma_data_w(offs_t offset,uint32_t data,uint32_t mem_mask)703 void magictg_state::adsp_idma_data_w(offs_t offset, uint32_t data, uint32_t mem_mask)
704 {
705 if (ACCESSING_BITS_16_31)
706 m_adsp->idma_addr_w(data >> 16);
707 else
708 m_adsp->idma_addr_w(data & 0xffff);
709 }
710
adsp_idma_data_r(offs_t offset,uint32_t mem_mask)711 uint32_t magictg_state::adsp_idma_data_r(offs_t offset, uint32_t mem_mask)
712 {
713 // TODO: Set /IACK appropriately
714 if (ACCESSING_BITS_0_15)
715 {
716 //logerror("RD %.8x %.8x\n", offset, mem_mask);
717 return m_adsp->idma_addr_r();
718 }
719 else
720 {
721 fatalerror("????\n");
722 }
723 }
724
adsp_idma_addr_w(offs_t offset,uint32_t data,uint32_t mem_mask)725 void magictg_state::adsp_idma_addr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
726 {
727 // TODO: Set /IACK appropriately
728 if (ACCESSING_BITS_16_31)
729 {
730 m_adsp->idma_addr_w(data >> 16);
731 //logerror("WR %.8x %.8x %.8x\n", offset, mem_mask, data >> 16);
732 }
733 else
734 fatalerror("????\n");
735 }
736
adsp_status_r()737 uint32_t magictg_state::adsp_status_r()
738 {
739 // ADSP_IACK = Bit 2
740 return (0 << 2) | (machine().rand() & 1);
741 }
742
adsp_control_r(offs_t offset)743 uint16_t magictg_state::adsp_control_r(offs_t offset)
744 {
745 uint16_t res = 0;
746
747 switch (offset)
748 {
749 case 0x4:
750 res = m_adsp_regs.bdma_word_count;
751 break;
752 case 0x5:
753 res = machine().rand() & 0xff;
754 break;
755 default:
756 logerror("Unhandled register: %x\n", 0x3fe0 + offset);
757 }
758 return res;
759 }
760
adsp_control_w(offs_t offset,uint16_t data)761 void magictg_state::adsp_control_w(offs_t offset, uint16_t data)
762 {
763 switch (offset)
764 {
765 case 0x1:
766 m_adsp_regs.bdma_internal_addr = data & 0x3fff;
767 break;
768 case 0x2:
769 m_adsp_regs.bdma_external_addr = data & 0x3fff;
770 break;
771 case 0x3:
772 m_adsp_regs.bdma_control = data & 0xff0f;
773 break;
774 case 0x4:
775 {
776 m_adsp_regs.bdma_word_count = data & 0x3fff;
777
778 if (data > 0)
779 {
780 uint8_t* adsp_rom = (uint8_t*)memregion("adsp")->base();
781
782 uint32_t page = (m_adsp_regs.bdma_control >> 8) & 0xff;
783 uint32_t dir = (m_adsp_regs.bdma_control >> 2) & 1;
784 uint32_t type = m_adsp_regs.bdma_control & 3;
785
786 uint32_t src_addr = (page << 14) | m_adsp_regs.bdma_external_addr;
787
788 address_space &addr_space = m_adsp->space((type == 0) ? AS_PROGRAM : AS_DATA);
789
790 if (dir == 0)
791 {
792 while (m_adsp_regs.bdma_word_count)
793 {
794 if (type == 0)
795 {
796 uint32_t src_word =(adsp_rom[src_addr + 0] << 16) |
797 (adsp_rom[src_addr + 1] << 8) |
798 (adsp_rom[src_addr + 2]);
799
800 addr_space.write_dword(m_adsp_regs.bdma_internal_addr * 4, src_word);
801
802 src_addr += 3;
803 m_adsp_regs.bdma_internal_addr ++;
804 }
805 else if (type == 1)
806 {
807 uint32_t src_word =(adsp_rom[src_addr + 0] << 8) | adsp_rom[src_addr + 1];
808
809 addr_space.write_dword(m_adsp_regs.bdma_internal_addr * 2, src_word);
810
811 src_addr += 2;
812 m_adsp_regs.bdma_internal_addr ++;
813 }
814 else
815 {
816 fatalerror("Unsupported BDMA width\n");
817 }
818
819 --m_adsp_regs.bdma_word_count;
820 }
821 }
822
823 /* Update external address count and page */
824 m_adsp_regs.bdma_external_addr = src_addr & 0x3fff;
825 m_adsp_regs.bdma_control &= ~0xff00;
826 m_adsp_regs.bdma_control |= ((src_addr >> 14) & 0xff) << 8;
827
828 if (m_adsp_regs.bdma_control & 8)
829 m_adsp->pulse_input_line(INPUT_LINE_RESET, attotime::zero);
830 }
831 break;
832 }
833 case 5:
834 logerror("PFLAGS: %x\n", data);
835 break;
836 default:
837 logerror("Unhandled register: %x %x\n", 0x3fe0 + offset, data);
838 }
839 }
840
841
842 /*************************************
843 *
844 * Main CPU
845 *
846 *************************************/
847
magictg_map(address_map & map)848 void magictg_state::magictg_map(address_map &map)
849 {
850 map(0x00000000, 0x007fffff).ram(); // 8MB RAM
851 map(0x00800000, 0x0081003f).ram(); // ?
852 map(0x0a000000, 0x0affffff).rw("voodoo_0", FUNC(voodoo_device::voodoo_r), FUNC(voodoo_device::voodoo_w));
853 #if defined(USE_TWO_3DFX)
854 map(0x0b000000, 0x0bffffff).rw("voodoo_1", FUNC(voodoo_device::voodoo_r), FUNC(voodoo_device::voodoo_w));
855 map(0x0c000000, 0x0c000fff).rw(FUNC(magictg_state::zr36120_r), FUNC(magictg_state::zr36120_w));
856 #else
857 map(0x0b000000, 0x0b000fff).rw(FUNC(magictg_state::zr36120_r), FUNC(magictg_state::zr36120_w));
858 #endif
859 map(0x0f000000, 0x0f000fff).rw(FUNC(magictg_state::f0_r), FUNC(magictg_state::f0_w)); // Split this up?
860 map(0x14000100, 0x14000103).rw(FUNC(magictg_state::adsp_idma_data_r), FUNC(magictg_state::adsp_idma_data_w));
861 map(0x14000104, 0x14000107).w(FUNC(magictg_state::adsp_idma_addr_w));
862 map(0x1b001024, 0x1b001027).r(FUNC(magictg_state::adsp_status_r));
863 map(0x1b001108, 0x1b00110b).r(FUNC(magictg_state::unk_r));
864 map(0x1e000000, 0x1e002fff).ram(); // NVRAM?
865 map(0x1e800000, 0x1e800007).rw(FUNC(magictg_state::unk2_r), FUNC(magictg_state::serial_w));
866 map(0x1fc00000, 0x1fffffff).rom().region("mips", 0);
867 }
868
869
870 /*************************************
871 *
872 * Mad Cow (IO/sound)
873 *
874 *************************************/
875
adsp_program_map(address_map & map)876 void magictg_state::adsp_program_map(address_map &map)
877 {
878 map.unmap_value_high();
879 map(0x0000, 0x3fff).ram().share("adsp_pram");
880 }
881
adsp_data_map(address_map & map)882 void magictg_state::adsp_data_map(address_map &map)
883 {
884 map.unmap_value_high();
885 // map(0x0000, 0x03ff).bankrw("databank");
886 map(0x0400, 0x3fdf).ram();
887 map(0x3fe0, 0x3fff).rw(FUNC(magictg_state::adsp_control_r), FUNC(magictg_state::adsp_control_w));
888 }
889
adsp_io_map(address_map & map)890 void magictg_state::adsp_io_map(address_map &map)
891 {
892 map.unmap_value_high();
893 }
894
895
896 /*************************************
897 *
898 * Input ports
899 *
900 *************************************/
901
902 static INPUT_PORTS_START( magictg )
903 PORT_START("IPT_TEST")
904 INPUT_PORTS_END
905
906
907 /*************************************
908 *
909 * Machine driver
910 *
911 *************************************/
912
magictg(machine_config & config)913 void magictg_state::magictg(machine_config &config)
914 {
915 R5000BE(config, m_mips, 150000000); /* TODO: CPU type and clock are unknown */
916 //m_mips->set_icache_size(16384); /* TODO: Unknown */
917 //m_mips->set_dcache_size(16384); /* TODO: Unknown */
918 m_mips->set_addrmap(AS_PROGRAM, &magictg_state::magictg_map);
919
920 ADSP2181(config, m_adsp, 16000000);
921 m_adsp->set_addrmap(AS_PROGRAM, &magictg_state::adsp_program_map);
922 m_adsp->set_addrmap(AS_DATA, &magictg_state::adsp_data_map);
923 m_adsp->set_addrmap(AS_IO, &magictg_state::adsp_io_map);
924
925 SPEAKER(config, "lspeaker").front_left();
926 SPEAKER(config, "rspeaker").front_right();
927
928 DMADAC(config, "dac1").add_route(ALL_OUTPUTS, "rspeaker", 1.0);
929 DMADAC(config, "dac2").add_route(ALL_OUTPUTS, "lspeaker", 1.0);
930
931 pci_bus_legacy_device &pcibus(PCI_BUS_LEGACY(config, "pcibus", 0, 0));
932 pcibus.set_device(0, FUNC(magictg_state::pci_dev0_r), FUNC(magictg_state::pci_dev0_w));
933 pcibus.set_device(7, FUNC(magictg_state::voodoo_0_pci_r), FUNC(magictg_state::voodoo_0_pci_w));
934
935 #if defined(USE_TWO_3DFX)
936 pcibus.set_device(8, FUNC(magictg_state::voodoo_1_pci_r), FUNC(magictg_state::voodoo_1_pci_w));
937 #endif
938 pcibus.set_device(9, FUNC(magictg_state::zr36120_pci_r), FUNC(magictg_state::zr36120_pci_w)); // TODO: ZR36120 device
939
940 VOODOO_1(config, m_voodoo[0], STD_VOODOO_1_CLOCK);
941 m_voodoo[0]->set_fbmem(2);
942 m_voodoo[0]->set_tmumem(4,0);
943 m_voodoo[0]->set_screen_tag("screen");
944 m_voodoo[0]->set_cpu_tag(m_mips);
945
946 VOODOO_1(config, m_voodoo[1], STD_VOODOO_1_CLOCK);
947 m_voodoo[1]->set_fbmem(2);
948 m_voodoo[1]->set_tmumem(4,0);
949 m_voodoo[1]->set_screen_tag("screen");
950 m_voodoo[1]->set_cpu_tag(m_mips);
951
952 screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER));
953 screen.set_refresh_hz(60);
954 screen.set_vblank_time(ATTOSECONDS_IN_USEC(0));
955 screen.set_size(1024, 1024);
956 screen.set_visarea(0, 511, 16, 447);
957 screen.set_screen_update(FUNC(magictg_state::screen_update_magictg));
958 }
959
960
961 /*************************************
962 *
963 * ROM definitions
964 *
965 *************************************/
966
967 ROM_START( magictg )
968 ROM_REGION64_BE( 0x400000, "mips", 0 )
969 ROM_LOAD16_BYTE( "magic.u34", 0x000000, 0x100000, CRC(2e8971e2) SHA1(9bdf433a7c7257389ebdf131317ef26a7d4e1ba2) )
970 ROM_LOAD16_BYTE( "magic.u35", 0x000001, 0x100000, CRC(e2202143) SHA1(f07b7da81508cd4594f66e34dabd904a21eb03f0) )
971 ROM_LOAD16_BYTE( "magic.u32", 0x200000, 0x100000, CRC(f1d530e3) SHA1(fcc392804cd6b98917a869cc5d3826278b7ba90b) )
972 ROM_LOAD16_BYTE( "magic.u33", 0x200001, 0x100000, CRC(b2330cfc) SHA1(559c35426588b349ef31bf8b296b950912f6fcc7) )
973
974 ROM_REGION16_LE( 0x80000, "adsp", 0 )
975 ROM_LOAD( "magic.20u", 0x00000, 0x80000, CRC(50968301) SHA1(e9bdd0c942f0c66e18aa8de5a04edb51cdf1fee8) )
976
977 ROM_REGION32_BE( 0x1000000, "adsp_data", 0 )
978 ROM_LOAD( "magic.snd0.u8", 0x000000, 0x400000, CRC(3cb81717) SHA1(9d35796381ca57e9782e0338c456e63c31d11266) )
979 ROM_LOAD( "magic.snd1.u14",0x400000, 0x400000, CRC(b4ef9977) SHA1(dedc79e5d506bb0d1649a41b9912dcc999e1da72) )
980 ROM_LOAD( "magic.snd2.u13",0x800000, 0x400000, CRC(3728f16e) SHA1(6b7da30b100d053e95aa96edf74a0474f1493dfb) )
981 ROM_LOAD( "magic.snd3.u7", 0xc00000, 0x400000, CRC(11a1cb63) SHA1(a1048d3cd580747c20eb0b4e816e7e4e0f5c8c2b) )
982
983 ROM_REGION( 0x2000000, "jpeg", 0 )
984 ROM_LOAD( "magic_s0.u9", 0x0000000, 0x800000, CRC(a01b5b99) SHA1(e77f2e9b08a97d6118e1e307b38ea79d0177e9b8) )
985 ROM_LOAD( "magic_s1.u10", 0x0800000, 0x800000, CRC(d5a1a557) SHA1(2511ee8d08da765a2fa2d42fb504793f9e8b615c) )
986 ROM_LOAD( "magic_s2.u12", 0x1000000, 0x800000, CRC(06ed6770) SHA1(884a3e4c97a50fa926546eb6def2c11c5732ba88) )
987 ROM_LOAD( "magic_s3.u11", 0x1800000, 0x800000, CRC(71d4c252) SHA1(aeab2542b9d5fb63f4d60b808010a657a895c1d7) )
988
989 ROM_REGION( 0x400000, "key", 0 )
990 ROM_LOAD( "magic.k0.u20", 0x000000, 0x400000, CRC(63ab0e9e) SHA1(c4f0b009860ee499496ed7fc1f14ef1e221c1085) )
991 ROM_END
992
993 ROM_START( magictga )
994 ROM_REGION64_BE( 0x400000, "mips", 0 )
995 ROM_LOAD16_BYTE( "magic.u63", 0x000000, 0x100000, CRC(a10d45f1) SHA1(0ede10f19cf70baf7b43e3f672532b4be1a179f8) )
996 ROM_LOAD16_BYTE( "magic.u64", 0x000001, 0x100000, CRC(8fdb6060) SHA1(b638244cad86dc60435a4a9150a5b639f5d61a3f) )
997 ROM_LOAD16_BYTE( "magic.u61", 0x200000, 0x100000, CRC(968891d6) SHA1(67ab87039864bb148d20795333ffa7a23e3b84f2) )
998 ROM_LOAD16_BYTE( "magic.u62", 0x200001, 0x100000, CRC(690946eb) SHA1(6c9b02367704309f4fde5cbd9d195a45c32c3861) )
999
1000 // this set was incomplete, none of these roms were dumped for it, are they the same?
1001 ROM_REGION32_BE( 0x80000, "adsp", 0 )
1002 ROM_LOAD( "magic.20u", 0x00000, 0x80000, BAD_DUMP CRC(50968301) SHA1(e9bdd0c942f0c66e18aa8de5a04edb51cdf1fee8) )
1003
1004 ROM_REGION32_BE( 0x1000000, "adsp_data", 0 )
1005 ROM_LOAD( "magic.snd0.u8", 0x000000, 0x400000, BAD_DUMP CRC(3cb81717) SHA1(9d35796381ca57e9782e0338c456e63c31d11266) )
1006 ROM_LOAD( "magic.snd1.u14",0x400000, 0x400000, BAD_DUMP CRC(b4ef9977) SHA1(dedc79e5d506bb0d1649a41b9912dcc999e1da72) )
1007 ROM_LOAD( "magic.snd2.u13",0x800000, 0x400000, BAD_DUMP CRC(3728f16e) SHA1(6b7da30b100d053e95aa96edf74a0474f1493dfb) )
1008 ROM_LOAD( "magic.snd3.u7", 0xc00000, 0x400000, BAD_DUMP CRC(11a1cb63) SHA1(a1048d3cd580747c20eb0b4e816e7e4e0f5c8c2b) )
1009
1010 ROM_REGION( 0x2000000, "jpeg", 0 )
1011 ROM_LOAD( "magic_s0.u9", 0x0000000, 0x800000, BAD_DUMP CRC(a01b5b99) SHA1(e77f2e9b08a97d6118e1e307b38ea79d0177e9b8) )
1012 ROM_LOAD( "magic_s1.u10", 0x0800000, 0x800000, BAD_DUMP CRC(d5a1a557) SHA1(2511ee8d08da765a2fa2d42fb504793f9e8b615c) )
1013 ROM_LOAD( "magic_s2.u12", 0x1000000, 0x800000, BAD_DUMP CRC(06ed6770) SHA1(884a3e4c97a50fa926546eb6def2c11c5732ba88) )
1014 ROM_LOAD( "magic_s3.u11", 0x1800000, 0x800000, BAD_DUMP CRC(71d4c252) SHA1(aeab2542b9d5fb63f4d60b808010a657a895c1d7) )
1015
1016 ROM_REGION( 0x400000, "key", 0 )
1017 ROM_LOAD( "magic.k0.u20", 0x000000, 0x400000, BAD_DUMP CRC(63ab0e9e) SHA1(c4f0b009860ee499496ed7fc1f14ef1e221c1085) )
1018 ROM_END
1019
1020
1021 /*************************************
1022 *
1023 * Game driver(s)
1024 *
1025 *************************************/
1026
1027 GAME( 1997, magictg, 0, magictg, magictg, magictg_state, empty_init, ROT0, "Acclaim", "Magic the Gathering: Armageddon (set 1)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
1028 GAME( 1997, magictga, magictg, magictg, magictg, magictg_state, empty_init, ROT0, "Acclaim", "Magic the Gathering: Armageddon (set 2)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
1029