1 // license:BSD-3-Clause 2 // copyright-holders:Ryan Holtz 3 #ifndef MAME_INCLUDES_N64_H 4 #define MAME_INCLUDES_N64_H 5 6 #pragma once 7 8 #include "cpu/rsp/rsp.h" 9 #include "cpu/mips/mips3.h" 10 #include "sound/dmadac.h" 11 12 /*----------- driver state -----------*/ 13 14 class n64_rdp; 15 class n64_periphs; 16 17 class n64_state : public driver_device 18 { 19 public: n64_state(const machine_config & mconfig,device_type type,const char * tag)20 n64_state(const machine_config &mconfig, device_type type, const char *tag) 21 : driver_device(mconfig, type, tag) 22 , m_vr4300(*this, "maincpu") 23 , m_rsp(*this, "rsp") 24 , m_sram(*this, "sram") 25 , m_rdram(*this, "rdram") 26 , m_rsp_imem(*this, "rsp_imem") 27 , m_rsp_dmem(*this, "rsp_dmem") 28 , m_rcp_periphs(*this, "rcp") 29 { 30 } 31 32 virtual void machine_start() override; 33 virtual void machine_reset() override; 34 virtual void video_start() override; 35 void n64_machine_stop(); 36 37 uint32_t screen_update_n64(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); 38 DECLARE_WRITE_LINE_MEMBER(screen_vblank_n64); 39 40 // Getters rdp()41 n64_rdp* rdp() { return m_rdp; } rdram()42 uint32_t* rdram() { return m_rdram; } sram()43 uint32_t* sram() { return m_sram; } rsp_imem()44 uint32_t* rsp_imem() { return m_rsp_imem; } rsp_dmem()45 uint32_t* rsp_dmem() { return m_rsp_dmem; } 46 47 protected: 48 required_device<mips3_device> m_vr4300; 49 required_device<rsp_device> m_rsp; 50 51 optional_shared_ptr<uint32_t> m_sram; 52 required_shared_ptr<uint32_t> m_rdram; 53 required_shared_ptr<uint32_t> m_rsp_imem; 54 required_shared_ptr<uint32_t> m_rsp_dmem; 55 56 required_device<n64_periphs> m_rcp_periphs; 57 58 /* video-related */ 59 n64_rdp *m_rdp; 60 }; 61 62 /*----------- devices -----------*/ 63 64 #define AUDIO_DMA_DEPTH 2 65 66 struct n64_savable_data_t 67 { 68 uint8_t sram[0x20000]; 69 uint8_t eeprom[2048]; 70 uint8_t mempak[2][0x8000]; 71 }; 72 73 class n64_periphs : public device_t, 74 public device_video_interface 75 { 76 private: 77 struct AUDIO_DMA 78 { 79 uint32_t address; 80 uint32_t length; 81 }; 82 83 public: 84 // construction/destruction 85 n64_periphs(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); 86 87 uint32_t is64_r(offs_t offset); 88 void is64_w(offs_t offset, uint32_t data); 89 uint32_t open_r(offs_t offset); 90 void open_w(uint32_t data); 91 uint32_t rdram_reg_r(offs_t offset, uint32_t mem_mask = ~0); 92 void rdram_reg_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 93 uint32_t mi_reg_r(offs_t offset, uint32_t mem_mask = ~0); 94 void mi_reg_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 95 uint32_t vi_reg_r(offs_t offset, uint32_t mem_mask = ~0); 96 void vi_reg_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 97 uint32_t ai_reg_r(offs_t offset, uint32_t mem_mask = ~0); 98 void ai_reg_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 99 uint32_t pi_reg_r(offs_t offset, uint32_t mem_mask = ~0); 100 void pi_reg_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 101 uint32_t ri_reg_r(offs_t offset, uint32_t mem_mask = ~0); 102 void ri_reg_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 103 uint32_t si_reg_r(offs_t offset); 104 void si_reg_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 105 uint32_t dd_reg_r(offs_t offset); 106 void dd_reg_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 107 uint32_t pif_ram_r(offs_t offset, uint32_t mem_mask = ~0); 108 void pif_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 109 TIMER_CALLBACK_MEMBER(reset_timer_callback); 110 TIMER_CALLBACK_MEMBER(vi_scanline_callback); 111 TIMER_CALLBACK_MEMBER(dp_delay_callback); 112 TIMER_CALLBACK_MEMBER(ai_timer_callback); 113 TIMER_CALLBACK_MEMBER(pi_dma_callback); 114 TIMER_CALLBACK_MEMBER(si_dma_callback); 115 uint32_t dp_reg_r(offs_t offset, uint32_t mem_mask = ~0); 116 void dp_reg_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 117 uint32_t sp_reg_r(offs_t offset); 118 void sp_reg_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 119 void sp_set_status(uint32_t data); 120 void signal_rcp_interrupt(int interrupt); 121 void check_interrupts(); 122 123 void dp_full_sync(); 124 void ai_timer_tick(); 125 void pi_dma_tick(); 126 void si_dma_tick(); 127 void reset_tick(); 128 void video_update(bitmap_rgb32 &bitmap); 129 130 // Video Interface (VI) registers 131 uint32_t vi_width; 132 uint32_t vi_origin; 133 uint32_t vi_control; 134 uint32_t vi_blank; 135 uint32_t vi_hstart; 136 uint32_t vi_vstart; 137 uint32_t vi_xscale; 138 uint32_t vi_yscale; 139 uint32_t vi_burst; 140 uint32_t vi_vsync; 141 uint32_t vi_hsync; 142 uint32_t vi_leap; 143 uint32_t vi_intr; 144 uint32_t vi_vburst; 145 uint8_t field; 146 147 /* nvram-specific for MESS */ 148 device_t *m_nvram_image; 149 150 n64_savable_data_t m_save_data; 151 152 uint32_t cart_length; 153 154 bool dd_present; 155 bool disk_present; 156 bool cart_present; 157 158 // Mouse X2/Y2 for delta position 159 int mouse_x2[4]; 160 int mouse_y2[4]; 161 162 void poll_reset_button(bool button); 163 164 uint32_t dp_clock; 165 166 protected: 167 // device-level overrides 168 virtual void device_start() override; 169 virtual void device_reset() override; 170 171 private: 172 n64_state* m_n64; 173 address_space *m_mem_map; 174 required_device<mips3_device> m_vr4300; 175 required_device<rsp_device> m_rsp; 176 177 uint32_t *m_rdram; 178 uint32_t *m_sram; 179 uint32_t *m_rsp_imem; 180 uint32_t *m_rsp_dmem; 181 182 void clear_rcp_interrupt(int interrupt); 183 184 bool reset_held; 185 emu_timer *reset_timer; 186 emu_timer *dp_delay_timer; 187 188 uint8_t is64_buffer[0x10000]; 189 190 // Video interface (VI) registers and functions 191 emu_timer *vi_scanline_timer; 192 193 // Audio Interface (AI) registers and functions 194 void ai_dma(); 195 AUDIO_DMA *ai_fifo_get_top(); 196 void ai_fifo_push(uint32_t address, uint32_t length); 197 void ai_fifo_pop(); 198 bool ai_delayed_carry; 199 200 required_device_array<dmadac_sound_device, 2> ai_dac; 201 uint32_t ai_dram_addr; 202 uint32_t ai_len; 203 uint32_t ai_control; 204 int ai_dacrate; 205 int ai_bitrate; 206 uint32_t ai_status; 207 208 emu_timer *ai_timer; 209 210 AUDIO_DMA ai_fifo[AUDIO_DMA_DEPTH]; 211 int ai_fifo_wpos; 212 int ai_fifo_rpos; 213 int ai_fifo_num; 214 215 // Memory Interface (MI) registers 216 uint32_t mi_version; 217 uint32_t mi_interrupt; 218 uint32_t mi_intr_mask; 219 uint32_t mi_mode; 220 221 // RDRAM Interface (RI) registers 222 uint32_t rdram_regs[10]; 223 uint32_t ri_regs[8]; 224 225 // RSP Interface (SP) registers 226 void sp_dma(int direction); 227 228 uint32_t sp_mem_addr; 229 uint32_t sp_dram_addr; 230 int sp_dma_length; 231 int sp_dma_count; 232 int sp_dma_skip; 233 uint32_t sp_semaphore; 234 235 // Disk Drive (DD) registers and functions 236 void dd_set_zone_and_track_offset(); 237 void dd_update_bm(); 238 void dd_write_sector(); 239 void dd_read_sector(); 240 void dd_read_C2(); 241 uint32_t dd_buffer[256]; 242 uint32_t dd_sector_data[64]; 243 uint32_t dd_ram_seq_data[16]; 244 uint32_t dd_data_reg; 245 uint32_t dd_status_reg; 246 uint32_t dd_track_reg; 247 uint32_t dd_buf_status_reg; 248 uint32_t dd_sector_err_reg; 249 uint32_t dd_seq_status_reg; 250 uint32_t dd_seq_ctrl_reg; 251 uint32_t dd_sector_reg; 252 uint32_t dd_reset_reg; 253 uint32_t dd_current_reg; 254 bool dd_bm_reset_held; 255 bool dd_write; 256 uint8_t dd_int; 257 uint8_t dd_start_block; 258 uint8_t dd_start_sector; 259 uint8_t dd_sectors_per_block; 260 uint8_t dd_sector_size; 261 uint8_t dd_zone; 262 uint32_t dd_track_offset; 263 264 // Peripheral Interface (PI) registers and functions 265 emu_timer *pi_dma_timer; 266 uint32_t pi_dram_addr; 267 uint32_t pi_cart_addr; 268 uint32_t pi_rd_len; 269 uint32_t pi_wr_len; 270 uint32_t pi_status; 271 uint32_t pi_bsd_dom1_lat; 272 uint32_t pi_bsd_dom1_pwd; 273 uint32_t pi_bsd_dom1_pgs; 274 uint32_t pi_bsd_dom1_rls; 275 uint32_t pi_bsd_dom2_lat; 276 uint32_t pi_bsd_dom2_pwd; 277 uint32_t pi_bsd_dom2_pgs; 278 uint32_t pi_bsd_dom2_rls; 279 uint32_t pi_dma_dir; 280 281 // Serial Interface (SI) registers and functions 282 emu_timer *si_dma_timer; 283 void pif_dma(int direction); 284 void handle_pif(); 285 int pif_channel_handle_command(int channel, int slength, uint8_t *sdata, int rlength, uint8_t *rdata); 286 uint8_t calc_mempak_crc(uint8_t *buffer, int length); 287 uint8_t pif_ram[0x40]; 288 uint8_t pif_cmd[0x40]; 289 uint32_t si_dram_addr; 290 uint32_t si_pif_addr; 291 uint32_t si_pif_addr_rd64b; 292 uint32_t si_pif_addr_wr64b; 293 uint32_t si_status_val; 294 uint32_t si_dma_dir; 295 uint32_t cic_status; 296 int cic_type; 297 298 n64_savable_data_t savable_data; 299 300 // Video Interface (VI) functions 301 void vi_recalculate_resolution(); 302 void video_update16(bitmap_rgb32 &bitmap); 303 void video_update32(bitmap_rgb32 &bitmap); 304 uint8_t random_seed; // %HACK%, adds 19 each time it's read and is more or less random get_random()305 uint8_t get_random() { return random_seed += 0x13; } 306 307 int32_t m_gamma_table[256]; 308 int32_t m_gamma_dither_table[0x4000]; 309 310 }; 311 312 // device type definition 313 DECLARE_DEVICE_TYPE(N64PERIPH, n64_periphs) 314 315 /*----------- defined in video/n64.c -----------*/ 316 317 #define DACRATE_NTSC (48681812) 318 #define DACRATE_PAL (49656530) 319 #define DACRATE_MPAL (48628316) 320 321 /*----------- defined in machine/n64.c -----------*/ 322 323 #define SP_INTERRUPT 0x1 324 #define SI_INTERRUPT 0x2 325 #define AI_INTERRUPT 0x4 326 #define VI_INTERRUPT 0x8 327 #define PI_INTERRUPT 0x10 328 #define DP_INTERRUPT 0x20 329 330 #define SP_STATUS_HALT 0x0001 331 #define SP_STATUS_BROKE 0x0002 332 #define SP_STATUS_DMABUSY 0x0004 333 #define SP_STATUS_DMAFULL 0x0008 334 #define SP_STATUS_IOFULL 0x0010 335 #define SP_STATUS_SSTEP 0x0020 336 #define SP_STATUS_INTR_BREAK 0x0040 337 #define SP_STATUS_SIGNAL0 0x0080 338 #define SP_STATUS_SIGNAL1 0x0100 339 #define SP_STATUS_SIGNAL2 0x0200 340 #define SP_STATUS_SIGNAL3 0x0400 341 #define SP_STATUS_SIGNAL4 0x0800 342 #define SP_STATUS_SIGNAL5 0x1000 343 #define SP_STATUS_SIGNAL6 0x2000 344 #define SP_STATUS_SIGNAL7 0x4000 345 346 #define DP_STATUS_XBUS_DMA 0x01 347 #define DP_STATUS_FREEZE 0x02 348 #define DP_STATUS_FLUSH 0x04 349 #define DP_STATUS_START_VALID 0x400 350 351 #define DD_ASIC_STATUS_DISK_CHANGE 0x00010000 352 #define DD_ASIC_STATUS_MECHA_ERR 0x00020000 353 #define DD_ASIC_STATUS_WRPROTECT_ERR 0x00040000 354 #define DD_ASIC_STATUS_HEAD_RETRACT 0x00080000 355 #define DD_ASIC_STATUS_MOTOR_OFF 0x00100000 356 #define DD_ASIC_STATUS_RESET 0x00400000 357 #define DD_ASIC_STATUS_BUSY 0x00800000 358 #define DD_ASIC_STATUS_DISK 0x01000000 359 #define DD_ASIC_STATUS_MECHA_INT 0x02000000 360 #define DD_ASIC_STATUS_BM_INT 0x04000000 361 #define DD_ASIC_STATUS_BM_ERROR 0x08000000 362 #define DD_ASIC_STATUS_C2_XFER 0x10000000 363 #define DD_ASIC_STATUS_DREQ 0x40000000 364 365 #define DD_TRACK_INDEX_LOCK 0x60000000 366 367 #define DD_BM_MECHA_INT_RESET 0x01000000 368 #define DD_BM_XFERBLOCKS 0x02000000 369 #define DD_BM_DISABLE_C1 0x04000000 370 #define DD_BM_DISABLE_OR_CHK 0x08000000 371 #define DD_BM_RESET 0x10000000 372 #define DD_BM_INT_MASK 0x20000000 373 #define DD_BM_MODE 0x40000000 374 #define DD_BM_START 0x80000000 375 376 #define DD_BMST_RUNNING 0x80000000 377 #define DD_BMST_ERROR 0x04000000 378 #define DD_BMST_MICRO_STATUS 0x02000000 379 #define DD_BMST_BLOCKS 0x01000000 380 #define DD_BMST_C1_CORRECT 0x00800000 381 #define DD_BMST_C1_DOUBLE 0x00400000 382 #define DD_BMST_C1_SINGLE 0x00200000 383 #define DD_BMST_C1_ERROR 0x00010000 384 385 #define DD_ASIC_ERR_AM_FAIL 0x80000000 386 #define DD_ASIC_ERR_MICRO_FAIL 0x40000000 387 #define DD_ASIC_ERR_SPINDLE_FAIL 0x20000000 388 #define DD_ASIC_ERR_OVER_RUN 0x10000000 389 #define DD_ASIC_ERR_OFFTRACK 0x08000000 390 #define DD_ASIC_ERR_NO_DISK 0x04000000 391 #define DD_ASIC_ERR_CLOCK_UNLOCK 0x02000000 392 #define DD_ASIC_ERR_SELF_STOP 0x01000000 393 394 #define DD_SEQ_MICRO_INT_MASK 0x80000000 395 #define DD_SEQ_MICRO_PC_ENABLE 0x40000000 396 397 #define SECTORS_PER_BLOCK 85 398 #define BLOCKS_PER_TRACK 2 399 400 const unsigned int ddZoneSecSize[16] = {232,216,208,192,176,160,144,128, 401 216,208,192,176,160,144,128,112}; 402 const unsigned int ddZoneTrackSize[16] = {158,158,149,149,149,149,149,114, 403 158,158,149,149,149,149,149,114}; 404 const unsigned int ddStartOffset[16] = 405 {0x0,0x5F15E0,0xB79D00,0x10801A0,0x1523720,0x1963D80,0x1D414C0,0x20BBCE0, 406 0x23196E0,0x28A1E00,0x2DF5DC0,0x3299340,0x36D99A0,0x3AB70E0,0x3E31900,0x4149200}; 407 408 #endif // MAME_INCLUDES_N64_H 409