1 // license:BSD-3-Clause 2 // copyright-holders:Phil Stroffolino 3 /*************************************************************************** 4 5 Namco System NB-1 hardware 6 7 ***************************************************************************/ 8 #ifndef MAME_INCLUDES_NAMCONB1_H 9 #define MAME_INCLUDES_NAMCONB1_H 10 11 #pragma once 12 13 #include "machine/eeprompar.h" 14 #include "machine/namcomcu.h" 15 #include "machine/timer.h" 16 #include "screen.h" 17 #include "video/namco_c116.h" 18 #include "video/namco_c355spr.h" 19 #include "video/namco_c123tmap.h" 20 #include "video/namco_c169roz.h" 21 22 23 class namconb1_state : public driver_device 24 { 25 public: namconb1_state(const machine_config & mconfig,device_type type,const char * tag)26 namconb1_state(const machine_config &mconfig, device_type type, const char *tag) : 27 driver_device(mconfig, type, tag), 28 m_gametype(0), 29 m_maincpu(*this, "maincpu"), 30 m_c116(*this, "c116"), 31 m_c123tmap(*this, "c123tmap"), 32 m_c355spr(*this, "c355spr"), 33 m_c169roz(*this, "c169roz"), 34 m_screen(*this, "screen"), 35 m_mcu(*this, "mcu"), 36 m_eeprom(*this, "eeprom"), 37 m_p1(*this, "P1"), 38 m_p2(*this, "P2"), 39 m_p3(*this, "P3"), 40 m_p4(*this, "P4"), 41 m_misc(*this, "MISC"), 42 m_light0_x(*this, "LIGHT0_X"), 43 m_light0_y(*this, "LIGHT0_Y"), 44 m_light1_x(*this, "LIGHT1_X"), 45 m_light1_y(*this, "LIGHT1_Y"), 46 m_spritebank32(*this, "spritebank32"), 47 m_tilebank32(*this, "tilebank32"), 48 m_rozbank32(*this, "rozbank32"), 49 m_namconb_shareram(*this, "namconb_share") 50 { } 51 52 void namconb1(machine_config &config); 53 void namconb2(machine_config &config); 54 void outfxies(machine_config &config); 55 void machbrkr(machine_config &config); 56 57 void init_sws95(); 58 void init_machbrkr(); 59 void init_sws97(); 60 void init_sws96(); 61 void init_vshoot(); 62 void init_nebulray(); 63 void init_gunbulet(); 64 void init_gslgr94j(); 65 void init_outfxies(); 66 void init_gslgr94u(); 67 68 protected: 69 virtual void machine_start() override; 70 virtual void machine_reset() override; 71 virtual void video_start() override; 72 73 private: 74 int m_gametype; 75 enum 76 { 77 /* Namco NB1 */ 78 NAMCONB1_NEBULRAY = 0x2000, 79 NAMCONB1_GUNBULET, 80 NAMCONB1_GSLGR94U, 81 NAMCONB1_GSLGR94J, 82 NAMCONB1_SWS95, 83 NAMCONB1_SWS96, 84 NAMCONB1_SWS97, 85 NAMCONB1_VSHOOT, 86 87 /* Namco NB2 */ 88 NAMCONB2_OUTFOXIES, 89 NAMCONB2_MACH_BREAKERS, 90 }; 91 92 required_device<cpu_device> m_maincpu; 93 required_device<namco_c116_device> m_c116; 94 required_device<namco_c123tmap_device> m_c123tmap; 95 required_device<namco_c355spr_device> m_c355spr; 96 optional_device<namco_c169roz_device> m_c169roz; // NB1 only, not NA1 97 required_device<screen_device> m_screen; 98 required_device<m37710_cpu_device> m_mcu; 99 required_device<eeprom_parallel_28xx_device> m_eeprom; 100 required_ioport m_p1; 101 required_ioport m_p2; 102 optional_ioport m_p3; 103 optional_ioport m_p4; 104 required_ioport m_misc; 105 optional_ioport m_light0_x; 106 optional_ioport m_light0_y; 107 optional_ioport m_light1_x; 108 optional_ioport m_light1_y; 109 required_shared_ptr<u32> m_spritebank32; 110 optional_shared_ptr<u32> m_tilebank32; 111 optional_shared_ptr<u32> m_rozbank32; 112 required_shared_ptr<u16> m_namconb_shareram; 113 114 u8 m_vbl_irq_level; 115 u8 m_pos_irq_level; 116 u8 m_unk_irq_level; 117 u16 m_count; 118 u8 m_port6; 119 u32 m_tilemap_tile_bank[4]; 120 std::unique_ptr<u32[]> m_spritebank32_delayed; 121 122 u32 randgen_r(); 123 void srand_w(u32 data); 124 void namconb1_cpureg_w(offs_t offset, u8 data); 125 void namconb2_cpureg_w(offs_t offset, u8 data); 126 u8 namconb1_cpureg_r(offs_t offset); 127 u8 namconb2_cpureg_r(offs_t offset); 128 u32 custom_key_r(offs_t offset); 129 u32 gunbulet_gun_r(offs_t offset); 130 u32 share_r(offs_t offset); 131 void share_w(offs_t offset, u32 data, u32 mem_mask = ~0); 132 void mcu_shared_w(offs_t offset, u16 data, u16 mem_mask = ~0); 133 u8 port6_r(); 134 void port6_w(u8 data); 135 u8 port7_r(); 136 template <int Bit> u16 dac_bit_r(); 137 138 void rozbank32_w(offs_t offset, u32 data, u32 mem_mask = ~0); 139 void video_update_common(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect); 140 u32 screen_update_namconb1(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect); 141 u32 screen_update_namconb2(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect); 142 DECLARE_WRITE_LINE_MEMBER(screen_vblank); 143 144 TIMER_DEVICE_CALLBACK_MEMBER(scantimer); 145 TIMER_DEVICE_CALLBACK_MEMBER(mcu_irq0_cb); 146 TIMER_DEVICE_CALLBACK_MEMBER(mcu_irq2_cb); 147 148 int NB1objcode2tile(int code); 149 int NB2objcode2tile_machbrkr(int code); 150 int NB2objcode2tile_outfxies(int code); 151 void NB1TilemapCB(u16 code, int *tile, int *mask); 152 void NB2TilemapCB_machbrkr(u16 code, int *tile, int *mask); 153 void NB2TilemapCB_outfxies(u16 code, int *tile, int *mask); 154 void NB2RozCB_machbrkr(u16 code, int *tile, int *mask, int which); 155 void NB2RozCB_outfxies(u16 code, int *tile, int *mask, int which); 156 void namcoc75_am(address_map &map); 157 void namconb1_am(address_map &map); 158 void namconb2_am(address_map &map); 159 }; 160 161 #endif // MAME_INCLUDES_NAMCONB1_H 162