1 /////////////////////////////////////////////////////////////// 2 // File: v810_opt.h 3 // 4 // Description: Defines used in v810_dis.cpp 5 // 6 7 #ifndef V810_OPT_H_ 8 #define V810_OPT_H_ 9 10 namespace Mednafen 11 { 12 #define sign_26(num) ((uint32)sign_x_to_s32(26, num)) 13 #define sign_16(num) ((uint32)(int16)(num)) 14 #define sign_14(num) ((uint32)sign_x_to_s32(14, num)) 15 #define sign_12(num) ((uint32)sign_x_to_s32(12, num)) 16 #define sign_9(num) ((uint32)sign_x_to_s32(9, num)) 17 #define sign_8(_value) ((uint32)(int8)(_value)) 18 #define sign_5(num) ((uint32)sign_x_to_s32(5, num)) 19 20 /////////////////////////////////////////////////////////////////// 21 // Define Modes 22 #define AM_I 0x01 23 #define AM_II 0x02 24 #define AM_III 0x03 25 #define AM_IV 0x04 26 #define AM_V 0x05 27 #define AM_VIa 0x06 // Mode6 form1 28 #define AM_VIb 0x0A // Mode6 form2 29 #define AM_VII 0x07 30 #define AM_VIII 0x08 31 #define AM_IX 0x09 32 #define AM_BSTR 0x0B // Bit String Instructions 33 #define AM_FPP 0x0C // Floating Point Instructions 34 #define AM_UDEF 0x0D // Unknown/Undefined Instructions 35 36 /////////////////////////////////////////////////////////////////// 37 // Table of Instructions Address Modes 38 39 static const int addr_mode[80] = { 40 AM_I, AM_I, AM_I, AM_I, AM_I, AM_I, AM_I, AM_I, 41 AM_I, AM_I, AM_I, AM_I, AM_I, AM_I, AM_I, AM_I, 42 AM_II, AM_II, AM_II, AM_II, AM_II, AM_II, AM_II, AM_II, 43 AM_II, AM_IX, AM_IX, AM_UDEF, AM_II, AM_II, AM_II, AM_BSTR, 44 AM_UDEF, AM_UDEF, AM_UDEF, AM_UDEF, AM_UDEF, AM_UDEF, AM_UDEF, AM_UDEF, 45 AM_V, AM_V, AM_IV, AM_IV, AM_V, AM_V, AM_V, AM_V, 46 AM_VIa, AM_VIa, AM_UDEF, AM_VIa, AM_VIb, AM_VIb, AM_UDEF, AM_VIb, 47 AM_VIa, AM_VIa, AM_VIa, AM_VIa, AM_VIb, AM_VIb, AM_FPP, AM_VIb, 48 AM_III, AM_III, AM_III, AM_III, AM_III, AM_III, AM_III, AM_III, 49 AM_III, AM_III, AM_III, AM_III, AM_III, AM_III, AM_III, AM_III 50 }; 51 // All instructions greater than 0x50 are undefined (this should not be posible of cource) 52 53 54 /////////////////////////////////////////////////////////////////// 55 // Opcodes for V810 Instruction set 56 #define MOV 0x00 57 #define ADD 0x01 58 #define SUB 0x02 59 #define CMP 0x03 60 #define SHL 0x04 61 #define SHR 0x05 62 #define JMP 0x06 63 #define SAR 0x07 64 #define MUL 0x08 65 #define DIV 0x09 66 #define MULU 0x0A 67 #define DIVU 0x0B 68 #define OR 0x0C 69 #define AND 0x0D 70 #define XOR 0x0E 71 #define NOT 0x0F 72 #define MOV_I 0x10 73 #define ADD_I 0x11 74 #define SETF 0x12 75 #define CMP_I 0x13 76 #define SHL_I 0x14 77 #define SHR_I 0x15 78 #define EI 0x16 79 #define SAR_I 0x17 80 #define TRAP 0x18 81 #define RETI 0x19 82 #define HALT 0x1A 83 //0x1B 84 #define LDSR 0x1C 85 #define STSR 0x1D 86 #define DI 0x1E 87 #define BSTR 0x1F //Special Bit String Inst 88 //0x20 - 0x27 // Lost to Branch Instructions 89 #define MOVEA 0x28 90 #define ADDI 0x29 91 #define JR 0x2A 92 #define JAL 0x2B 93 #define ORI 0x2C 94 #define ANDI 0x2D 95 #define XORI 0x2E 96 #define MOVHI 0x2F 97 #define LD_B 0x30 98 #define LD_H 0x31 99 //0x32 100 #define LD_W 0x33 101 #define ST_B 0x34 102 #define ST_H 0x35 103 //0x36 104 #define ST_W 0x37 105 #define IN_B 0x38 106 #define IN_H 0x39 107 #define CAXI 0x3A 108 #define IN_W 0x3B 109 #define OUT_B 0x3C 110 #define OUT_H 0x3D 111 #define FPP 0x3E //Special Float Inst 112 #define OUT_W 0x3F 113 114 115 // Branch Instructions ( Extended opcode only for Branch command) 116 // Common instrcutions commented out 117 118 #define BV 0x40 119 #define BL 0x41 120 #define BE 0x42 121 #define BNH 0x43 122 #define BN 0x44 123 #define BR 0x45 124 #define BLT 0x46 125 #define BLE 0x47 126 #define BNV 0x48 127 #define BNL 0x49 128 #define BNE 0x4A 129 #define BH 0x4B 130 #define BP 0x4C 131 #define NOP 0x4D 132 #define BGE 0x4E 133 #define BGT 0x4F 134 135 //#define BC 0x41 136 //#define BZ 0x42 137 //#define BNC 0x49 138 //#define BNZ 0x4A 139 140 // Bit String Subopcodes 141 #define SCH0BSU 0x00 142 #define SCH0BSD 0x01 143 #define SCH1BSU 0x02 144 #define SCH1BSD 0x03 145 146 #define ORBSU 0x08 147 #define ANDBSU 0x09 148 #define XORBSU 0x0A 149 #define MOVBSU 0x0B 150 #define ORNBSU 0x0C 151 #define ANDNBSU 0x0D 152 #define XORNBSU 0x0E 153 #define NOTBSU 0x0F 154 155 156 // Floating Point Subopcodes 157 #define CMPF_S 0x00 158 159 #define CVT_WS 0x02 160 #define CVT_SW 0x03 161 #define ADDF_S 0x04 162 #define SUBF_S 0x05 163 #define MULF_S 0x06 164 #define DIVF_S 0x07 165 #define XB 0x08 166 #define XH 0x09 167 #define REV 0x0A 168 #define TRNC_SW 0x0B 169 #define MPYHW 0x0C 170 171 } 172 #endif //DEFINE_H 173 174