1 // license:BSD-3-Clause 2 // copyright-holders:Barry Rodewald 3 /* 4 * Gravis Ultrasound ISA card 5 * 6 * Started: 28/01/2012 7 * 8 * I/O port map (info from the Gravis Ultrasound SDK documentation): 9 * Base port is 0x2X0 - where X is defined by a jumper 10 * 11 * MIDI: 12 * 0x3X0 - MIDI Control (read), MIDI Status (write) 13 * 0x3X1 - MIDI Transmit (write), MIDI Receive (read) 14 * MIDI operates identically to a 6850 UART 15 * 16 * Joystick: 17 * 0x201 - Joystick trigger timer (write), Joystick data (read) 18 * 19 * GF1 Synthesiser: 20 * 0x3X2 - Page register (voice select) 21 * 0x3X3 - Global Register select 22 * 0x3X4 - Global Data (low byte) 23 * 0x3X5 - Global Data (high byte) 24 * 0x2X6 - IRQ status register (read only, active high) 25 * 0x2X8 - Timer control register 26 * 0x2X9 - Timer data 27 * 0x3X7 - DRAM data (can be via DMA also) 28 * 29 * Board: 30 * 0x2X0: Mix control register (write only) 31 * 0x2XB: IRQ/DMA control register (write only) - dependant on mix control bit 6 32 * 0x2XF: Register controls (board rev 3.4+ only) 33 * 0x7X6: Board version (read only, board rev 3.7+ only) 34 * 35 * Mixer Control: 36 * 0x7X6: Control port (write only) 37 * 0x3X6: Data port (write only) 38 */ 39 40 #ifndef MAME_BUS_ISA_GUS_H 41 #define MAME_BUS_ISA_GUS_H 42 43 #pragma once 44 45 #include "isa.h" 46 #include "machine/6850acia.h" 47 48 49 //************************************************************************** 50 // TYPE DEFINITIONS 51 //************************************************************************** 52 53 // ======================> gf1_device 54 55 #define GF1_CLOCK 9878400 56 57 class gf1_device : 58 public acia6850_device, 59 public device_sound_interface 60 { 61 public: 62 struct gus_voice 63 { 64 uint8_t voice_ctrl; 65 uint16_t freq_ctrl; 66 uint32_t start_addr; 67 uint32_t end_addr; 68 uint8_t vol_ramp_rate; 69 uint8_t vol_ramp_start; 70 uint8_t vol_ramp_end; 71 uint16_t current_vol; 72 uint32_t current_addr; 73 uint8_t pan_position; 74 uint8_t vol_ramp_ctrl; 75 uint32_t vol_count; 76 bool rollover; 77 int16_t sample; // current sample data 78 }; 79 80 // construction/destruction 81 gf1_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); 82 txirq_handler()83 auto txirq_handler() { return m_txirq_handler.bind(); } rxirq_handler()84 auto rxirq_handler() { return m_rxirq_handler.bind(); } wave_irq_handler()85 auto wave_irq_handler() { return m_wave_irq_handler.bind(); } ramp_irq_handler()86 auto ramp_irq_handler() { return m_ramp_irq_handler.bind(); } timer1_irq_handler()87 auto timer1_irq_handler() { return m_timer1_irq_handler.bind(); } timer2_irq_handler()88 auto timer2_irq_handler() { return m_timer2_irq_handler.bind(); } sb_irq_handler()89 auto sb_irq_handler() { return m_sb_irq_handler.bind(); } dma_irq_handler()90 auto dma_irq_handler() { return m_dma_irq_handler.bind(); } drq1_handler()91 auto drq1_handler() { return m_drq1_handler.bind(); } drq2_handler()92 auto drq2_handler() { return m_drq2_handler.bind(); } nmi_handler()93 auto nmi_handler() { return m_nmi_handler.bind(); } 94 95 // current IRQ/DMA channel getters gf1_irq()96 uint8_t gf1_irq() { if(m_gf1_irq != 0) return m_gf1_irq; else return m_midi_irq; } // workaround for win95 loading dumb values midi_irq()97 uint8_t midi_irq() { if(m_irq_combine == 0) return m_midi_irq; else return m_gf1_irq; } dma_channel1()98 uint8_t dma_channel1() { return m_dma_channel1; } dma_channel2()99 uint8_t dma_channel2() { if(m_dma_combine == 0) return m_dma_channel2; else return m_dma_channel1; } 100 101 uint8_t global_reg_select_r(offs_t offset); 102 void global_reg_select_w(offs_t offset, uint8_t data); 103 uint8_t global_reg_data_r(offs_t offset); 104 void global_reg_data_w(offs_t offset, uint8_t data); 105 uint8_t dram_r(offs_t offset); 106 void dram_w(offs_t offset, uint8_t data); 107 uint8_t adlib_r(offs_t offset); 108 void adlib_w(offs_t offset, uint8_t data); 109 uint8_t adlib_cmd_r(offs_t offset); 110 void adlib_cmd_w(offs_t offset, uint8_t data); 111 uint8_t mix_ctrl_r(offs_t offset); 112 void mix_ctrl_w(offs_t offset, uint8_t data); 113 uint8_t stat_r(); 114 void stat_w(uint8_t data); 115 uint8_t sb_r(offs_t offset); 116 void sb_w(offs_t offset, uint8_t data); 117 void sb2x6_w(uint8_t data); 118 119 // DMA signals 120 uint8_t dack_r(int line); 121 void dack_w(int line,uint8_t data); 122 void eop_w(int state); 123 124 // optional information overrides 125 virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override; 126 virtual void sound_stream_update(sound_stream &stream, std::vector<read_stream_view> const &inputs, std::vector<write_stream_view> &outputs) override; 127 128 protected: 129 // voice-specific registers 130 gus_voice m_voice[32]; 131 132 // global registers (not voice-specific) 133 uint8_t m_dma_dram_ctrl; 134 uint16_t m_dma_start_addr; 135 uint32_t m_dram_addr; 136 uint8_t m_timer_ctrl; 137 uint8_t m_timer1_count; 138 uint8_t m_timer2_count; 139 uint8_t m_timer1_value; 140 uint8_t m_timer2_value; 141 uint16_t m_sampling_freq; 142 uint8_t m_sampling_ctrl; 143 uint8_t m_joy_trim_dac; 144 uint8_t m_reset; 145 uint8_t m_active_voices; 146 uint8_t m_irq_source; 147 148 void set_irq(uint8_t source, uint8_t voice); 149 void reset_irq(uint8_t source); 150 void update_volume_ramps(); 151 152 std::vector<uint8_t> m_wave_ram; 153 154 // device-level overrides 155 virtual void device_start() override; 156 virtual void device_reset() override; 157 virtual void device_stop() override; 158 virtual void device_clock_changed() override; 159 160 virtual void update_irq() override; 161 162 private: 163 // internal state 164 sound_stream* m_stream; 165 166 emu_timer* m_timer1; 167 emu_timer* m_timer2; 168 emu_timer* m_dmatimer; 169 emu_timer* m_voltimer; 170 171 uint8_t m_current_voice; 172 uint8_t m_current_reg; 173 //uint8_t m_port; 174 //uint8_t m_irq; 175 //uint8_t m_dma; 176 177 uint8_t m_adlib_cmd; 178 uint8_t m_mix_ctrl; 179 uint8_t m_gf1_irq; 180 uint8_t m_midi_irq; 181 uint8_t m_dma_channel1; 182 uint8_t m_dma_channel2; 183 uint8_t m_irq_combine; 184 uint8_t m_dma_combine; 185 uint8_t m_adlib_timer_cmd; 186 uint8_t m_adlib_timer1_enable; 187 uint8_t m_adlib_timer2_enable; 188 uint8_t m_adlib_status; 189 uint8_t m_adlib_data; 190 uint8_t m_voice_irq_fifo[32]; 191 uint8_t m_voice_irq_ptr; 192 uint8_t m_voice_irq_current; 193 uint8_t m_dma_16bit; // set by bit 6 of the DMA DRAM control reg 194 uint8_t m_statread; 195 uint8_t m_sb_data_2xc; 196 uint8_t m_sb_data_2xe; 197 uint8_t m_reg_ctrl; 198 uint8_t m_fake_adlib_status; 199 uint32_t m_dma_current; 200 uint16_t m_volume_table[4096]; 201 202 static const device_timer_id ADLIB_TIMER1 = 0; 203 static const device_timer_id ADLIB_TIMER2 = 1; 204 static const device_timer_id DMA_TIMER = 2; 205 static const device_timer_id VOL_RAMP_TIMER = 3; 206 207 int m_txirq; 208 int m_rxirq; 209 210 devcb_write_line m_txirq_handler; 211 devcb_write_line m_rxirq_handler; 212 devcb_write_line m_wave_irq_handler; 213 devcb_write_line m_ramp_irq_handler; 214 devcb_write_line m_timer1_irq_handler; 215 devcb_write_line m_timer2_irq_handler; 216 devcb_write_line m_sb_irq_handler; 217 devcb_write_line m_dma_irq_handler; 218 devcb_write_line m_drq1_handler; 219 devcb_write_line m_drq2_handler; 220 devcb_write_line m_nmi_handler; 221 }; 222 223 class isa16_gus_device : 224 public device_t, 225 public device_isa16_card_interface 226 { 227 public: 228 isa16_gus_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); 229 void set_irq(uint8_t source); 230 void reset_irq(uint8_t source); 231 void set_midi_irq(uint8_t source); 232 void reset_midi_irq(uint8_t source); 233 234 uint8_t board_r(offs_t offset); 235 uint8_t synth_r(offs_t offset); 236 void board_w(offs_t offset, uint8_t data); 237 void synth_w(offs_t offset, uint8_t data); 238 uint8_t adlib_r(offs_t offset); 239 void adlib_w(offs_t offset, uint8_t data); 240 uint8_t joy_r(offs_t offset); 241 void joy_w(offs_t offset, uint8_t data); 242 243 // DMA overrides 244 virtual uint8_t dack_r(int line) override; 245 virtual void dack_w(int line,uint8_t data) override; 246 virtual void eop_w(int state) override; 247 248 protected: 249 // device-level overrides 250 virtual void device_start() override; 251 virtual void device_reset() override; 252 virtual void device_stop() override; 253 254 // optional information overrides 255 virtual void device_add_mconfig(machine_config &config) override; 256 virtual ioport_constructor device_input_ports() const override; 257 258 private: 259 DECLARE_WRITE_LINE_MEMBER(midi_txirq); 260 DECLARE_WRITE_LINE_MEMBER(midi_rxirq); 261 DECLARE_WRITE_LINE_MEMBER(wavetable_irq); 262 DECLARE_WRITE_LINE_MEMBER(volumeramp_irq); 263 DECLARE_WRITE_LINE_MEMBER(timer1_irq); 264 DECLARE_WRITE_LINE_MEMBER(timer2_irq); 265 DECLARE_WRITE_LINE_MEMBER(sb_irq); 266 DECLARE_WRITE_LINE_MEMBER(dma_irq); 267 DECLARE_WRITE_LINE_MEMBER(drq1_w); 268 DECLARE_WRITE_LINE_MEMBER(drq2_w); 269 DECLARE_WRITE_LINE_MEMBER(nmi_w); 270 DECLARE_WRITE_LINE_MEMBER(write_acia_clock); 271 272 required_device<gf1_device> m_gf1; 273 274 uint8_t m_irq_status; 275 attotime m_joy_time; 276 }; 277 278 // device type definition 279 DECLARE_DEVICE_TYPE(GF1, gf1_device) 280 DECLARE_DEVICE_TYPE(ISA16_GUS, isa16_gus_device) 281 282 #endif // MAME_BUS_ISA_GUS_H 283