1 // license:BSD-3-Clause
2 // copyright-holders:David Haywood, Farfetch'd
3 /*** DRIVER INFO & NOTES ******************************************************
4 Speed Spin (c)1994 TCH
5 driver by David Haywood & Farfetch'd
6
7 Notes:
8 - To enter "easy" service mode, keep some input pressed during boot,
9 e.g. BUTTON 1.
10
11 TODO:
12 - Unknown Port Writes:
13 cpu #0 (PC=00000D88): unmapped port byte write to 00000001 = 02
14 cpu #0 (PC=00006974): unmapped port byte write to 00000010 = 10
15 cpu #0 (PC=00006902): unmapped port byte write to 00000010 = 20
16 etc.
17 - Writes to ROM regions
18 cpu #0 (PC=00001119): byte write to ROM 0000C8B9 = 01
19 cpu #0 (PC=00001119): byte write to ROM 0000C899 = 01
20 etc.
21
22 ******************************************************************************/
23
24 #include "emu.h"
25 #include "includes/speedspn.h"
26
27 #include "cpu/z80/z80.h"
28 #include "screen.h"
29 #include "speaker.h"
30
31
32 /*** README INFO **************************************************************
33
34 ROMSET: speedspn
35
36 Speed Spin
37 1994, TCH
38
39 PCB No: PR02/2
40 CPU : Z80 (6Mhz)
41 SOUND : Z80 (6Mhz), OKI M6295
42 RAM : 62256 (x1), 6264 (x1), 6116 (x6)
43 XTAL : 12.000MHz (near Z80's), 10.000MHz (near PLCC84)
44 DIP : 8 position (x2)
45 OTHER : TPC1020AFN-084C (PLCC84, Gfx controller)
46
47 ROMs Type Used C'sum
48 -------------------------------------------
49 TCH-SS1.u78 27C040 Main Program C246h
50 TCH-SS2.u96 27C512 Sound Program 5D04h
51 TCH-SS3.u95 27C040 Oki Samples 7340h
52 TCH-SS4.u70 27C010 \ ECD8h
53 TCH-SS5.u69 " | 9E7Bh
54 TCH-SS6.u60 " | E844h
55 TCH-SS7.u59 " | Gfx 3DDah
56 TCH-SS8.u39 " | A9B5h
57 TCH-SS9.u34 " / AB2Bh
58
59
60 ******************************************************************************/
61
irq_ack_r()62 uint8_t speedspn_state::irq_ack_r()
63 {
64 // I think this simply acknowledges the IRQ #0, it's read within the handler and the
65 // value is discarded
66 return 0;
67 }
68
rombank_w(uint8_t data)69 void speedspn_state::rombank_w(uint8_t data)
70 {
71 if (data > 8)
72 {
73 popmessage ("Unmapped Bank Write %02x", data);
74 data = 0;
75 }
76 m_prgbank->set_entry(data);
77 }
78
79 /*** SOUND RELATED ***********************************************************/
80
sound_w(uint8_t data)81 void speedspn_state::sound_w(uint8_t data)
82 {
83 m_soundlatch->write(data);
84 m_audiocpu->set_input_line(0, HOLD_LINE);
85 }
86
okibank_w(uint8_t data)87 void speedspn_state::okibank_w(uint8_t data)
88 {
89 m_okibank->set_entry(data & 3);
90 }
91
92 /*** MEMORY MAPS *************************************************************/
93
94 /* main cpu */
95
program_map(address_map & map)96 void speedspn_state::program_map(address_map &map)
97 {
98 map(0x0000, 0x7fff).rom();
99 map(0x8000, 0x87ff).ram().w(m_palette, FUNC(palette_device::write8)).share("palette"); /* RAM COLOUR */
100 map(0x8800, 0x8fff).ram().w(FUNC(speedspn_state::attram_w)).share("attram");
101 map(0x9000, 0x9fff).rw(FUNC(speedspn_state::vidram_r), FUNC(speedspn_state::vidram_w)); /* RAM FIX / RAM OBJECTS (selected by bit 0 of port 17) */
102 map(0xa000, 0xa7ff).ram();
103 map(0xa800, 0xafff).ram();
104 map(0xb000, 0xbfff).ram(); /* RAM PROGRAM */
105 map(0xc000, 0xffff).bankr("prgbank"); /* banked ROM */
106 }
107
io_map(address_map & map)108 void speedspn_state::io_map(address_map &map)
109 {
110 map.global_mask(0xff);
111 map(0x07, 0x07).w(FUNC(speedspn_state::display_disable_w));
112 map(0x10, 0x10).portr("SYSTEM");
113 map(0x11, 0x11).portr("P1");
114 map(0x12, 0x12).portr("P2").w(FUNC(speedspn_state::rombank_w));
115 map(0x13, 0x13).portr("DSW1").w(FUNC(speedspn_state::sound_w));
116 map(0x14, 0x14).portr("DSW2");
117 map(0x16, 0x16).r(FUNC(speedspn_state::irq_ack_r)); // @@@ could be watchdog, value is discarded
118 map(0x17, 0x17).w(FUNC(speedspn_state::vidram_bank_w));
119 }
120
121 /* sound cpu */
122
sound_map(address_map & map)123 void speedspn_state::sound_map(address_map &map)
124 {
125 map(0x0000, 0x7fff).rom();
126 map(0x8000, 0x87ff).ram();
127 map(0x9000, 0x9000).w(FUNC(speedspn_state::okibank_w));
128 map(0x9800, 0x9800).rw(m_oki, FUNC(okim6295_device::read), FUNC(okim6295_device::write));
129 map(0xa000, 0xa000).r(m_soundlatch, FUNC(generic_latch_8_device::read));
130 }
131
oki_map(address_map & map)132 void speedspn_state::oki_map(address_map &map)
133 {
134 map(0x00000, 0x1ffff).rom();
135 map(0x20000, 0x3ffff).bankr("okibank");
136 }
137
138 /*** INPUT PORT **************************************************************/
139
140 static INPUT_PORTS_START( speedspn )
141 PORT_START("SYSTEM")
142 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
143 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START2 )
144 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
145 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 )
146 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
147 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 )
148 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
149 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
150
151 PORT_START("P1")
152 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
153 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
154 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
155 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
156 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
157 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
158 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
159 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
160
161 PORT_START("P2")
162 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
163 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
164 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
165 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
166 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
167 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
168 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
169 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
170
171 PORT_START("DSW1")
172 PORT_DIPNAME( 0x0f, 0x0f, DEF_STR( Coin_A ) ) PORT_DIPLOCATION("SW1:8,7,6,5")
173 PORT_DIPSETTING( 0x01, DEF_STR( 5C_1C ) )
174 PORT_DIPSETTING( 0x04, DEF_STR( 4C_1C ) )
175 PORT_DIPSETTING( 0x07, DEF_STR( 3C_1C ) )
176 PORT_DIPSETTING( 0x00, "5 Coins/2 Credits" )
177 PORT_DIPSETTING( 0x0a, DEF_STR( 2C_1C ) )
178 PORT_DIPSETTING( 0x06, DEF_STR( 3C_2C ) )
179 PORT_DIPSETTING( 0x03, DEF_STR( 4C_3C ) )
180 PORT_DIPSETTING( 0x0f, DEF_STR( 1C_1C ) )
181 PORT_DIPSETTING( 0x02, DEF_STR( 4C_5C ) )
182 PORT_DIPSETTING( 0x05, "3 Coins/5 Credits" )
183 PORT_DIPSETTING( 0x09, DEF_STR( 2C_3C ) )
184 PORT_DIPSETTING( 0x0e, DEF_STR( 1C_2C ) )
185 PORT_DIPSETTING( 0x08, DEF_STR( 2C_5C ) )
186 PORT_DIPSETTING( 0x0d, DEF_STR( 1C_3C ) )
187 PORT_DIPSETTING( 0x0c, DEF_STR( 1C_4C ) )
188 PORT_DIPSETTING( 0x0b, DEF_STR( 1C_5C ) )
189 PORT_DIPNAME( 0xf0, 0xf0, DEF_STR( Coin_B ) ) PORT_DIPLOCATION("SW1:4,3,2,1")
190 PORT_DIPSETTING( 0x10, DEF_STR( 5C_1C ) )
191 PORT_DIPSETTING( 0x40, DEF_STR( 4C_1C ) )
192 PORT_DIPSETTING( 0x70, DEF_STR( 3C_1C ) )
193 PORT_DIPSETTING( 0x00, "5 Coins/2 Credits" )
194 PORT_DIPSETTING( 0xa0, DEF_STR( 2C_1C ) )
195 PORT_DIPSETTING( 0x60, DEF_STR( 3C_2C ) )
196 PORT_DIPSETTING( 0x30, DEF_STR( 4C_3C ) )
197 PORT_DIPSETTING( 0xf0, DEF_STR( 1C_1C ) )
198 PORT_DIPSETTING( 0x20, DEF_STR( 4C_5C ) )
199 PORT_DIPSETTING( 0x50, "3 Coins/5 Credits" )
200 PORT_DIPSETTING( 0x90, DEF_STR( 2C_3C ) )
201 PORT_DIPSETTING( 0xe0, DEF_STR( 1C_2C ) )
202 PORT_DIPSETTING( 0x80, DEF_STR( 2C_5C ) )
203 PORT_DIPSETTING( 0xd0, DEF_STR( 1C_3C ) )
204 PORT_DIPSETTING( 0xc0, DEF_STR( 1C_4C ) )
205 PORT_DIPSETTING( 0xb0, DEF_STR( 1C_5C ) )
206
207 PORT_START("DSW2")
208 PORT_DIPNAME( 0x01, 0x01, "World Cup" ) PORT_DIPLOCATION("SW2:8")
209 PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
210 PORT_DIPSETTING( 0x01, DEF_STR( On ) )
211 PORT_DIPNAME( 0x02, 0x02, "Backhand" ) PORT_DIPLOCATION("SW2:7")
212 PORT_DIPSETTING( 0x02, "Automatic" )
213 PORT_DIPSETTING( 0x00, "Manual" )
214 PORT_DIPNAME( 0x0c, 0x0c, "Points to Win" ) PORT_DIPLOCATION("SW2:6,5")
215 PORT_DIPSETTING( 0x0c, "11 Points and 1 Advantage" )
216 PORT_DIPSETTING( 0x08, "11 Points and 2 Advantage" )
217 PORT_DIPSETTING( 0x04, "21 Points and 1 Advantage" )
218 PORT_DIPSETTING( 0x00, "21 Points and 2 Advantage" )
219 PORT_DIPNAME( 0x30, 0x30, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:4,3")
220 PORT_DIPSETTING( 0x20, DEF_STR( Easy ) )
221 PORT_DIPSETTING( 0x30, DEF_STR( Normal ) )
222 PORT_DIPSETTING( 0x10, DEF_STR( Hard ) )
223 PORT_DIPSETTING( 0x00, DEF_STR( Hardest ) )
224 PORT_DIPNAME( 0x40, 0x40, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW2:2")
225 PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
226 PORT_DIPSETTING( 0x40, DEF_STR( On ) )
227 PORT_SERVICE_DIPLOC( 0x080, IP_ACTIVE_LOW, "SW2:1" )
228 INPUT_PORTS_END
229
230 /*** GFX DECODE **************************************************************/
231
232 static const gfx_layout speedspn_charlayout =
233 {
234 8,8,
235 RGN_FRAC(1,4),
236 4,
237 { RGN_FRAC(2,4), RGN_FRAC(3,4), RGN_FRAC(0,4), RGN_FRAC(1,4) },
238 { 0, 1, 2, 3, 4, 5, 6, 7 },
239 { 7*8, 6*8, 5*8, 4*8, 3*8, 2*8, 1*8, 0*8 },
240 8*8
241 };
242
243 static const gfx_layout speedspn_spritelayout =
244 {
245 16,16,
246 RGN_FRAC(1,2),
247 4,
248 { 4, 0, RGN_FRAC(1,2)+4, RGN_FRAC(1,2)+0 },
249 { 16*16+11, 16*16+10, 16*16+9, 16*16+8, 16*16+3, 16*16+2, 16*16+1, 16*16+0,
250 11, 10, 9, 8, 3, 2, 1, 0 },
251 { 8*16+7*16, 8*16+6*16, 8*16+5*16, 8*16+4*16, 8*16+3*16, 8*16+2*16, 8*16+1*16, 8*16+0*16,
252 7*16, 6*16, 5*16, 4*16, 3*16, 2*16, 1*16, 0*16 },
253 32*16
254 };
255
256
257 static GFXDECODE_START( gfx_speedspn )
258 GFXDECODE_ENTRY( "gfx1", 0, speedspn_charlayout, 0x000, 0x40 )
259 GFXDECODE_ENTRY( "gfx2", 0, speedspn_spritelayout, 0x000, 0x40 )
260 GFXDECODE_END
261
262 /*** MACHINE DRIVER **********************************************************/
263
machine_start()264 void speedspn_state::machine_start()
265 {
266 /* is this weird banking some form of protection? */
267 uint8_t *rom = memregion("maincpu")->base();
268 m_prgbank->configure_entry(0, &rom[0x28000]);
269 m_prgbank->configure_entry(1, &rom[0x14000]);
270 m_prgbank->configure_entry(2, &rom[0x1c000]);
271 m_prgbank->configure_entry(3, &rom[0x54000]);
272 m_prgbank->configure_entry(4, &rom[0x48000]);
273 m_prgbank->configure_entry(5, &rom[0x3c000]);
274 m_prgbank->configure_entry(6, &rom[0x18000]);
275 m_prgbank->configure_entry(7, &rom[0x4c000]);
276 m_prgbank->configure_entry(8, &rom[0x50000]);
277 m_prgbank->set_entry(0);
278
279 m_okibank->configure_entries(0, 4, memregion("oki")->base(), 0x20000);
280 m_okibank->set_entry(0);
281 }
282
283
speedspn(machine_config & config)284 void speedspn_state::speedspn(machine_config &config)
285 {
286 /* basic machine hardware */
287 Z80(config, m_maincpu, 6000000); /* 6 MHz */
288 m_maincpu->set_addrmap(AS_PROGRAM, &speedspn_state::program_map);
289 m_maincpu->set_addrmap(AS_IO, &speedspn_state::io_map);
290 m_maincpu->set_vblank_int("screen", FUNC(speedspn_state::irq0_line_hold));
291
292 Z80(config, m_audiocpu, 6000000); /* 6 MHz */
293 m_audiocpu->set_addrmap(AS_PROGRAM, &speedspn_state::sound_map);
294
295 /* video hardware */
296 screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER));
297 screen.set_refresh_hz(60);
298 screen.set_vblank_time(ATTOSECONDS_IN_USEC(0));
299 screen.set_size(64*8, 32*8);
300 screen.set_visarea(8*8, 56*8-1, 1*8, 31*8-1);
301 screen.set_screen_update(FUNC(speedspn_state::screen_update));
302 screen.set_palette(m_palette);
303
304 GFXDECODE(config, m_gfxdecode, m_palette, gfx_speedspn);
305 PALETTE(config, m_palette).set_format(palette_device::xRGB_444, 0x400);
306
307 /* sound hardware */
308 SPEAKER(config, "mono").front_center();
309
310 GENERIC_LATCH_8(config, m_soundlatch);
311
312 OKIM6295(config, m_oki, 1122000, okim6295_device::PIN7_HIGH); // clock frequency & pin 7 not verified
313 m_oki->add_route(ALL_OUTPUTS, "mono", 1.0);
314 m_oki->set_addrmap(0, &speedspn_state::oki_map);
315 }
316
317 /*** ROM LOADING *************************************************************/
318
319 ROM_START( speedspn )
320 ROM_REGION( 0x080000, "maincpu", 0 ) /* CPU1 code */
321 /* most of this is probably actually banked */
322 ROM_LOAD( "tch-ss1.u78", 0x00000, 0x080000, CRC(41b6b45b) SHA1(d969119959db4cc3be50f188bfa41e4b4896eaca) )
323
324 ROM_REGION( 0x10000, "audiocpu", 0 ) /* CPU2 code */
325 ROM_LOAD( "tch-ss2.u96", 0x00000, 0x10000, CRC(4611fd0c) SHA1(b49ad6a8be6ccfef0b2ed187fb3b008fb7eeb2b5) ) // FIRST AND SECOND HALF IDENTICAL
326
327 ROM_REGION( 0x080000, "oki", 0 ) /* Samples */
328 ROM_LOAD( "tch-ss3.u95", 0x00000, 0x080000, CRC(1c9deb5e) SHA1(89f01a8e8bdb0eee47e9195b312d2e65d41d3548) )
329
330 ROM_REGION( 0x80000, "gfx1", ROMREGION_INVERT ) /* GFX */
331 ROM_LOAD( "tch-ss4.u70", 0x00000, 0x020000, CRC(41517859) SHA1(3c5102e41c5a70e02ed88ea43ca63edf13f4c1b9) )
332 ROM_LOAD( "tch-ss5.u69", 0x20000, 0x020000, CRC(832b2f34) SHA1(7a3060869a9698c9ed4187b239a70e273de64e3c) )
333 ROM_LOAD( "tch-ss6.u60", 0x40000, 0x020000, CRC(f1fd7289) SHA1(8950ef58efdffc45d68152257ca36aedf5ddf677) )
334 ROM_LOAD( "tch-ss7.u59", 0x60000, 0x020000, CRC(c4958543) SHA1(c959b440801707c30a8968a1f44abe5442d03eff) )
335
336 ROM_REGION( 0x40000, "gfx2", ROMREGION_INVERT ) /* GFX */
337 ROM_LOAD( "tch-ss8.u39", 0x00000, 0x020000, CRC(2f27b16d) SHA1(7cc017fa08573f8a9d94d017abb987f8288bcd29) )
338 ROM_LOAD( "tch-ss9.u34", 0x20000, 0x020000, CRC(c372f8ec) SHA1(514bef0859c0adfd9cdd22864230fc83e9b1962d) )
339 ROM_END
340
341
342
343 /*** GAME DRIVERS ************************************************************/
344
345 GAME( 1994, speedspn, 0, speedspn, speedspn, speedspn_state, empty_init, ROT180, "TCH", "Speed Spin", MACHINE_SUPPORTS_SAVE )
346