1 // license:LGPL-2.1+ 2 // copyright-holders:Angelo Salese, Wilbert Pol 3 /***************************************************************************** 4 * 5 * includes/3do.h 6 * 7 ****************************************************************************/ 8 9 #ifndef MAME_INCLUDES_3DO_H 10 #define MAME_INCLUDES_3DO_H 11 12 #include "machine/nvram.h" 13 #include "machine/timer.h" 14 #include "screen.h" 15 16 17 class _3do_state : public driver_device 18 { 19 public: _3do_state(const machine_config & mconfig,device_type type,const char * tag)20 _3do_state(const machine_config &mconfig, device_type type, const char *tag) 21 : driver_device(mconfig, type, tag), 22 m_maincpu(*this, "maincpu"), 23 m_dram(*this, "dram"), 24 m_vram(*this, "vram"), 25 m_nvram(*this, "nvram"), 26 m_screen(*this, "screen"), 27 m_bank1(*this, "bank1") { } 28 29 void _3do(machine_config &config); 30 void _3do_pal(machine_config &config); 31 32 protected: 33 virtual void machine_start() override; 34 virtual void machine_reset() override; 35 virtual void video_start() override; 36 37 private: 38 struct SLOW2 { 39 /* 03180000 - 0318003f - configuration group */ 40 /* 03180040 - 0318007f - diagnostic UART */ 41 42 uint8_t cg_r_count; 43 uint8_t cg_w_count; 44 uint32_t cg_input; 45 uint32_t cg_output; 46 }; 47 48 49 struct MADAM { 50 uint32_t revision; /* 03300000 */ 51 uint32_t msysbits; /* 03300004 */ 52 uint32_t mctl; /* 03300008 */ 53 uint32_t sltime; /* 0330000c */ 54 uint32_t abortbits; /* 03300020 */ 55 uint32_t privbits; /* 03300024 */ 56 uint32_t statbits; /* 03300028 */ 57 uint32_t diag; /* 03300040 */ 58 59 uint32_t ccobctl0; /* 03300110 */ 60 uint32_t ppmpc; /* 03300120 */ 61 62 uint32_t regctl0; /* 03300130 */ 63 uint32_t regctl1; /* 03300134 */ 64 uint32_t regctl2; /* 03300138 */ 65 uint32_t regctl3; /* 0330013c */ 66 uint32_t xyposh; /* 03300140 */ 67 uint32_t xyposl; /* 03300144 */ 68 uint32_t linedxyh; /* 03300148 */ 69 uint32_t linedxyl; /* 0330014c */ 70 uint32_t dxyh; /* 03300150 */ 71 uint32_t dxyl; /* 03300154 */ 72 uint32_t ddxyh; /* 03300158 */ 73 uint32_t ddxyl; /* 0330015c */ 74 75 uint32_t pip[16]; /* 03300180-033001bc (W); 03300180-033001fc (R) */ 76 uint32_t fence[16]; /* 03300200-0330023c (W); 03300200-0330027c (R) */ 77 uint32_t mmu[64]; /* 03300300-033003fc */ 78 uint32_t dma[32][4]; /* 03300400-033005fc */ 79 uint32_t mult[40]; /* 03300600-0330069c */ 80 uint32_t mult_control; /* 033007f0-033007f4 */ 81 uint32_t mult_status; /* 033007f8 */ 82 }; 83 84 85 struct CLIO { 86 screen_device *screen; 87 88 uint32_t revision; /* 03400000 */ 89 uint32_t csysbits; /* 03400004 */ 90 uint32_t vint0; /* 03400008 */ 91 uint32_t vint1; /* 0340000c */ 92 uint32_t audin; /* 03400020 */ 93 uint32_t audout; /* 03400024 */ 94 uint32_t cstatbits; /* 03400028 */ 95 uint32_t wdog; /* 0340002c */ 96 uint32_t hcnt; /* 03400030 */ 97 uint32_t vcnt; /* 03400034 */ 98 uint32_t seed; /* 03400038 */ 99 uint32_t random; /* 0340004c */ 100 uint32_t irq0; /* 03400040 / 03400044 */ 101 uint32_t irq0_enable; /* 03400048 / 0340004c */ 102 uint32_t mode; /* 03400050 / 03400054 */ 103 uint32_t badbits; /* 03400058 */ 104 uint32_t spare; /* 0340005c */ 105 uint32_t irq1; /* 03400060 / 03400064 */ 106 uint32_t irq1_enable; /* 03400068 / 0340006c */ 107 uint32_t hdelay; /* 03400080 */ 108 uint32_t adbio; /* 03400084 */ 109 uint32_t adbctl; /* 03400088 */ 110 /* Timers */ 111 uint32_t timer_count[16];/* 034001** & 8 */ 112 uint32_t timer_backup[16]; /* 034001**+4 & 8 */ 113 uint64_t timer_ctrl; /* 03400200 */ 114 uint32_t slack; /* 03400220 */ 115 /* DMA */ 116 uint32_t dmareqdis; /* 03400308 */ 117 /* Expansion bus */ 118 uint32_t expctl; /* 03400400/03400404 */ 119 uint32_t type0_4; /* 03400408 */ 120 uint32_t dipir1; /* 03400410 */ 121 uint32_t dipir2; /* 03400414 */ 122 /* Bus signals */ 123 uint32_t sel; /* 03400500 - 0340053f */ 124 uint32_t poll; /* 03400540 - 0340057f */ 125 uint32_t cmdstat; /* 03400580 - 034005bf */ 126 uint32_t data; /* 034005c0 - 034005ff */ 127 /* DSPP */ 128 uint32_t semaphore; /* 034017d0 */ 129 uint32_t semaack; /* 034017d4 */ 130 uint32_t dsppdma; /* 034017e0 */ 131 uint32_t dspprst0; /* 034017e4 */ 132 uint32_t dspprst1; /* 034017e8 */ 133 uint32_t dspppc; /* 034017f4 */ 134 uint32_t dsppnr; /* 034017f8 */ 135 uint32_t dsppgw; /* 034017fc */ 136 uint32_t dsppn[0x400]; /* 03401800 - 03401bff DSPP N stack (32bit writes) */ 137 /* 03402000 - 034027ff DSPP N stack (16bit writes) */ 138 uint32_t dsppei[0x100]; /* 03403000 - 034030ff DSPP EI stack (32bit writes) */ 139 /* 03403400 - 034035ff DSPP EI stack (16bit writes) */ 140 uint32_t dsppeo[0x1f]; /* 03403800 - 0340381f DSPP EO stack (32bit reads) */ 141 /* 03403c00 - 03403c3f DSPP EO stack (32bit reads) */ 142 uint32_t dsppclkreload; /* 034039dc / 03403fbc */ 143 /* UNCLE */ 144 uint32_t unclerev; /* 0340c000 */ 145 uint32_t uncle_soft_rev; /* 0340c004 */ 146 uint32_t uncle_addr; /* 0340c008 */ 147 uint32_t uncle_rom; /* 0340c00c */ 148 }; 149 150 151 struct SVF { 152 uint32_t sport[512]; 153 uint32_t color; 154 }; 155 156 struct DSPP { 157 std::unique_ptr<uint16_t[]> N; 158 std::unique_ptr<uint16_t[]> EI; 159 std::unique_ptr<uint16_t[]> EO; 160 }; 161 162 required_device<cpu_device> m_maincpu; 163 required_shared_ptr<uint32_t> m_dram; 164 required_shared_ptr<uint32_t> m_vram; 165 required_device<nvram_device> m_nvram; 166 required_device<screen_device> m_screen; 167 required_memory_bank m_bank1; 168 169 SLOW2 m_slow2; 170 MADAM m_madam; 171 CLIO m_clio; 172 SVF m_svf; 173 DSPP m_dspp; 174 uint8_t m_nvmem[0x8000]; 175 176 // uint8_t m_video_bits[512]; 177 uint8_t nvarea_r(offs_t offset); 178 void nvarea_w(offs_t offset, uint8_t data); 179 uint32_t slow2_r(offs_t offset); 180 void slow2_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 181 uint32_t svf_r(offs_t offset); 182 void svf_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 183 uint32_t madam_r(offs_t offset); 184 void madam_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 185 uint32_t clio_r(offs_t offset); 186 void clio_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 187 uint32_t screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); 188 189 TIMER_DEVICE_CALLBACK_MEMBER( timer_x16_cb ); 190 191 void main_mem(address_map &map); 192 193 void m_slow2_init( void ); 194 void m_madam_init( void ); 195 void m_clio_init( void ); 196 197 void m_request_fiq(uint32_t irq_req, uint8_t type); 198 }; 199 200 201 #endif // MAME_INCLUDES_3DO_H 202