1 // license:BSD-3-Clause 2 // copyright-holders:Lukasz Markowski 3 #ifndef MAME_INCLUDES_CXHUMAX_H 4 #define MAME_INCLUDES_CXHUMAX_H 5 6 #pragma once 7 8 #include "cpu/arm7/arm7.h" 9 #include "cpu/arm7/arm7core.h" 10 #include "machine/intelfsh.h" 11 #include "machine/i2cmem.h" 12 #include "machine/terminal.h" 13 14 15 class cxhumax_state : public driver_device 16 { 17 public: 18 static constexpr unsigned MAX_CX_TIMERS = 16; 19 20 struct cx_timer_t 21 { 22 uint32_t value; 23 uint32_t limit; 24 uint32_t mode; 25 uint32_t timebase; 26 emu_timer *timer; 27 }; 28 29 struct cx_timer_regs_t 30 { 31 cx_timer_t timer[MAX_CX_TIMERS]; 32 uint32_t timer_irq; 33 }; 34 cxhumax_state(const machine_config & mconfig,device_type type,const char * tag)35 cxhumax_state(const machine_config &mconfig, device_type type, const char *tag) : 36 driver_device(mconfig, type, tag), 37 m_maincpu(*this, "maincpu"), 38 m_flash(*this, "flash"), 39 m_ram(*this, "ram"), 40 m_terminal(*this, "terminal"), 41 m_i2cmem(*this, "eeprom") 42 { 43 } 44 45 required_device<cpu_device> m_maincpu; 46 required_device<intel_28f320j3d_device> m_flash; 47 required_shared_ptr<uint32_t> m_ram; 48 required_device<generic_terminal_device> m_terminal; 49 50 void flash_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 51 uint32_t flash_r(offs_t offset, uint32_t mem_mask = ~0); 52 53 void cx_hsx_w(offs_t offset, uint32_t data); 54 uint32_t cx_hsx_r(offs_t offset); 55 56 void cx_romdescr_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 57 uint32_t cx_romdescr_r(offs_t offset); 58 void cx_isaromdescr_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 59 uint32_t cx_isaromdescr_r(offs_t offset); 60 void cx_isadescr_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 61 uint32_t cx_isadescr_r(offs_t offset); 62 void cx_rommap_w(offs_t offset, uint32_t data); 63 uint32_t cx_rommap_r(offs_t offset); 64 void cx_rommode_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 65 uint32_t cx_rommode_r(offs_t offset); 66 void cx_xoemask_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 67 uint32_t cx_xoemask_r(offs_t offset); 68 void cx_pci_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 69 uint32_t cx_pci_r(offs_t offset); 70 void cx_extdesc_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 71 uint32_t cx_extdesc_r(offs_t offset); 72 73 void cx_remap_w(offs_t offset, uint32_t data); 74 void cx_scratch_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 75 uint32_t cx_scratch_r(offs_t offset); 76 77 void cx_timers_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 78 uint32_t cx_timers_r(offs_t offset); 79 80 void cx_uart2_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 81 uint32_t cx_uart2_r(offs_t offset); 82 83 void cx_pll_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 84 uint32_t cx_pll_r(offs_t offset); 85 void cx_clkdiv_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 86 uint32_t cx_clkdiv_r(offs_t offset); 87 void cx_pllprescale_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 88 uint32_t cx_pllprescale_r(offs_t offset); 89 90 void cx_chipcontrol_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 91 uint32_t cx_chipcontrol_r(offs_t offset); 92 93 void cx_intctrl_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 94 uint32_t cx_intctrl_r(offs_t offset); 95 96 void cx_ss_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 97 uint32_t cx_ss_r(offs_t offset); 98 99 void cx_i2c0_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 100 uint32_t cx_i2c0_r(offs_t offset); 101 void cx_i2c1_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 102 uint32_t cx_i2c1_r(offs_t offset); 103 void cx_i2c2_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 104 uint32_t cx_i2c2_r(offs_t offset); 105 106 void cx_mc_cfg_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 107 uint32_t cx_mc_cfg_r(offs_t offset); 108 109 void cx_drm0_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 110 uint32_t cx_drm0_r(offs_t offset); 111 void cx_drm1_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 112 uint32_t cx_drm1_r(offs_t offset); 113 114 void cx_hdmi_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 115 uint32_t cx_hdmi_r(offs_t offset); 116 117 void cx_gxa_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 118 uint32_t cx_gxa_r(offs_t offset); 119 120 uint32_t dummy_flash_r(); 121 122 uint32_t m_romdescr_reg; 123 uint32_t m_isaromdescr_regs[0x0C/4]; 124 uint32_t m_isadescr_regs[0x10/4]; 125 uint32_t m_rommode_reg; 126 uint32_t m_xoemask_reg; 127 uint32_t m_pci_regs[0x08/4]; 128 uint32_t m_extdesc_regs[0x80/4]; 129 130 uint32_t m_scratch_reg; 131 cx_timer_regs_t m_timer_regs; 132 133 uint32_t m_uart2_regs[0x30/4]; 134 135 uint32_t m_pll_regs[0x14/4]; 136 uint32_t m_clkdiv_regs[0x18/4]; 137 uint32_t m_pllprescale_reg; 138 139 uint32_t m_intctrl_regs[0x38/4]; 140 141 uint32_t m_ss_regs[0x18/4]; 142 uint8_t m_ss_tx_fifo[8]; // 8 entries (size hardcoded to 8 bits per entry - TODO) 143 144 uint32_t m_i2c0_regs[0x20/4]; 145 uint32_t m_i2c1_regs[0x20/4]; 146 required_device<i2cmem_device> m_i2cmem; 147 uint32_t m_i2c2_regs[0x20/4]; 148 149 void i2cmem_start(); 150 void i2cmem_stop(); 151 uint8_t i2cmem_read_byte(int last); 152 void i2cmem_write_byte(uint8_t data); 153 154 uint32_t m_mccfg_regs[0x0C/4]; 155 156 uint32_t m_chipcontrol_regs[0x74/4]; 157 158 uint32_t m_drm0_regs[0xfc/4]; 159 uint32_t m_drm1_regs[0xfc/4]; 160 161 uint32_t m_hdmi_regs[0x400/4]; 162 163 uint32_t m_gxa_cmd_regs[0x130/4]; 164 virtual void machine_start() override; 165 virtual void machine_reset() override; 166 virtual void video_start() override; 167 uint32_t screen_update_cxhumax(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); 168 TIMER_CALLBACK_MEMBER(timer_tick); 169 void cxhumax(machine_config &config); 170 void cxhumax_map(address_map &map); 171 }; 172 173 #define INTDEST 0 // Interrupt destination (1=IRQ, 0=FIQ) 174 #define INTENABLE 1 // Enables the interrupt generation 175 #define INTIRQ 2 // Normal interrupt 176 #define INTFIQ 3 // Fast interrupt 177 #define INTSTATCLR 4 // Read: interrupt status, Write: clear pending interrupt 178 #define INTSTATSET 5 // Read: interrupt status, Write: sets a pending interrupt 179 #define INTGROUP1 0 180 #define INTGROUP2 1 181 182 #define INTREG(group, index) (((group) << 3) | (index)) 183 184 #define GXA_CMD_RW_REGISTER 0x00 185 #define GXA_CMD_QMARK 0x02 186 #define GXA_CMD_PALETTE_FETCH 0x03 187 #define GXA_CMD_VFILTER_COEFF_FETCH 0x04 188 #define GXA_CMD_HFILTER_COEFF_FETCH 0x05 189 #define GXA_CMD_BLT_21 0x21 190 #define GXA_CMD_BLT_23 0x23 191 #define GXA_CMD_BLT_25 0x25 192 #define GXA_CMD_BLT_27 0x27 193 #define GXA_CMD_BLT_2B 0x2b 194 #define GXA_CMD_BLT_2F 0x2f 195 #define GXA_CMD_LINE_30 0x30 196 #define GXA_CMD_LINE_32 0x32 197 #define GXA_CMD_BLT_31 0x31 198 #define GXA_CMD_BLT 0x33 199 #define GXA_CMD_LINE_34 0x34 200 #define GXA_CMD_LINE_36 0x36 201 #define GXA_CMD_BLT_35 0x35 202 #define GXA_CMD_BLT_37 0x37 203 #define GXA_CMD_LINE_3A 0x3a 204 #define GXA_CMD_BLT_3B 0x3b 205 #define GXA_CMD_LINE_3E 0x3e 206 #define GXA_CMD_BLT_3F 0x3f 207 #define GXA_CMD_SBLT_ABLEND 0x71 208 #define GXA_CMD_SBLT_ROP 0x7b 209 210 #define GXA_CMD_REG 0x07 211 212 #define GXA_CFG2_REG 0x3f 213 #define IRQ_STAT_QMARK 21 214 #define IRQ_EN_QMARK 17 215 216 #define INT_UART2_BIT (1<<1) 217 #define INT_TIMER_BIT (1<<7) 218 #define INT_PWM_BIT (1 << 14) 219 #define INT_PIO103_BIT (1 << 15) 220 221 #define PCI_CFG_ADDR_REG 0 222 #define PCI_CFG_DATA_REG 1 223 224 #define TIMER_VALUE 0 225 #define TIMER_LIMIT 1 226 #define TIMER_MODE 2 227 #define TIMER_TIMEBASE 3 228 229 #define UART_FIFO_REG 0 230 #define UART_IRQE_REG 1 231 #define UART_IRQE_TIDE_BIT (1<<6) 232 #define UART_BRDL_REG 0 233 #define UART_BRDU_REG 1 234 #define UART_FIFC_REG 2 235 #define UART_FRMC_REG 3 236 #define UART_FRMC_BDS_BIT (1<<7) 237 #define UART_STAT_REG 5 238 #define UART_STAT_TSR_BIT (1<<5) 239 #define UART_STAT_TID_BIT (1<<6) 240 241 #define SREG_MPG_0_INTFRAC_REG 0 242 #define SREG_MPG_1_INTFRAC_REG 1 243 #define SREG_ARM_INTFRAC_REG 2 244 #define SREG_MEM_INTFRAC_REG 3 245 #define SREG_USB_INTFRAC_REG 4 246 247 #define SREG_DIV_0_REG 0 248 #define SREG_DIV_1_REG 1 249 #define SREG_DIV_2_REG 2 250 #define SREG_DIV_3_REG 3 251 #define SREG_DIV_4_REG 4 252 #define SREG_DIV_5_REG 5 253 254 #define PIN_CONFIG_0_REG 0 // Pin Configuration 0 Register 255 #define SREG_MODE_REG 3 // SREG Mode Register 256 #define PIN_ALT_FUNC_REG 4 // Alternate Pin Function Select Register 257 #define PLL_LOCK_STAT_0_REG 9 // Resource Lock Register 258 #define PLL_IO_CTL_REG 20 // IO Control Register 259 #define SREG_TEST_REG 28 // Test Register 260 261 #define I2C_MODE_REG 0 262 #define I2C_CTRL_REG 1 263 #define I2C_STAT_REG 2 264 #define I2C_RDATA_REG 3 265 266 #define I2C_WACK_BIT (1<<1) 267 #define I2C_INT_BIT (1<<0) 268 269 #define SS_CNTL_REG 0 270 #define SS_FIFC_REG 1 271 #define SS_BAUD_REG 2 272 #define SS_FIFO_REG 4 273 #define SS_STAT_REG 5 274 275 #define MC_CFG0 0 276 #define MC_CFG1 1 277 #define MC_CFG2 2 278 279 #define DRM_ACTIVE_X_REG 1 280 #define DRM_ACTIVE_Y_REG 2 281 #define DRM_BCKGND_REG 3 282 #define DRM_OSD_PTR_REG 32 283 284 #endif // MAME_INCLUDES_CXHUMAX_H 285