1 // license:LGPL-2.1+ 2 // copyright-holders:Angelo Salese, Olivier Galibert, David Haywood, Samuele Zannoli, R. Belmont, ElSemi 3 /* 4 5 dc.h - Sega Dreamcast includes 6 7 */ 8 #ifndef MAME_INCLUDES_DC_H 9 #define MAME_INCLUDES_DC_H 10 11 #pragma once 12 13 #include "video/powervr2.h" 14 #include "machine/naomig1.h" 15 #include "machine/maple-dc.h" 16 #include "machine/timer.h" 17 #include "sound/aica.h" 18 19 class dc_state : public driver_device 20 { 21 public: dc_state(const machine_config & mconfig,device_type type,const char * tag)22 dc_state(const machine_config &mconfig, device_type type, const char *tag) 23 : driver_device(mconfig, type, tag), 24 dc_framebuffer_ram(*this, "frameram"), 25 dc_texture_ram(*this, "dc_texture_ram"), 26 dc_sound_ram(*this, "dc_sound_ram"), 27 dc_ram(*this, "dc_ram"), 28 m_maincpu(*this, "maincpu"), 29 m_soundcpu(*this, "soundcpu"), 30 m_powervr2(*this, "powervr2"), 31 m_maple(*this, "maple_dc"), 32 m_naomig1(*this, "rom_board"), 33 m_aica(*this, "aica") { } 34 35 required_shared_ptr<uint64_t> dc_framebuffer_ram; // '32-bit access area' 36 required_shared_ptr<uint64_t> dc_texture_ram; // '64-bit access area' 37 38 required_shared_ptr<uint16_t> dc_sound_ram; 39 required_shared_ptr<uint64_t> dc_ram; 40 41 /* machine related */ 42 uint32_t dc_sysctrl_regs[0x200/4]; 43 uint32_t g1bus_regs[0x100/4]; // DC-only 44 uint32_t g2bus_regs[0x100/4]; 45 uint8_t m_armrst; 46 47 struct { 48 uint32_t g2_addr; 49 uint32_t root_addr; 50 uint32_t size; 51 uint8_t dir; 52 uint8_t flag; 53 uint8_t indirect; 54 uint8_t start; 55 uint8_t sel; 56 } m_g2_dma[4]; 57 58 virtual void machine_start() override; 59 virtual void machine_reset() override; 60 TIMER_CALLBACK_MEMBER(g2_dma_irq); 61 TIMER_CALLBACK_MEMBER(ch2_dma_irq); 62 uint32_t dc_aica_reg_r(offs_t offset, uint32_t mem_mask = ~0); 63 void dc_aica_reg_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 64 uint32_t dc_arm_aica_r(offs_t offset); 65 void dc_arm_aica_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 66 void g2_dma_execute(address_space &space, int channel); 67 inline int decode_reg32_64(uint32_t offset, uint64_t mem_mask, uint64_t *shift); 68 inline int decode_reg3216_64(uint32_t offset, uint64_t mem_mask, uint64_t *shift); 69 int dc_compute_interrupt_level(); 70 void dc_update_interrupt_status(); 71 inline int decode_reg_64(uint32_t offset, uint64_t mem_mask, uint64_t *shift); 72 uint64_t dc_sysctrl_r(offs_t offset, uint64_t mem_mask = ~0); 73 void dc_sysctrl_w(offs_t offset, uint64_t data, uint64_t mem_mask = ~0); 74 uint64_t dc_gdrom_r(offs_t offset, uint64_t mem_mask = ~0); 75 void dc_gdrom_w(offs_t offset, uint64_t data, uint64_t mem_mask = ~0); 76 uint64_t dc_g2_ctrl_r(offs_t offset, uint64_t mem_mask = ~0); 77 void dc_g2_ctrl_w(address_space &space, offs_t offset, uint64_t data, uint64_t mem_mask = ~0); 78 uint64_t dc_modem_r(offs_t offset, uint64_t mem_mask = ~0); 79 void dc_modem_w(offs_t offset, uint64_t data, uint64_t mem_mask = ~0); 80 void g1_irq(uint8_t data); 81 void pvr_irq(uint8_t data); 82 void maple_irq(uint8_t data); 83 uint16_t soundram_r(offs_t offset); 84 void soundram_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0); 85 DECLARE_WRITE_LINE_MEMBER(aica_irq); 86 DECLARE_WRITE_LINE_MEMBER(sh4_aica_irq); 87 DECLARE_WRITE_LINE_MEMBER(external_irq); 88 89 90 required_device<sh4_base_device> m_maincpu; 91 required_device<cpu_device> m_soundcpu; 92 required_device<powervr2_device> m_powervr2; 93 required_device<maple_dc_device> m_maple; 94 optional_device<naomi_g1_device> m_naomig1; 95 required_device<aica_device> m_aica; 96 97 void generic_dma(uint32_t main_adr, void *dma_ptr, uint32_t length, uint32_t size, bool to_mainram); 98 TIMER_DEVICE_CALLBACK_MEMBER(dc_scanline); 99 DECLARE_MACHINE_RESET(dc_console); 100 101 void naomi_aw_base(machine_config &config); 102 void aica_map(address_map &map); 103 void dc_audio_map(address_map &map); 104 }; 105 106 /*--------- Ch2-DMA Control Registers ----------*/ 107 #define SB_C2DSTAT ((0x005f6800-0x005f6800)/4) 108 #define SB_C2DLEN ((0x005f6804-0x005f6800)/4) 109 #define SB_C2DST ((0x005f6808-0x005f6800)/4) 110 /*-------- Sort-DMA Control Registers ----------*/ 111 #define SB_SDSTAW ((0x005f6810-0x005f6800)/4) 112 #define SB_SDBAAW ((0x005f6814-0x005f6800)/4) 113 #define SB_SDWLT ((0x005f6818-0x005f6800)/4) 114 #define SB_SDLAS ((0x005f681c-0x005f6800)/4) 115 #define SB_SDST ((0x005f6820-0x005f6800)/4) 116 /*-- DDT I/F Block & System Control Registers --*/ 117 #define SB_DBREQM ((0x005f6840-0x005f6800)/4) 118 #define SB_BAVLWC ((0x005f6844-0x005f6800)/4) 119 #define SB_C2DPRYC ((0x005f6848-0x005f6800)/4) 120 #define SB_C2DMAXL ((0x005f684c-0x005f6800)/4) 121 #define SB_TFREM ((0x005f6880-0x005f6800)/4) 122 #define SB_LMMODE0 ((0x005f6884-0x005f6800)/4) 123 #define SB_LMMODE1 ((0x005f6888-0x005f6800)/4) 124 #define SB_FFST ((0x005f688c-0x005f6800)/4) 125 #define SB_SFRES ((0x005f6890-0x005f6800)/4) 126 #define SB_SBREV ((0x005f689c-0x005f6800)/4) 127 #define SB_RBSPLT ((0x005f68a0-0x005f6800)/4) 128 /*-------- Interrupt Control Registers ---------*/ 129 #define SB_ISTNRM ((0x005f6900-0x005f6800)/4) 130 #define SB_ISTEXT ((0x005f6904-0x005f6800)/4) 131 #define SB_ISTERR ((0x005f6908-0x005f6800)/4) 132 #define SB_IML2NRM ((0x005f6910-0x005f6800)/4) 133 #define SB_IML2EXT ((0x005f6914-0x005f6800)/4) 134 #define SB_IML2ERR ((0x005f6918-0x005f6800)/4) 135 #define SB_IML4NRM ((0x005f6920-0x005f6800)/4) 136 #define SB_IML4EXT ((0x005f6924-0x005f6800)/4) 137 #define SB_IML4ERR ((0x005f6928-0x005f6800)/4) 138 #define SB_IML6NRM ((0x005f6930-0x005f6800)/4) 139 #define SB_IML6EXT ((0x005f6934-0x005f6800)/4) 140 #define SB_IML6ERR ((0x005f6938-0x005f6800)/4) 141 #define SB_PDTNRM ((0x005f6940-0x005f6800)/4) 142 #define SB_PDTEXT ((0x005f6944-0x005f6800)/4) 143 #define SB_G2DTNRM ((0x005f6950-0x005f6800)/4) 144 #define SB_G2DTEXT ((0x005f6954-0x005f6800)/4) 145 146 147 /*-------- Maple-DMA Control Registers ---------*/ 148 #define SB_MDSTAR ((0x005f6c04-0x005f6c00)/4) 149 #define SB_MDTSEL ((0x005f6c10-0x005f6c00)/4) 150 #define SB_MDEN ((0x005f6c14-0x005f6c00)/4) 151 #define SB_MDST ((0x005f6c18-0x005f6c00)/4) 152 /*---- Maple I/F Block HW Control Registers ----*/ 153 #define SB_MSYS ((0x005f6c80-0x005f6c00)/4) 154 #define SB_MST ((0x005f6c84-0x005f6c00)/4) 155 #define SB_MSHTCL ((0x005f6c88-0x005f6c00)/4) 156 #define SB_MDAPRO ((0x005f6c8c-0x005f6c00)/4) 157 #define SB_MMSEL ((0x005f6ce8-0x005f6c00)/4) 158 /*-------- Maple-DMA Debug Registers -----------*/ 159 #define SB_MTXDAD ((0x005f6cf4-0x005f6c00)/4) 160 #define SB_MRXDAD ((0x005f6cf8-0x005f6c00)/4) 161 #define SB_MRXDBD ((0x005f6cfc-0x005f6c00)/4) 162 163 /*--------- GD-DMA Control Registers -----------*/ 164 #define SB_GDSTAR ((0x005f7404-0x005f7400)/4) 165 #define SB_GDLEN ((0x005f7408-0x005f7400)/4) 166 #define SB_GDDIR ((0x005f740c-0x005f7400)/4) 167 #define SB_GDEN ((0x005f7414-0x005f7400)/4) 168 #define SB_GDST ((0x005f7418-0x005f7400)/4) 169 /*----- G1 I/F Block HW Control Registers ------*/ 170 #define SB_G1RRC ((0x005f7480-0x005f7400)/4) 171 #define SB_G1RWC ((0x005f7484-0x005f7400)/4) 172 #define SB_G1FRC ((0x005f7488-0x005f7400)/4) 173 #define SB_G1FWC ((0x005f748c-0x005f7400)/4) 174 #define SB_G1CRC ((0x005f7490-0x005f7400)/4) 175 #define SB_G1CWC ((0x005f7494-0x005f7400)/4) 176 #define SB_G1GDRC ((0x005f74a0-0x005f7400)/4) 177 #define SB_G1GDWC ((0x005f74a4-0x005f7400)/4) 178 #define SB_G1SYSM ((0x005f74b0-0x005f7400)/4) 179 #define SB_G1CRDYC ((0x005f74b4-0x005f7400)/4) 180 #define SB_GDAPRO ((0x005f74b8-0x005f7400)/4) 181 182 /*-------- BIOS security Registers ---------*/ 183 #define SB_SECUR_EADR ((0x005f74e4-0x005f7400)/4) 184 #define SB_SECUR_STATE ((0x005f74ec-0x005f7400)/4) 185 /*---------- GD-DMA Debug Registers ------------*/ 186 #define SB_GDSTARD ((0x005f74f4-0x005f7400)/4) 187 #define SB_GDLEND ((0x005f74f8-0x005f7400)/4) 188 189 /*-------- Wave DMA Control Registers ----------*/ 190 #define SB_ADSTAG ((0x005f7800-0x005f7800)/4) 191 #define SB_ADSTAR ((0x005f7804-0x005f7800)/4) 192 #define SB_ADLEN ((0x005f7808-0x005f7800)/4) 193 #define SB_ADDIR ((0x005f780c-0x005f7800)/4) 194 #define SB_ADTSEL ((0x005f7810-0x005f7800)/4) 195 #define SB_ADTRG SB_ADTSEL 196 #define SB_ADEN ((0x005f7814-0x005f7800)/4) 197 #define SB_ADST ((0x005f7818-0x005f7800)/4) 198 #define SB_ADSUSP ((0x005f781c-0x005f7800)/4) 199 200 /*----- External 1 DMA Control Registers -------*/ 201 #define SB_E1STAG ((0x005f7820-0x005f7800)/4) 202 #define SB_E1STAR ((0x005f7824-0x005f7800)/4) 203 #define SB_E1LEN ((0x005f7828-0x005f7800)/4) 204 #define SB_E1DIR ((0x005f782c-0x005f7800)/4) 205 #define SB_E1TSEL ((0x005f7830-0x005f7800)/4) 206 #define SB_E1TRG SB_E1TSEL 207 #define SB_E1EN ((0x005f7834-0x005f7800)/4) 208 #define SB_E1ST ((0x005f7838-0x005f7800)/4) 209 #define SB_E1SUSP ((0x005f783c-0x005f7800)/4) 210 211 /*----- External 2 DMA Control Registers -------*/ 212 #define SB_E2STAG ((0x005f7840-0x005f7800)/4) 213 #define SB_E2STAR ((0x005f7844-0x005f7800)/4) 214 #define SB_E2LEN ((0x005f7848-0x005f7800)/4) 215 #define SB_E2DIR ((0x005f784c-0x005f7800)/4) 216 #define SB_E2TSEL ((0x005f7850-0x005f7800)/4) 217 #define SB_E2TRG SB_E2TSEL 218 #define SB_E2EN ((0x005f7854-0x005f7800)/4) 219 #define SB_E2ST ((0x005f7858-0x005f7800)/4) 220 #define SB_E2SUSP ((0x005f785c-0x005f7800)/4) 221 222 /*------- Debug DMA Control Registers ----------*/ 223 #define SB_DDSTAG ((0x005f7860-0x005f7800)/4) 224 #define SB_DDSTAR ((0x005f7864-0x005f7800)/4) 225 #define SB_DDLEN ((0x005f7868-0x005f7800)/4) 226 #define SB_DDDIR ((0x005f786c-0x005f7800)/4) 227 #define SB_DDTSEL ((0x005f7870-0x005f7800)/4) 228 #define SB_DDTRG SB_DDTSEL 229 #define SB_DDEN ((0x005f7874-0x005f7800)/4) 230 #define SB_DDST ((0x005f7878-0x005f7800)/4) 231 #define SB_DDSUSP ((0x005f787c-0x005f7800)/4) 232 /*----- G2 I/F Block HW Control Registers ------*/ 233 #define SB_G2ID ((0x005f7880-0x005f7800)/4) 234 #define SB_G2DSTO ((0x005f7890-0x005f7800)/4) 235 #define SB_G2TRTO ((0x005f7894-0x005f7800)/4) 236 #define SB_G2MDMTO ((0x005f7898-0x005f7800)/4) 237 #define SB_G2MDMW ((0x005f789c-0x005f7800)/4) 238 #define SB_G2APRO ((0x005f78bc-0x005f7800)/4) 239 240 /*---------- G2 DMA Debug Registers ------------*/ 241 #define SB_ADSTAGD ((0x005f78c0-0x005f7800)/4) 242 #define SB_ADSTARD ((0x005f78c4-0x005f7800)/4) 243 #define SB_ADLEND ((0x005f78c8-0x005f7800)/4) 244 #define SB_E1STAGD ((0x005f78d0-0x005f7800)/4) 245 #define SB_E1STARD ((0x005f78d4-0x005f7800)/4) 246 #define SB_E1LEND ((0x005f78d8-0x005f7800)/4) 247 #define SB_E2STAGD ((0x005f78e0-0x005f7800)/4) 248 #define SB_E2STARD ((0x005f78e4-0x005f7800)/4) 249 #define SB_E2LEND ((0x005f78e8-0x005f7800)/4) 250 #define SB_DDSTAGD ((0x005f78f0-0x005f7800)/4) 251 #define SB_DDSTARD ((0x005f78f4-0x005f7800)/4) 252 #define SB_DDLEND ((0x005f78f8-0x005f7800)/4) 253 254 #define RTC1 ((0x00710000-0x00710000)/4) 255 #define RTC2 ((0x00710004-0x00710000)/4) 256 #define RTC3 ((0x00710008-0x00710000)/4) 257 258 259 /* ------------- normal interrupts ------------- */ 260 #define IST_EOR_VIDEO 0x00000001 261 #define IST_EOR_ISP 0x00000002 262 #define IST_EOR_TSP 0x00000004 263 #define IST_VBL_IN 0x00000008 264 #define IST_VBL_OUT 0x00000010 265 #define IST_HBL_IN 0x00000020 266 #define IST_EOXFER_YUV 0x00000040 267 #define IST_EOXFER_OPLST 0x00000080 268 #define IST_EOXFER_OPMV 0x00000100 269 #define IST_EOXFER_TRLST 0x00000200 270 #define IST_EOXFER_TRMV 0x00000400 271 #define IST_DMA_PVR 0x00000800 272 #define IST_DMA_MAPLE 0x00001000 273 #define IST_DMA_MAPLEVB 0x00002000 274 #define IST_DMA_GDROM 0x00004000 275 #define IST_DMA_AICA 0x00008000 276 #define IST_DMA_EXT1 0x00010000 277 #define IST_DMA_EXT2 0x00020000 278 #define IST_DMA_DEV 0x00040000 279 #define IST_DMA_CH2 0x00080000 280 #define IST_DMA_SORT 0x00100000 281 #define IST_EOXFER_PTLST 0x00200000 282 #define IST_G1G2EXTSTAT 0x40000000 283 #define IST_ERROR 0x80000000 284 /* ------------ external interrupts ------------ */ 285 #define IST_EXT_EXTERNAL 0x00000008 286 #define IST_EXT_MODEM 0x00000004 287 #define IST_EXT_AICA 0x00000002 288 #define IST_EXT_GDROM 0x00000001 289 /* -------------- error interrupts ------------- */ 290 #define IST_ERR_ISP_LIMIT 0x00000004 291 #define IST_ERR_PVRIF_ILL_ADDR 0x00000040 292 293 #endif // MAME_INCLUDES_DC_H 294