1 // license:BSD-3-Clause 2 // copyright-holders:Ryan Holtz, R. Belmont 3 #pragma once 4 5 #ifndef MAME_INCLUDES_NDS_H 6 #define MAME_INCLUDES_NDS_H 7 8 #include "cpu/arm7/arm7.h" 9 #include "cpu/arm7/arm7core.h" 10 #include "machine/bankdev.h" 11 #include "machine/timer.h" 12 13 class nds_state : public driver_device 14 { 15 public: nds_state(const machine_config & mconfig,device_type type,const char * tag)16 nds_state(const machine_config &mconfig, device_type type, const char *tag) 17 : driver_device(mconfig, type, tag), 18 m_arm7(*this, "arm7"), 19 m_arm9(*this, "arm9"), 20 m_firmware(*this, "firmware"), 21 m_arm7wrambnk(*this, "nds7wram"), 22 m_arm9wrambnk(*this, "nds9wram"), 23 m_arm7ram(*this, "arm7ram") 24 { } 25 26 void nds(machine_config &config); 27 28 private: 29 void machine_start() override; 30 void machine_reset() override; 31 32 // ARM7 33 uint32_t arm7_io_r(offs_t offset, uint32_t mem_mask = ~0); 34 void arm7_io_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 35 36 // ARM9 37 uint32_t arm9_io_r(offs_t offset, uint32_t mem_mask = ~0); 38 void arm9_io_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 39 40 uint32_t wram_first_half_r(offs_t offset); 41 uint32_t wram_second_half_r(offs_t offset); 42 void wram_first_half_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 43 void wram_second_half_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 44 uint32_t wram_arm7mirror_r(offs_t offset); 45 void wram_arm7mirror_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 46 47 void nds7_wram_map(address_map &map); 48 void nds9_wram_map(address_map &map); 49 void nds_arm7_map(address_map &map); 50 void nds_arm9_map(address_map &map); 51 52 required_device<arm7_cpu_device> m_arm7; 53 required_device<arm946es_cpu_device> m_arm9; 54 required_region_ptr<uint32_t> m_firmware; 55 required_device<address_map_bank_device> m_arm7wrambnk, m_arm9wrambnk; 56 required_shared_ptr<uint32_t> m_arm7ram; 57 58 enum { 59 TIMER_OFFSET = (0x100/4), 60 RTC_OFFSET = (0x138/4), 61 IPCSYNC_OFFSET = (0x180/4), 62 AUX_SPI_CNT_OFFSET = (0x1a0/4), 63 GAMECARD_BUS_CTRL_OFFSET = (0x1a4/4), 64 GAMECARD_DATA_OFFSET = (0x1a8/4), 65 GAMECARD_DATA_2_OFFSET = (0x1ac/4), 66 SPI_CTRL_OFFSET = (0x1c0/4), 67 IME_OFFSET = (0x208/4), 68 IE_OFFSET = (0x210/4), 69 IF_OFFSET = (0x214/4), 70 WRAMSTAT_OFFSET = (0x241/4), 71 VRAMCNT_A_OFFSET = (0x240/4), 72 WRAMCNT_OFFSET = (0x244/4), 73 VRAMCNT_H_OFFSET = (0x248/4), 74 POSTFLG_OFFSET = (0x300/4), 75 GAMECARD_DATA_IN_OFFSET = (0x100010/4), 76 POSTFLG_PBF_SHIFT = 0, 77 POSTFLG_RAM_SHIFT = 1, 78 POSTFLG_PBF_MASK = (1 << POSTFLG_PBF_SHIFT), 79 POSTFLG_RAM_MASK = (1 << POSTFLG_RAM_SHIFT), 80 GAMECARD_DATA_READY = (1 << 23), 81 GAMECARD_BLOCK_BUSY = (1 << 31) 82 }; 83 84 uint32_t m_arm7_postflg; 85 uint32_t m_arm9_postflg; 86 uint32_t m_gamecard_ctrl, m_cartdata_len; 87 uint32_t m_ime[2], m_ie[2], m_if[2]; 88 uint16_t m_arm7_ipcsync, m_arm9_ipcsync, m_spicnt; 89 uint8_t m_WRAM[0x8000]; 90 uint8_t m_wramcnt; 91 uint8_t m_vramcnta, m_vramcntb, m_vramcntc, m_vramcntd, m_vramcnte, m_vramcntf, m_vramcntg, m_vramcnth, m_vramcnti; 92 bool m_arm7halted; 93 94 // DMA 95 emu_timer *m_dma_timer[8]; 96 //uint32_t m_dma_src[8]; 97 //uint32_t m_dma_dst[8]; 98 //uint16_t m_dma_cnt[8]; 99 100 // Timers 101 uint32_t m_timer_regs[8]; 102 uint16_t m_timer_reload[8]; 103 int m_timer_recalc[8]; 104 double m_timer_hz[8]; 105 106 emu_timer *m_tmr_timer[8], *m_irq_timer; 107 108 TIMER_CALLBACK_MEMBER(dma_complete); 109 TIMER_CALLBACK_MEMBER(timer_expire); 110 TIMER_CALLBACK_MEMBER(handle_irq); 111 112 void request_irq(int which_cpu, uint32_t int_type); 113 void dma_exec(int ch); 114 }; 115 116 #endif // INCLUDES_NDS_H 117