1 // license:BSD-3-Clause
2 // copyright-holders:Krzysztof Strzecha
3 /***************************************************************************
4
5 machine.c
6
7 Functions to emulate general aspects of PMD-85 (RAM, ROM, interrupts,
8 I/O ports)
9
10 Krzysztof Strzecha
11
12 ***************************************************************************/
13
14 #include "emu.h"
15 #include "includes/pmd85.h"
16
17
18
19 enum {PMD85_LED_1 = 0, PMD85_LED_2, PMD85_LED_3};
20 enum {PMD85_1, PMD85_2, PMD85_2A, PMD85_2B, PMD85_3, ALFA, MATO, C2717};
21
22
23
pmd851_update_memory()24 void pmd85_state::pmd851_update_memory()
25 {
26 address_space& space = m_maincpu->space(AS_PROGRAM);
27 uint8_t *ram = m_ram->pointer();
28
29 if (m_startup_mem_map)
30 {
31 space.unmap_write(0x0000, 0x0fff);
32 space.nop_write(0x1000, 0x1fff);
33 space.unmap_write(0x2000, 0x2fff);
34 space.nop_write(0x3000, 0x3fff);
35
36 space.nop_read(0x1000, 0x1fff);
37 space.nop_read(0x3000, 0x3fff);
38
39 m_bank[1]->set_base(m_rom);
40 m_bank[3]->set_base(m_rom);
41 m_bank[5]->set_base(ram + 0xc000);
42
43 m_bank[6]->set_base(m_rom);
44 m_bank[7]->set_base(m_rom);
45 m_bank[8]->set_base(ram + 0xc000);
46 }
47 else
48 {
49 space.install_write_bank(0x0000, 0x0fff, "bank1");
50 space.install_write_bank(0x1000, 0x1fff, "bank2");
51 space.install_write_bank(0x2000, 0x2fff, "bank3");
52 space.install_write_bank(0x3000, 0x3fff, "bank4");
53 space.install_write_bank(0x4000, 0x7fff, "bank5");
54
55 space.install_read_bank(0x1000, 0x1fff, "bank2");
56 space.install_read_bank(0x3000, 0x3fff, "bank4");
57
58 m_bank[1]->set_base(ram);
59 m_bank[2]->set_base(ram + 0x1000);
60 m_bank[3]->set_base(ram + 0x2000);
61 m_bank[4]->set_base(ram + 0x3000);
62 m_bank[5]->set_base(ram + 0x4000);
63 }
64 }
65
pmd852a_update_memory()66 void pmd85_state::pmd852a_update_memory()
67 {
68 address_space& space = m_maincpu->space(AS_PROGRAM);
69 uint8_t *ram = m_ram->pointer();
70
71 if (m_startup_mem_map)
72 {
73 space.unmap_write(0x0000, 0x0fff);
74 space.unmap_write(0x2000, 0x2fff);
75
76 m_bank[1]->set_base(m_rom);
77 m_bank[2]->set_base(ram + 0x9000);
78 m_bank[3]->set_base(m_rom);
79 m_bank[4]->set_base(ram + 0xb000);
80 m_bank[5]->set_base(ram + 0xc000);
81 m_bank[6]->set_base(m_rom);
82 m_bank[7]->set_base(ram + 0x9000);
83 m_bank[8]->set_base(m_rom);
84 m_bank[9]->set_base(ram + 0xb000);
85 m_bank[10]->set_base(ram + 0xc000);
86
87 }
88 else
89 {
90 space.install_write_bank(0x0000, 0x0fff, "bank1");
91 space.install_write_bank(0x2000, 0x2fff, "bank3");
92
93 m_bank[1]->set_base(ram);
94 m_bank[2]->set_base(ram + 0x1000);
95 m_bank[3]->set_base(ram + 0x2000);
96 m_bank[4]->set_base(ram + 0x5000);
97 m_bank[5]->set_base(ram + 0x4000);
98 }
99 }
100
pmd853_update_memory()101 void pmd85_state::pmd853_update_memory()
102 {
103 uint8_t *ram = m_ram->pointer();
104
105 if (m_startup_mem_map)
106 {
107 m_bank[1]->set_base(m_rom);
108 m_bank[2]->set_base(m_rom);
109 m_bank[3]->set_base(m_rom);
110 m_bank[4]->set_base(m_rom);
111 m_bank[5]->set_base(m_rom);
112 m_bank[6]->set_base(m_rom);
113 m_bank[7]->set_base(m_rom);
114 m_bank[8]->set_base(m_rom);
115 m_bank[9]->set_base(ram);
116 m_bank[10]->set_base(ram + 0x2000);
117 m_bank[11]->set_base(ram + 0x4000);
118 m_bank[12]->set_base(ram + 0x6000);
119 m_bank[13]->set_base(ram + 0x8000);
120 m_bank[14]->set_base(ram + 0xa000);
121 m_bank[15]->set_base(ram + 0xc000);
122 m_bank[16]->set_base(ram + 0xe000);
123 }
124 else
125 {
126 m_bank[1]->set_base(ram);
127 m_bank[2]->set_base(ram + 0x2000);
128 m_bank[3]->set_base(ram + 0x4000);
129 m_bank[4]->set_base(ram + 0x6000);
130 m_bank[5]->set_base(ram + 0x8000);
131 m_bank[6]->set_base(ram + 0xa000);
132 m_bank[7]->set_base(ram + 0xc000);
133 m_bank[8]->set_base(m_pmd853_memory_mapping ? m_rom : ram + 0xe000);
134 }
135 }
136
alfa_update_memory()137 void pmd85_state::alfa_update_memory()
138 {
139 address_space& space = m_maincpu->space(AS_PROGRAM);
140 uint8_t *ram = m_ram->pointer();
141
142 if (m_startup_mem_map)
143 {
144 space.unmap_write(0x0000, 0x0fff);
145 space.unmap_write(0x1000, 0x33ff);
146 space.nop_write(0x3400, 0x3fff);
147
148 m_bank[1]->set_base(m_rom);
149 m_bank[2]->set_base(m_rom + 0x1000);
150 m_bank[4]->set_base(ram + 0xc000);
151 m_bank[5]->set_base(m_rom);
152 m_bank[6]->set_base(m_rom + 0x1000);
153 m_bank[7]->set_base(ram + 0xc000);
154 }
155 else
156 {
157 space.install_write_bank(0x0000, 0x0fff, "bank1");
158 space.install_write_bank(0x1000, 0x33ff, "bank2");
159 space.install_write_bank(0x3400, 0x3fff, "bank3");
160
161 m_bank[1]->set_base(ram);
162 m_bank[2]->set_base(ram + 0x1000);
163 m_bank[3]->set_base(ram + 0x3400);
164 m_bank[4]->set_base(ram + 0x4000);
165 }
166 }
167
mato_update_memory()168 void pmd85_state::mato_update_memory()
169 {
170 address_space& space = m_maincpu->space(AS_PROGRAM);
171 uint8_t *ram = m_ram->pointer();
172
173 if (m_startup_mem_map)
174 {
175 space.unmap_write(0x0000, 0x3fff);
176
177 m_bank[1]->set_base(m_rom);
178 m_bank[2]->set_base(ram + 0xc000);
179 m_bank[3]->set_base(m_rom);
180 m_bank[4]->set_base(ram + 0xc000);
181 }
182 else
183 {
184 space.install_write_bank(0x0000, 0x3fff, "bank1");
185
186 m_bank[1]->set_base(ram);
187 m_bank[2]->set_base(ram + 0x4000);
188 }
189 }
190
c2717_update_memory()191 void pmd85_state::c2717_update_memory()
192 {
193 address_space& space = m_maincpu->space(AS_PROGRAM);
194 uint8_t *ram = m_ram->pointer();
195
196 if (m_startup_mem_map)
197 {
198 space.unmap_write(0x0000, 0x3fff);
199
200 m_bank[1]->set_base(m_rom);
201 m_bank[2]->set_base(ram + 0x4000);
202 m_bank[3]->set_base(m_rom);
203 m_bank[4]->set_base(ram + 0xc000);
204 }
205 else
206 {
207 space.install_write_bank(0x0000, 0x3fff, "bank1");
208 m_bank[1]->set_base(ram);
209 m_bank[2]->set_base(ram + 0x4000);
210 }
211 }
212
213 /*******************************************************************************
214
215 Motherboard 8255 (PMD-85.1, PMD-85.2, PMD-85.3, Didaktik Alfa)
216 --------------------------------------------------------------
217 keyboard, speaker, LEDs
218
219 *******************************************************************************/
220
ppi0_porta_r()221 uint8_t pmd85_state::ppi0_porta_r()
222 {
223 return 0xff;
224 }
225
ppi0_portb_r()226 uint8_t pmd85_state::ppi0_portb_r()
227 {
228 return m_io_keyboard[(m_ppi_port_outputs[0][0] & 0x0f)]->read() & m_io_keyboard[15]->read();
229 }
230
ppi0_portc_r()231 uint8_t pmd85_state::ppi0_portc_r()
232 {
233 return 0xff;
234 }
235
ppi0_porta_w(uint8_t data)236 void pmd85_state::ppi0_porta_w(uint8_t data)
237 {
238 m_ppi_port_outputs[0][0] = data;
239 }
240
ppi0_portb_w(uint8_t data)241 void pmd85_state::ppi0_portb_w(uint8_t data)
242 {
243 m_ppi_port_outputs[0][1] = data;
244 }
245
ppi0_portc_w(uint8_t data)246 void pmd85_state::ppi0_portc_w(uint8_t data)
247 {
248 m_ppi_port_outputs[0][2] = data;
249 m_leds[PMD85_LED_2] = BIT(data, 3);
250 //m_leds[PMD85_LED_3] = BIT(data, 2);
251 m_speaker->level_w(BIT(data, 2));
252 }
253
254 /*******************************************************************************
255
256 Motherboard 8255 (Mato)
257 -----------------------
258 keyboard, speaker, LEDs, tape
259
260 *******************************************************************************/
261
mato_ppi0_portb_r()262 uint8_t pmd85_state::mato_ppi0_portb_r()
263 {
264 u8 i,data = 0xff;
265
266 for (i = 0; i < 8; i++)
267 if (!BIT(m_ppi_port_outputs[0][0], i))
268 data &= m_io_keyboard[i]->read();
269
270 return data;
271 }
272
mato_ppi0_portc_r()273 uint8_t pmd85_state::mato_ppi0_portc_r()
274 {
275 u8 data = m_io_keyboard[8]->read() & 0x7f;
276 data |= (m_cassette->input() > 0.038) ? 0x80 : 0;
277 return data;
278 }
279
mato_ppi0_portc_w(uint8_t data)280 void pmd85_state::mato_ppi0_portc_w(uint8_t data)
281 {
282 m_ppi_port_outputs[0][2] = data;
283 m_leds[PMD85_LED_2] = BIT(data, 3);
284 m_leds[PMD85_LED_3] = BIT(data, 2);
285 m_speaker->level_w(BIT(data, 1));
286 m_cassette->output(BIT(data, 0) ? 1 : -1);
287 }
288
289 /*******************************************************************************
290
291 I/O board 8255
292 --------------
293 GPIO/0 (K3 connector), GPIO/1 (K4 connector)
294
295 *******************************************************************************/
296
ppi1_porta_r()297 uint8_t pmd85_state::ppi1_porta_r()
298 {
299 return 0xff;
300 }
301
ppi1_portb_r()302 uint8_t pmd85_state::ppi1_portb_r()
303 {
304 return 0xff;
305 }
306
ppi1_portc_r()307 uint8_t pmd85_state::ppi1_portc_r()
308 {
309 return 0xff;
310 }
311
ppi1_porta_w(uint8_t data)312 void pmd85_state::ppi1_porta_w(uint8_t data)
313 {
314 m_ppi_port_outputs[1][0] = data;
315 }
316
ppi1_portb_w(uint8_t data)317 void pmd85_state::ppi1_portb_w(uint8_t data)
318 {
319 m_ppi_port_outputs[1][1] = data;
320 }
321
ppi1_portc_w(uint8_t data)322 void pmd85_state::ppi1_portc_w(uint8_t data)
323 {
324 m_ppi_port_outputs[1][2] = data;
325 }
326
327 /*******************************************************************************
328
329 I/O board 8255
330 --------------
331 IMS-2 (K5 connector)
332
333 - 8251 - cassette recorder and V.24/IFSS (selectable by switch)
334
335 - external interfaces connector (K2)
336
337 *******************************************************************************/
338
ppi2_porta_r()339 uint8_t pmd85_state::ppi2_porta_r()
340 {
341 return 0xff;
342 }
343
ppi2_portb_r()344 uint8_t pmd85_state::ppi2_portb_r()
345 {
346 return 0xff;
347 }
348
ppi2_portc_r()349 uint8_t pmd85_state::ppi2_portc_r()
350 {
351 return 0xff;
352 }
353
ppi2_porta_w(uint8_t data)354 void pmd85_state::ppi2_porta_w(uint8_t data)
355 {
356 m_ppi_port_outputs[2][0] = data;
357 }
358
ppi2_portb_w(uint8_t data)359 void pmd85_state::ppi2_portb_w(uint8_t data)
360 {
361 m_ppi_port_outputs[2][1] = data;
362 }
363
ppi2_portc_w(uint8_t data)364 void pmd85_state::ppi2_portc_w(uint8_t data)
365 {
366 m_ppi_port_outputs[2][2] = data;
367 }
368
369 /*******************************************************************************
370
371 I/O board 8251
372 --------------
373 cassette recorder and V.24/IFSS (selectable by switch)
374
375 *******************************************************************************/
376
377 /*******************************************************************************
378
379 I/O board external interfaces connector (K2)
380 --------------------------------------------
381
382 *******************************************************************************/
383
384
385
386 /*******************************************************************************
387
388 ROM Module 8255
389 ---------------
390 port A - data read
391 ports B, C - address select
392
393 *******************************************************************************/
394
ppi3_porta_r()395 uint8_t pmd85_state::ppi3_porta_r()
396 {
397 if (memregion("user1")->base())
398 return memregion("user1")->base()[m_ppi_port_outputs[3][1] | (m_ppi_port_outputs[3][2] << 8)];
399 else
400 return 0;
401 }
402
ppi3_portb_r()403 uint8_t pmd85_state::ppi3_portb_r()
404 {
405 return 0xff;
406 }
407
ppi3_portc_r()408 uint8_t pmd85_state::ppi3_portc_r()
409 {
410 return 0xff;
411 }
412
ppi3_porta_w(uint8_t data)413 void pmd85_state::ppi3_porta_w(uint8_t data)
414 {
415 m_ppi_port_outputs[3][0] = data;
416 }
417
ppi3_portb_w(uint8_t data)418 void pmd85_state::ppi3_portb_w(uint8_t data)
419 {
420 m_ppi_port_outputs[3][1] = data;
421 }
422
ppi3_portc_w(uint8_t data)423 void pmd85_state::ppi3_portc_w(uint8_t data)
424 {
425 m_ppi_port_outputs[3][2] = data;
426 }
427
428 /*******************************************************************************
429
430 I/O ports (PMD-85.1, PMD-85.2, PMD-85.3, Didaktik Alfa)
431 -------------------------------------------------------
432
433 I/O board
434 1xxx11aa external interfaces connector (K2)
435
436 0xxx11aa I/O board interfaces
437 000111aa 8251 (casette recorder, V24)
438 010011aa 8255 (GPIO/0, GPIO/1)
439 010111aa 8253
440 011111aa 8255 (IMS-2)
441
442 Motherboard
443 1xxx01aa 8255 (keyboard, speaker, LEDs)
444 PMD-85.3 memory banking
445
446 ROM Module
447 1xxx10aa 8255 (ROM reading)
448
449 *******************************************************************************/
450
io_r(offs_t offset)451 uint8_t pmd85_state::io_r(offs_t offset)
452 {
453 if (m_startup_mem_map)
454 {
455 return 0xff;
456 }
457
458 switch (offset & 0x0c)
459 {
460 case 0x04: /* Motherboard */
461 switch (offset & 0x80)
462 {
463 case 0x80: /* Motherboard 8255 */
464 return m_ppi0->read(offset & 0x03);
465 }
466 break;
467 case 0x08: /* ROM module connector */
468 if (m_rom_module_present)
469 {
470 switch (offset & 0x80)
471 {
472 case 0x80: /* ROM module 8255 */
473 return m_ppi3->read(offset & 0x03);
474 }
475 }
476 break;
477 case 0x0c: /* I/O board */
478 switch (offset & 0x80)
479 {
480 case 0x00: /* I/O board interfaces */
481 switch (offset & 0x70)
482 {
483 case 0x10: /* 8251 (cassette recorder, V24) */
484 return m_uart->read(offset & 0x01);
485 case 0x40: /* 8255 (GPIO/0, GPIO/1) */
486 return m_ppi1->read(offset & 0x03);
487 case 0x50: /* 8253 */
488 return m_pit->read(offset & 0x03);
489 case 0x70: /* 8255 (IMS-2) */
490 return m_ppi2->read(offset & 0x03);
491 }
492 break;
493 case 0x80: /* external interfaces */
494 break;
495 }
496 break;
497 }
498 if ((m_model == ALFA) && ((offset & 0xfe) == 0xf0))
499 return m_uart->read(offset & 0x01);
500
501 logerror ("Reading from unmapped port: %02x\n", offset);
502 return 0xff;
503 }
504
io_w(offs_t offset,uint8_t data)505 void pmd85_state::io_w(offs_t offset, uint8_t data)
506 {
507 if (m_startup_mem_map)
508 {
509 m_startup_mem_map = 0;
510 (this->*update_memory)();
511 }
512
513 switch (offset & 0x0c)
514 {
515 case 0x04: /* Motherboard */
516 switch (offset & 0x80)
517 {
518 case 0x80: /* Motherboard 8255 */
519 m_ppi0->write(offset & 0x03, data);
520 /* PMD-85.3 memory banking */
521 if ((offset & 0x03) == 0x03)
522 {
523 m_pmd853_memory_mapping = data & 0x01;
524 (this->*update_memory)();
525 }
526 break;
527 }
528 break;
529 case 0x08: /* ROM module connector */
530 if (m_rom_module_present)
531 {
532 switch (offset & 0x80)
533 {
534 case 0x80: /* ROM module 8255 */
535 m_ppi3->write(offset & 0x03, data);
536 break;
537 }
538 }
539 break;
540 case 0x0c: /* I/O board */
541 switch (offset & 0x80)
542 {
543 case 0x00: /* I/O board interfaces */
544 switch (offset & 0x70)
545 {
546 case 0x10: /* 8251 (cassette recorder, V24) */
547 m_uart->write(offset & 0x01, data);
548 break;
549 case 0x40: /* 8255 (GPIO/0, GPIO/0) */
550 m_ppi1->write(offset & 0x03, data);
551 break;
552 case 0x50: /* 8253 */
553 m_pit->write(offset & 0x03, data);
554 logerror ("8253 writing. Address: %02x, Data: %02x\n", offset, data);
555 break;
556 case 0x70: /* 8255 (IMS-2) */
557 m_ppi2->write(offset & 0x03, data);
558 break;
559 }
560 break;
561 case 0x80: /* external interfaces */
562 break;
563 }
564 break;
565 }
566 if ((m_model == ALFA) && ((offset & 0xfe) == 0xf0))
567 m_uart->write(offset & 0x01, data);
568 //logerror ("Writing to unmapped port: %02x:%02X\n", offset,data);
569 }
570
571 /*******************************************************************************
572
573 I/O ports (Mato)
574 ----------------
575
576 Motherboard
577 1xxx01aa 8255 (keyboard, speaker, LEDs, tape)
578
579 *******************************************************************************/
580
mato_io_r(offs_t offset)581 uint8_t pmd85_state::mato_io_r(offs_t offset)
582 {
583 if (m_startup_mem_map)
584 {
585 return 0xff;
586 }
587
588 switch (offset & 0x0c)
589 {
590 case 0x04: /* Motherboard */
591 switch (offset & 0x80)
592 {
593 case 0x80: /* Motherboard 8255 */
594 return m_ppi0->read(offset & 0x03);
595 }
596 break;
597 }
598
599 logerror ("Reading from unmapped port: %02x\n", offset);
600 return 0xff;
601 }
602
mato_io_w(offs_t offset,uint8_t data)603 void pmd85_state::mato_io_w(offs_t offset, uint8_t data)
604 {
605 if (m_startup_mem_map)
606 {
607 m_startup_mem_map = 0;
608 (this->*update_memory)();
609 }
610
611 switch (offset & 0x0c)
612 {
613 case 0x04: /* Motherboard */
614 switch (offset & 0x80)
615 {
616 case 0x80: /* Motherboard 8255 */
617 return m_ppi0->write(offset & 0x03, data);
618 }
619 break;
620 }
621 }
622
device_timer(emu_timer & timer,device_timer_id id,int param,void * ptr)623 void pmd85_state::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
624 {
625 switch (id)
626 {
627 case TIMER_CASSETTE:
628 cassette_timer_callback(ptr, param);
629 break;
630 default:
631 throw emu_fatalerror("Unknown id in pmd85_state::device_timer");
632 }
633 }
634
TIMER_CALLBACK_MEMBER(pmd85_state::cassette_timer_callback)635 TIMER_CALLBACK_MEMBER(pmd85_state::cassette_timer_callback)
636 {
637 bool data;
638 bool current_level;
639
640 if (!BIT(m_io_dsw0->read(), 1)) /* V.24 / Tape Switch */
641 {
642 /* tape reading */
643 if (m_cassette->get_state()&CASSETTE_PLAY)
644 {
645 switch (m_model)
646 {
647 case PMD85_1:
648 case ALFA:
649 if (m_clk_level_tape)
650 {
651 m_previous_level = (m_cassette->input() > 0.038) ? 1 : 0;
652 m_clk_level_tape = 0;
653 }
654 else
655 {
656 current_level = (m_cassette->input() > 0.038) ? 1 : 0;
657
658 if (m_previous_level!=current_level)
659 {
660 data = (!m_previous_level && current_level) ? 1 : 0;
661
662 m_uart->write_rxd(data);
663
664 m_clk_level_tape = 1;
665 }
666 }
667
668 m_uart->write_rxc(m_clk_level_tape);
669 return;
670 case PMD85_2:
671 case PMD85_2A:
672 case C2717:
673 case PMD85_3:
674 // works for pmd852, pmd852a, pmd852b, pmd853, c2717, c2717pmd
675 m_uart->write_dsr( (m_cassette->input() > 0.038) ? 0 : 1);
676 return;
677 }
678 }
679
680 /* tape writing */
681 if (m_cassette->get_state()&CASSETTE_RECORD)
682 {
683 m_cassette->output((m_txd ^ m_clk_level_tape) ? 1 : -1);
684
685 m_clk_level_tape = m_clk_level_tape ? 0 : 1;
686 m_uart->write_txc(m_clk_level_tape);
687
688 return;
689 }
690
691 m_clk_level_tape = 1;
692
693 m_clk_level = m_clk_level ? 0 : 1;
694 m_uart->write_txc(m_clk_level);
695 }
696 }
697
INPUT_CHANGED_MEMBER(pmd85_state::pmd85_reset)698 INPUT_CHANGED_MEMBER(pmd85_state::pmd85_reset)
699 {
700 machine().schedule_soft_reset();
701 }
702
common_driver_init()703 void pmd85_state::common_driver_init()
704 {
705 m_previous_level = 0;
706 m_clk_level = m_clk_level_tape = 1;
707 m_cassette_timer = timer_alloc(TIMER_CASSETTE);
708 m_cassette_timer->adjust(attotime::zero, 0, attotime::from_hz(2400));
709 }
710
init_pmd851()711 void pmd85_state::init_pmd851()
712 {
713 m_model = PMD85_1;
714 update_memory = &pmd85_state::pmd851_update_memory;
715 common_driver_init();
716 }
717
init_pmd852()718 void pmd85_state::init_pmd852()
719 {
720 m_model = PMD85_2;
721 update_memory = &pmd85_state::pmd851_update_memory;
722 common_driver_init();
723 }
724
init_pmd852a()725 void pmd85_state::init_pmd852a()
726 {
727 m_model = PMD85_2A;
728 update_memory = &pmd85_state::pmd852a_update_memory;
729 common_driver_init();
730 }
731
init_pmd853()732 void pmd85_state::init_pmd853()
733 {
734 m_model = PMD85_3;
735 update_memory = &pmd85_state::pmd853_update_memory;
736 common_driver_init();
737 }
738
init_alfa()739 void pmd85_state::init_alfa()
740 {
741 m_model = ALFA;
742 update_memory = &pmd85_state::alfa_update_memory;
743 common_driver_init();
744 }
745
init_mato()746 void pmd85_state::init_mato()
747 {
748 m_model = MATO;
749 update_memory = &pmd85_state::mato_update_memory;
750 }
751
init_c2717()752 void pmd85_state::init_c2717()
753 {
754 m_model = C2717;
755 update_memory = &pmd85_state::c2717_update_memory;
756 common_driver_init();
757 }
758
machine_reset()759 void pmd85_state::machine_reset()
760 {
761 /* checking for Rom Module */
762 m_rom_module_present = 0;
763 switch (m_model)
764 {
765 case PMD85_1:
766 case PMD85_2:
767 case PMD85_2A:
768 case PMD85_3:
769 case C2717:
770 m_rom_module_present = BIT(m_io_dsw0->read(), 0);
771 break;
772 case ALFA:
773 case MATO:
774 break;
775 }
776
777 for (u8 i = 0; i < 4; i++)
778 for (u8 j = 0; j < 3; j++)
779 m_ppi_port_outputs[i][j] = 0;
780
781 /* memory initialization */
782 m_pmd853_memory_mapping = 1;
783 m_startup_mem_map = 1;
784 (this->*update_memory)();
785 }
786
machine_start()787 void pmd85_state::machine_start()
788 {
789 m_leds.resolve();
790 save_item(NAME(m_txd));
791 save_item(NAME(m_rts));
792 save_item(NAME(m_rom_module_present));
793 save_item(NAME(m_ppi_port_outputs));
794 save_item(NAME(m_startup_mem_map));
795 save_item(NAME(m_pmd853_memory_mapping));
796 save_item(NAME(m_previous_level));
797 save_item(NAME(m_clk_level));
798 save_item(NAME(m_clk_level_tape));
799 save_item(NAME(m_model));
800 }
801
802