1 #define OP_SHIFT_b(c, ea32) \
2 { \
3 uint8_t temp_orig = temp; \
4 if (!c) return 0; \
5 flags_rebuild(); \
6 switch (rmdat & 0x38) \
7 { \
8 case 0x00: /*ROL b, c*/ \
9 while (c > 0) \
10 { \
11 temp2 = (temp & 0x80) ? 1 : 0; \
12 temp = (temp << 1) | temp2; \
13 c--; \
14 } \
15 seteab(temp); if (cpu_state.abrt) return 1; \
16 flags &= ~(C_FLAG | V_FLAG); \
17 if (temp2) flags |= C_FLAG; \
18 if ((flags & C_FLAG) ^ (temp >> 7)) flags |= V_FLAG; \
19 CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
20 PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
21 break; \
22 case 0x08: /*ROR b,CL*/ \
23 while (c > 0) \
24 { \
25 temp2 = temp & 1; \
26 temp >>= 1; \
27 if (temp2) temp |= 0x80; \
28 c--; \
29 } \
30 seteab(temp); if (cpu_state.abrt) return 1; \
31 flags &= ~(C_FLAG | V_FLAG); \
32 if (temp2) flags |= C_FLAG; \
33 if ((temp ^ (temp >> 1)) & 0x40) flags |= V_FLAG; \
34 CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
35 PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
36 break; \
37 case 0x10: /*RCL b,CL*/ \
38 temp2 = flags & C_FLAG; \
39 if (is486) CLOCK_CYCLES_ALWAYS(c); \
40 while (c > 0) \
41 { \
42 tempc = temp2 ? 1 : 0; \
43 temp2 = temp & 0x80; \
44 temp = (temp << 1) | tempc; \
45 c--; \
46 } \
47 seteab(temp); if (cpu_state.abrt) return 1; \
48 flags &= ~(C_FLAG | V_FLAG); \
49 if (temp2) flags |= C_FLAG; \
50 if ((flags & C_FLAG) ^ (temp >> 7)) flags |= V_FLAG; \
51 CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
52 PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
53 break; \
54 case 0x18: /*RCR b,CL*/ \
55 temp2 = flags & C_FLAG; \
56 if (is486) CLOCK_CYCLES_ALWAYS(c); \
57 while (c > 0) \
58 { \
59 tempc = temp2 ? 0x80 : 0; \
60 temp2 = temp & 1; \
61 temp = (temp >> 1) | tempc; \
62 c--; \
63 } \
64 seteab(temp); if (cpu_state.abrt) return 1; \
65 flags &= ~(C_FLAG | V_FLAG); \
66 if (temp2) flags |= C_FLAG; \
67 if ((temp ^ (temp >> 1)) & 0x40) flags |= V_FLAG; \
68 CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
69 PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
70 break; \
71 case 0x20: case 0x30: /*SHL b,CL*/ \
72 seteab(temp << c); if (cpu_state.abrt) return 1; \
73 set_flags_shift(FLAGS_SHL8, temp_orig, c, (temp << c) & 0xff); \
74 CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
75 PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
76 break; \
77 case 0x28: /*SHR b,CL*/ \
78 seteab(temp >> c); if (cpu_state.abrt) return 1; \
79 set_flags_shift(FLAGS_SHR8, temp_orig, c, temp >> c); \
80 CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
81 PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
82 break; \
83 case 0x38: /*SAR b,CL*/ \
84 temp = (int8_t)temp >> c; \
85 seteab(temp); if (cpu_state.abrt) return 1; \
86 set_flags_shift(FLAGS_SAR8, temp_orig, c, temp); \
87 CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
88 PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
89 break; \
90 } \
91 }
92
93 #define OP_SHIFT_w(c, ea32) \
94 { \
95 uint16_t temp_orig = temp; \
96 if (!c) return 0; \
97 flags_rebuild(); \
98 switch (rmdat & 0x38) \
99 { \
100 case 0x00: /*ROL w, c*/ \
101 while (c > 0) \
102 { \
103 temp2 = (temp & 0x8000) ? 1 : 0; \
104 temp = (temp << 1) | temp2; \
105 c--; \
106 } \
107 seteaw(temp); if (cpu_state.abrt) return 1; \
108 flags &= ~(C_FLAG | V_FLAG); \
109 if (temp2) flags |= C_FLAG; \
110 if ((flags & C_FLAG) ^ (temp >> 15)) flags |= V_FLAG; \
111 CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
112 PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
113 break; \
114 case 0x08: /*ROR w, c*/ \
115 while (c > 0) \
116 { \
117 temp2 = temp & 1; \
118 temp >>= 1; \
119 if (temp2) temp |= 0x8000; \
120 c--; \
121 } \
122 seteaw(temp); if (cpu_state.abrt) return 1; \
123 flags &= ~(C_FLAG | V_FLAG); \
124 if (temp2) flags |= C_FLAG; \
125 if ((temp ^ (temp >> 1)) & 0x4000) flags |= V_FLAG; \
126 CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
127 PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
128 break; \
129 case 0x10: /*RCL w, c*/ \
130 temp2 = flags & C_FLAG; \
131 if (is486) CLOCK_CYCLES_ALWAYS(c); \
132 while (c > 0) \
133 { \
134 tempc = temp2 ? 1 : 0; \
135 temp2 = temp & 0x8000; \
136 temp = (temp << 1) | tempc; \
137 c--; \
138 } \
139 seteaw(temp); if (cpu_state.abrt) return 1; \
140 flags &= ~(C_FLAG | V_FLAG); \
141 if (temp2) flags |= C_FLAG; \
142 if ((flags & C_FLAG) ^ (temp >> 15)) flags |= V_FLAG; \
143 CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
144 PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
145 break; \
146 case 0x18: /*RCR w, c*/ \
147 temp2 = flags & C_FLAG; \
148 if (is486) CLOCK_CYCLES_ALWAYS(c); \
149 while (c > 0) \
150 { \
151 tempc = temp2 ? 0x8000 : 0; \
152 temp2 = temp & 1; \
153 temp = (temp >> 1) | tempc; \
154 c--; \
155 } \
156 seteaw(temp); if (cpu_state.abrt) return 1; \
157 flags &= ~(C_FLAG | V_FLAG); \
158 if (temp2) flags |= C_FLAG; \
159 if ((temp ^ (temp >> 1)) & 0x4000) flags |= V_FLAG; \
160 CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
161 PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
162 break; \
163 case 0x20: case 0x30: /*SHL w, c*/ \
164 seteaw(temp << c); if (cpu_state.abrt) return 1; \
165 set_flags_shift(FLAGS_SHL16, temp_orig, c, (temp << c) & 0xffff); \
166 CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
167 PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
168 break; \
169 case 0x28: /*SHR w, c*/ \
170 seteaw(temp >> c); if (cpu_state.abrt) return 1; \
171 set_flags_shift(FLAGS_SHR16, temp_orig, c, temp >> c); \
172 CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
173 PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
174 break; \
175 case 0x38: /*SAR w, c*/ \
176 temp = (int16_t)temp >> c; \
177 seteaw(temp); if (cpu_state.abrt) return 1; \
178 set_flags_shift(FLAGS_SAR16, temp_orig, c, temp); \
179 CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
180 PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
181 break; \
182 } \
183 }
184
185 #define OP_SHIFT_l(c, ea32) \
186 { \
187 uint32_t temp_orig = temp; \
188 if (!c) return 0; \
189 flags_rebuild(); \
190 switch (rmdat & 0x38) \
191 { \
192 case 0x00: /*ROL l, c*/ \
193 while (c > 0) \
194 { \
195 temp2 = (temp & 0x80000000) ? 1 : 0; \
196 temp = (temp << 1) | temp2; \
197 c--; \
198 } \
199 seteal(temp); if (cpu_state.abrt) return 1; \
200 flags &= ~(C_FLAG | V_FLAG); \
201 if (temp2) flags |= C_FLAG; \
202 if ((flags & C_FLAG) ^ (temp >> 31)) flags |= V_FLAG; \
203 CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
204 PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
205 break; \
206 case 0x08: /*ROR l, c*/ \
207 while (c > 0) \
208 { \
209 temp2 = temp & 1; \
210 temp >>= 1; \
211 if (temp2) temp |= 0x80000000; \
212 c--; \
213 } \
214 seteal(temp); if (cpu_state.abrt) return 1; \
215 flags &= ~(C_FLAG | V_FLAG); \
216 if (temp2) flags |= C_FLAG; \
217 if ((temp ^ (temp >> 1)) & 0x40000000) flags |= V_FLAG; \
218 CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
219 PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
220 break; \
221 case 0x10: /*RCL l, c*/ \
222 temp2 = CF_SET(); \
223 if (is486) CLOCK_CYCLES_ALWAYS(c); \
224 while (c > 0) \
225 { \
226 tempc = temp2 ? 1 : 0; \
227 temp2 = temp & 0x80000000; \
228 temp = (temp << 1) | tempc; \
229 c--; \
230 } \
231 seteal(temp); if (cpu_state.abrt) return 1; \
232 flags &= ~(C_FLAG | V_FLAG); \
233 if (temp2) flags |= C_FLAG; \
234 if ((flags & C_FLAG) ^ (temp >> 31)) flags |= V_FLAG; \
235 CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
236 PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
237 break; \
238 case 0x18: /*RCR l, c*/ \
239 temp2 = flags & C_FLAG; \
240 if (is486) CLOCK_CYCLES_ALWAYS(c); \
241 while (c > 0) \
242 { \
243 tempc = temp2 ? 0x80000000 : 0; \
244 temp2 = temp & 1; \
245 temp = (temp >> 1) | tempc; \
246 c--; \
247 } \
248 seteal(temp); if (cpu_state.abrt) return 1; \
249 flags &= ~(C_FLAG | V_FLAG); \
250 if (temp2) flags |= C_FLAG; \
251 if ((temp ^ (temp >> 1)) & 0x40000000) flags |= V_FLAG; \
252 CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
253 PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
254 break; \
255 case 0x20: case 0x30: /*SHL l, c*/ \
256 seteal(temp << c); if (cpu_state.abrt) return 1; \
257 set_flags_shift(FLAGS_SHL32, temp_orig, c, temp << c); \
258 CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
259 PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
260 break; \
261 case 0x28: /*SHR l, c*/ \
262 seteal(temp >> c); if (cpu_state.abrt) return 1; \
263 set_flags_shift(FLAGS_SHR32, temp_orig, c, temp >> c); \
264 CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
265 PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
266 break; \
267 case 0x38: /*SAR l, c*/ \
268 temp = (int32_t)temp >> c; \
269 seteal(temp); if (cpu_state.abrt) return 1; \
270 set_flags_shift(FLAGS_SAR32, temp_orig, c, temp); \
271 CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
272 PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
273 break; \
274 } \
275 }
276
opC0_a16(uint32_t fetchdat)277 static int opC0_a16(uint32_t fetchdat)
278 {
279 int c;
280 int tempc;
281 uint8_t temp, temp2;
282
283 fetch_ea_16(fetchdat);
284 c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
285 PREFETCH_PREFIX();
286 temp = geteab(); if (cpu_state.abrt) return 1;
287 OP_SHIFT_b(c, 0);
288 return 0;
289 }
opC0_a32(uint32_t fetchdat)290 static int opC0_a32(uint32_t fetchdat)
291 {
292 int c;
293 int tempc;
294 uint8_t temp, temp2;
295
296 fetch_ea_32(fetchdat);
297 c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
298 PREFETCH_PREFIX();
299 temp = geteab(); if (cpu_state.abrt) return 1;
300 OP_SHIFT_b(c, 1);
301 return 0;
302 }
opC1_w_a16(uint32_t fetchdat)303 static int opC1_w_a16(uint32_t fetchdat)
304 {
305 int c;
306 int tempc;
307 uint16_t temp, temp2;
308
309 fetch_ea_16(fetchdat);
310 c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
311 PREFETCH_PREFIX();
312 temp = geteaw(); if (cpu_state.abrt) return 1;
313 OP_SHIFT_w(c, 0);
314 return 0;
315 }
opC1_w_a32(uint32_t fetchdat)316 static int opC1_w_a32(uint32_t fetchdat)
317 {
318 int c;
319 int tempc;
320 uint16_t temp, temp2;
321
322 fetch_ea_32(fetchdat);
323 c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
324 PREFETCH_PREFIX();
325 temp = geteaw(); if (cpu_state.abrt) return 1;
326 OP_SHIFT_w(c, 1);
327 return 0;
328 }
opC1_l_a16(uint32_t fetchdat)329 static int opC1_l_a16(uint32_t fetchdat)
330 {
331 int c;
332 int tempc;
333 uint32_t temp, temp2;
334
335 fetch_ea_16(fetchdat);
336 c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
337 PREFETCH_PREFIX();
338 temp = geteal(); if (cpu_state.abrt) return 1;
339 OP_SHIFT_l(c, 0);
340 return 0;
341 }
opC1_l_a32(uint32_t fetchdat)342 static int opC1_l_a32(uint32_t fetchdat)
343 {
344 int c;
345 int tempc;
346 uint32_t temp, temp2;
347
348 fetch_ea_32(fetchdat);
349 c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
350 PREFETCH_PREFIX();
351 temp = geteal(); if (cpu_state.abrt) return 1;
352 OP_SHIFT_l(c, 1);
353 return 0;
354 }
355
opD0_a16(uint32_t fetchdat)356 static int opD0_a16(uint32_t fetchdat)
357 {
358 int c = 1;
359 int tempc;
360 uint8_t temp, temp2;
361
362 fetch_ea_16(fetchdat);
363 temp = geteab(); if (cpu_state.abrt) return 1;
364 OP_SHIFT_b(c, 0);
365 return 0;
366 }
opD0_a32(uint32_t fetchdat)367 static int opD0_a32(uint32_t fetchdat)
368 {
369 int c = 1;
370 int tempc;
371 uint8_t temp, temp2;
372
373 fetch_ea_32(fetchdat);
374 temp = geteab(); if (cpu_state.abrt) return 1;
375 OP_SHIFT_b(c, 1);
376 return 0;
377 }
opD1_w_a16(uint32_t fetchdat)378 static int opD1_w_a16(uint32_t fetchdat)
379 {
380 int c = 1;
381 int tempc;
382 uint16_t temp, temp2;
383
384 fetch_ea_16(fetchdat);
385 temp = geteaw(); if (cpu_state.abrt) return 1;
386 OP_SHIFT_w(c, 0);
387 return 0;
388 }
opD1_w_a32(uint32_t fetchdat)389 static int opD1_w_a32(uint32_t fetchdat)
390 {
391 int c = 1;
392 int tempc;
393 uint16_t temp, temp2;
394
395 fetch_ea_32(fetchdat);
396 temp = geteaw(); if (cpu_state.abrt) return 1;
397 OP_SHIFT_w(c, 1);
398 return 0;
399 }
opD1_l_a16(uint32_t fetchdat)400 static int opD1_l_a16(uint32_t fetchdat)
401 {
402 int c = 1;
403 int tempc;
404 uint32_t temp, temp2;
405
406 fetch_ea_16(fetchdat);
407 temp = geteal(); if (cpu_state.abrt) return 1;
408 OP_SHIFT_l(c, 0);
409 return 0;
410 }
opD1_l_a32(uint32_t fetchdat)411 static int opD1_l_a32(uint32_t fetchdat)
412 {
413 int c = 1;
414 int tempc;
415 uint32_t temp, temp2;
416
417 fetch_ea_32(fetchdat);
418 temp = geteal(); if (cpu_state.abrt) return 1;
419 OP_SHIFT_l(c, 1);
420 return 0;
421 }
422
opD2_a16(uint32_t fetchdat)423 static int opD2_a16(uint32_t fetchdat)
424 {
425 int c;
426 int tempc;
427 uint8_t temp, temp2;
428
429 fetch_ea_16(fetchdat);
430 c = CL & 31;
431 temp = geteab(); if (cpu_state.abrt) return 1;
432 OP_SHIFT_b(c, 0);
433 return 0;
434 }
opD2_a32(uint32_t fetchdat)435 static int opD2_a32(uint32_t fetchdat)
436 {
437 int c;
438 int tempc;
439 uint8_t temp, temp2;
440
441 fetch_ea_32(fetchdat);
442 c = CL & 31;
443 temp = geteab(); if (cpu_state.abrt) return 1;
444 OP_SHIFT_b(c, 1);
445 return 0;
446 }
opD3_w_a16(uint32_t fetchdat)447 static int opD3_w_a16(uint32_t fetchdat)
448 {
449 int c;
450 int tempc;
451 uint16_t temp, temp2;
452
453 fetch_ea_16(fetchdat);
454 c = CL & 31;
455 temp = geteaw(); if (cpu_state.abrt) return 1;
456 OP_SHIFT_w(c, 0);
457 return 0;
458 }
opD3_w_a32(uint32_t fetchdat)459 static int opD3_w_a32(uint32_t fetchdat)
460 {
461 int c;
462 int tempc;
463 uint16_t temp, temp2;
464
465 fetch_ea_32(fetchdat);
466 c = CL & 31;
467 temp = geteaw(); if (cpu_state.abrt) return 1;
468 OP_SHIFT_w(c, 1);
469 return 0;
470 }
opD3_l_a16(uint32_t fetchdat)471 static int opD3_l_a16(uint32_t fetchdat)
472 {
473 int c;
474 int tempc;
475 uint32_t temp, temp2;
476
477 fetch_ea_16(fetchdat);
478 c = CL & 31;
479 temp = geteal(); if (cpu_state.abrt) return 1;
480 OP_SHIFT_l(c, 0);
481 return 0;
482 }
opD3_l_a32(uint32_t fetchdat)483 static int opD3_l_a32(uint32_t fetchdat)
484 {
485 int c;
486 int tempc;
487 uint32_t temp, temp2;
488
489 fetch_ea_32(fetchdat);
490 c = CL & 31;
491 temp = geteal(); if (cpu_state.abrt) return 1;
492 OP_SHIFT_l(c, 1);
493 return 0;
494 }
495
496
497 #define SHLD_w() \
498 if (count) \
499 { \
500 uint16_t tempw = geteaw(); if (cpu_state.abrt) return 1; \
501 int tempc = ((tempw << (count - 1)) & (1 << 15)) ? 1 : 0; \
502 uint32_t templ = (tempw << 16) | cpu_state.regs[cpu_reg].w; \
503 if (count <= 16) tempw = templ >> (16 - count); \
504 else tempw = (templ << count) >> 16; \
505 seteaw(tempw); if (cpu_state.abrt) return 1; \
506 setznp16(tempw); \
507 flags_rebuild(); \
508 if (tempc) flags |= C_FLAG; \
509 }
510
511 #define SHLD_l() \
512 if (count) \
513 { \
514 uint32_t templ = geteal(); if (cpu_state.abrt) return 1; \
515 int tempc = ((templ << (count - 1)) & (1 << 31)) ? 1 : 0; \
516 templ = (templ << count) | (cpu_state.regs[cpu_reg].l >> (32 - count)); \
517 seteal(templ); if (cpu_state.abrt) return 1; \
518 setznp32(templ); \
519 flags_rebuild(); \
520 if (tempc) flags |= C_FLAG; \
521 }
522
523
524 #define SHRD_w() \
525 if (count) \
526 { \
527 uint16_t tempw = geteaw(); if (cpu_state.abrt) return 1; \
528 int tempc = (tempw >> (count - 1)) & 1; \
529 uint32_t templ = tempw | (cpu_state.regs[cpu_reg].w << 16); \
530 tempw = templ >> count; \
531 seteaw(tempw); if (cpu_state.abrt) return 1; \
532 setznp16(tempw); \
533 flags_rebuild(); \
534 if (tempc) flags |= C_FLAG; \
535 }
536
537 #define SHRD_l() \
538 if (count) \
539 { \
540 uint32_t templ = geteal(); if (cpu_state.abrt) return 1; \
541 int tempc = (templ >> (count - 1)) & 1; \
542 templ = (templ >> count) | (cpu_state.regs[cpu_reg].l << (32 - count)); \
543 seteal(templ); if (cpu_state.abrt) return 1; \
544 setznp32(templ); \
545 flags_rebuild(); \
546 if (tempc) flags |= C_FLAG; \
547 }
548
549 #define opSHxD(operation) \
550 static int op ## operation ## _i_a16(uint32_t fetchdat) \
551 { \
552 int count; \
553 \
554 fetch_ea_16(fetchdat); \
555 count = getbyte() & 31; \
556 operation(); \
557 \
558 CLOCK_CYCLES(3); \
559 PREFETCH_RUN(3, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 0); \
560 return 0; \
561 } \
562 static int op ## operation ## _CL_a16(uint32_t fetchdat) \
563 { \
564 int count; \
565 \
566 fetch_ea_16(fetchdat); \
567 count = CL & 31; \
568 operation(); \
569 \
570 CLOCK_CYCLES(3); \
571 PREFETCH_RUN(3, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 0); \
572 return 0; \
573 } \
574 static int op ## operation ## _i_a32(uint32_t fetchdat) \
575 { \
576 int count; \
577 \
578 fetch_ea_32(fetchdat); \
579 count = getbyte() & 31; \
580 operation(); \
581 \
582 CLOCK_CYCLES(3); \
583 PREFETCH_RUN(3, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 1); \
584 return 0; \
585 } \
586 static int op ## operation ## _CL_a32(uint32_t fetchdat) \
587 { \
588 int count; \
589 \
590 fetch_ea_32(fetchdat); \
591 count = CL & 31; \
592 operation(); \
593 \
594 CLOCK_CYCLES(3); \
595 PREFETCH_RUN(3, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 1); \
596 return 0; \
597 }
598
599 opSHxD(SHLD_w)
600 opSHxD(SHLD_l)
601 opSHxD(SHRD_w)
602 opSHxD(SHRD_l)
603