1 /*************************************************************************** 2 * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team * 3 * * 4 * This program is free software; you can redistribute it and/or modify * 5 * it under the terms of the GNU General Public License as published by * 6 * the Free Software Foundation; either version 2 of the License, or * 7 * (at your option) any later version. * 8 * * 9 * This program is distributed in the hope that it will be useful, * 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of * 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * 12 * GNU General Public License for more details. * 13 * * 14 * You should have received a copy of the GNU General Public License * 15 * along with this program; if not, write to the * 16 * Free Software Foundation, Inc., * 17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * 18 ***************************************************************************/ 19 20 #ifndef __PSXDMA_H__ 21 #define __PSXDMA_H__ 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 #include "psxcommon.h" 28 #include "r3000a.h" 29 #include "psxhw.h" 30 #include "psxmem.h" 31 32 #define GPUDMA_INT(eCycle) { \ 33 psxRegs.interrupt |= (1 << PSXINT_GPUDMA); \ 34 psxRegs.intCycle[PSXINT_GPUDMA].cycle = eCycle; \ 35 psxRegs.intCycle[PSXINT_GPUDMA].sCycle = psxRegs.cycle; \ 36 } 37 38 #define SPUDMA_INT(eCycle) { \ 39 psxRegs.interrupt |= (1 << PSXINT_SPUDMA); \ 40 psxRegs.intCycle[PSXINT_SPUDMA].cycle = eCycle; \ 41 psxRegs.intCycle[PSXINT_SPUDMA].sCycle = psxRegs.cycle; \ 42 } 43 44 #define MDECOUTDMA_INT(eCycle) { \ 45 psxRegs.interrupt |= (1 << PSXINT_MDECOUTDMA); \ 46 psxRegs.intCycle[PSXINT_MDECOUTDMA].cycle = eCycle; \ 47 psxRegs.intCycle[PSXINT_MDECOUTDMA].sCycle = psxRegs.cycle; \ 48 } 49 50 #define MDECINDMA_INT(eCycle) { \ 51 psxRegs.interrupt |= (1 << PSXINT_MDECINDMA); \ 52 psxRegs.intCycle[PSXINT_MDECINDMA].cycle = eCycle; \ 53 psxRegs.intCycle[PSXINT_MDECINDMA].sCycle = psxRegs.cycle; \ 54 } 55 56 #define GPUOTCDMA_INT(eCycle) { \ 57 psxRegs.interrupt |= (1 << PSXINT_GPUOTCDMA); \ 58 psxRegs.intCycle[PSXINT_GPUOTCDMA].cycle = eCycle; \ 59 psxRegs.intCycle[PSXINT_GPUOTCDMA].sCycle = psxRegs.cycle; \ 60 } 61 62 #define CDRDMA_INT(eCycle) { \ 63 psxRegs.interrupt |= (1 << PSXINT_CDRDMA); \ 64 psxRegs.intCycle[PSXINT_CDRDMA].cycle = eCycle; \ 65 psxRegs.intCycle[PSXINT_CDRDMA].sCycle = psxRegs.cycle; \ 66 } 67 68 /* 69 DMA5 = N/A (PIO) 70 */ 71 72 void psxDma3(u32 madr, u32 bcr, u32 chcr); 73 void psxDma4(u32 madr, u32 bcr, u32 chcr); 74 void psxDma6(u32 madr, u32 bcr, u32 chcr); 75 void spuInterrupt(); 76 void mdec0Interrupt(); 77 void gpuotcInterrupt(); 78 void cdrDmaInterrupt(); 79 80 #ifdef __cplusplus 81 } 82 #endif 83 #endif 84