1 /*
2 * QEMU RISC-V VirtIO Board
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 *
6 * RISC-V machine with 16550a UART and VirtIO MMIO
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu/units.h"
23 #include "qemu/log.h"
24 #include "qemu/error-report.h"
25 #include "qapi/error.h"
26 #include "hw/boards.h"
27 #include "hw/loader.h"
28 #include "hw/sysbus.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/char/serial.h"
31 #include "target/riscv/cpu.h"
32 #include "hw/riscv/riscv_hart.h"
33 #include "hw/riscv/sifive_plic.h"
34 #include "hw/riscv/sifive_clint.h"
35 #include "hw/riscv/sifive_test.h"
36 #include "hw/riscv/virt.h"
37 #include "hw/riscv/boot.h"
38 #include "chardev/char.h"
39 #include "sysemu/arch_init.h"
40 #include "sysemu/device_tree.h"
41 #include "sysemu/sysemu.h"
42 #include "exec/address-spaces.h"
43 #include "hw/pci/pci.h"
44 #include "hw/pci-host/gpex.h"
45
46 #include <libfdt.h>
47
48 #if defined(TARGET_RISCV32)
49 # define BIOS_FILENAME "opensbi-riscv32-virt-fw_jump.bin"
50 #else
51 # define BIOS_FILENAME "opensbi-riscv64-virt-fw_jump.bin"
52 #endif
53
54 #ifdef TARGET_CHERI
55 #include "cheri_tagmem.h"
56 #endif
57
58 static const struct MemmapEntry {
59 hwaddr base;
60 hwaddr size;
61 } virt_memmap[] = {
62 [VIRT_DEBUG] = { 0x0, 0x100 },
63 [VIRT_MROM] = { 0x1000, 0x11000 },
64 [VIRT_TEST] = { 0x100000, 0x1000 },
65 [VIRT_RTC] = { 0x101000, 0x1000 },
66 [VIRT_CLINT] = { 0x2000000, 0x10000 },
67 [VIRT_PLIC] = { 0xc000000, 0x4000000 },
68 [VIRT_UART0] = { 0x10000000, 0x100 },
69 [VIRT_VIRTIO] = { 0x10001000, 0x1000 },
70 [VIRT_FLASH] = { 0x20000000, 0x4000000 },
71 [VIRT_DRAM] = { 0x80000000, 0x0 },
72 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
73 [VIRT_PCIE_PIO] = { 0x03000000, 0x00010000 },
74 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
75 };
76
77 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
78
virt_flash_create1(RISCVVirtState * s,const char * name,const char * alias_prop_name)79 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s,
80 const char *name,
81 const char *alias_prop_name)
82 {
83 /*
84 * Create a single flash device. We use the same parameters as
85 * the flash devices on the ARM virt board.
86 */
87 DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
88
89 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
90 qdev_prop_set_uint8(dev, "width", 4);
91 qdev_prop_set_uint8(dev, "device-width", 2);
92 qdev_prop_set_bit(dev, "big-endian", false);
93 qdev_prop_set_uint16(dev, "id0", 0x89);
94 qdev_prop_set_uint16(dev, "id1", 0x18);
95 qdev_prop_set_uint16(dev, "id2", 0x00);
96 qdev_prop_set_uint16(dev, "id3", 0x00);
97 qdev_prop_set_string(dev, "name", name);
98
99 object_property_add_child(OBJECT(s), name, OBJECT(dev),
100 &error_abort);
101 object_property_add_alias(OBJECT(s), alias_prop_name,
102 OBJECT(dev), "drive", &error_abort);
103
104 return PFLASH_CFI01(dev);
105 }
106
virt_flash_create(RISCVVirtState * s)107 static void virt_flash_create(RISCVVirtState *s)
108 {
109 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0");
110 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1");
111 }
112
virt_flash_map1(PFlashCFI01 * flash,hwaddr base,hwaddr size,MemoryRegion * sysmem)113 static void virt_flash_map1(PFlashCFI01 *flash,
114 hwaddr base, hwaddr size,
115 MemoryRegion *sysmem)
116 {
117 DeviceState *dev = DEVICE(flash);
118
119 assert(size % VIRT_FLASH_SECTOR_SIZE == 0);
120 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
121 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
122 qdev_init_nofail(dev);
123
124 memory_region_add_subregion(sysmem, base,
125 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
126 0));
127 }
128
virt_flash_map(RISCVVirtState * s,MemoryRegion * sysmem)129 static void virt_flash_map(RISCVVirtState *s,
130 MemoryRegion *sysmem)
131 {
132 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
133 hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
134
135 virt_flash_map1(s->flash[0], flashbase, flashsize,
136 sysmem);
137 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize,
138 sysmem);
139 }
140
create_pcie_irq_map(void * fdt,char * nodename,uint32_t plic_phandle)141 static void create_pcie_irq_map(void *fdt, char *nodename,
142 uint32_t plic_phandle)
143 {
144 int pin, dev;
145 uint32_t
146 full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {};
147 uint32_t *irq_map = full_irq_map;
148
149 /* This code creates a standard swizzle of interrupts such that
150 * each device's first interrupt is based on it's PCI_SLOT number.
151 * (See pci_swizzle_map_irq_fn())
152 *
153 * We only need one entry per interrupt in the table (not one per
154 * possible slot) seeing the interrupt-map-mask will allow the table
155 * to wrap to any number of devices.
156 */
157 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
158 int devfn = dev * 0x8;
159
160 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
161 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
162 int i = 0;
163
164 irq_map[i] = cpu_to_be32(devfn << 8);
165
166 i += FDT_PCI_ADDR_CELLS;
167 irq_map[i] = cpu_to_be32(pin + 1);
168
169 i += FDT_PCI_INT_CELLS;
170 irq_map[i++] = cpu_to_be32(plic_phandle);
171
172 i += FDT_PLIC_ADDR_CELLS;
173 irq_map[i] = cpu_to_be32(irq_nr);
174
175 irq_map += FDT_INT_MAP_WIDTH;
176 }
177 }
178
179 qemu_fdt_setprop(fdt, nodename, "interrupt-map",
180 full_irq_map, sizeof(full_irq_map));
181
182 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
183 0x1800, 0, 0, 0x7);
184 }
185
create_fdt(RISCVVirtState * s,const struct MemmapEntry * memmap,uint64_t mem_size,const char * cmdline)186 static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
187 uint64_t mem_size, const char *cmdline)
188 {
189 void *fdt;
190 int cpu, i;
191 uint32_t *cells;
192 char *nodename;
193 uint32_t plic_phandle, test_phandle, phandle = 1;
194 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
195 hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
196
197 fdt = s->fdt = create_device_tree(&s->fdt_size);
198 if (!fdt) {
199 error_report("create_device_tree() failed");
200 exit(1);
201 }
202
203 qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu");
204 qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio");
205 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
206 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
207
208 qemu_fdt_add_subnode(fdt, "/soc");
209 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
210 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
211 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
212 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
213
214 nodename = g_strdup_printf("/memory@%lx",
215 (long)memmap[VIRT_DRAM].base);
216 qemu_fdt_add_subnode(fdt, nodename);
217 qemu_fdt_setprop_cells(fdt, nodename, "reg",
218 memmap[VIRT_DRAM].base >> 32, memmap[VIRT_DRAM].base,
219 mem_size >> 32, mem_size);
220 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
221 g_free(nodename);
222
223 qemu_fdt_add_subnode(fdt, "/cpus");
224 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
225 SIFIVE_CLINT_TIMEBASE_FREQ);
226 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
227 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
228
229 for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
230 int cpu_phandle = phandle++;
231 int intc_phandle;
232 nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
233 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
234 char *isa = riscv_isa_string(&s->soc.harts[cpu]);
235 qemu_fdt_add_subnode(fdt, nodename);
236 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
237 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
238 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
239 qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
240 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
241 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
242 qemu_fdt_setprop_cell(fdt, nodename, "phandle", cpu_phandle);
243 intc_phandle = phandle++;
244 qemu_fdt_add_subnode(fdt, intc);
245 qemu_fdt_setprop_cell(fdt, intc, "phandle", intc_phandle);
246 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
247 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
248 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
249 g_free(isa);
250 g_free(intc);
251 g_free(nodename);
252 }
253
254 /* Add cpu-topology node */
255 qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
256 qemu_fdt_add_subnode(fdt, "/cpus/cpu-map/cluster0");
257 for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
258 char *core_nodename = g_strdup_printf("/cpus/cpu-map/cluster0/core%d",
259 cpu);
260 char *cpu_nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
261 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, cpu_nodename);
262 qemu_fdt_add_subnode(fdt, core_nodename);
263 qemu_fdt_setprop_cell(fdt, core_nodename, "cpu", intc_phandle);
264 g_free(core_nodename);
265 g_free(cpu_nodename);
266 }
267
268 cells = g_new0(uint32_t, s->soc.num_harts * 4);
269 for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
270 nodename =
271 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
272 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
273 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
274 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
275 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
276 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
277 g_free(nodename);
278 }
279 nodename = g_strdup_printf("/soc/clint@%lx",
280 (long)memmap[VIRT_CLINT].base);
281 qemu_fdt_add_subnode(fdt, nodename);
282 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
283 qemu_fdt_setprop_cells(fdt, nodename, "reg",
284 0x0, memmap[VIRT_CLINT].base,
285 0x0, memmap[VIRT_CLINT].size);
286 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
287 cells, s->soc.num_harts * sizeof(uint32_t) * 4);
288 g_free(cells);
289 g_free(nodename);
290
291 plic_phandle = phandle++;
292 cells = g_new0(uint32_t, s->soc.num_harts * 4);
293 for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
294 nodename =
295 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
296 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
297 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
298 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
299 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
300 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
301 g_free(nodename);
302 }
303 nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
304 (long)memmap[VIRT_PLIC].base);
305 qemu_fdt_add_subnode(fdt, nodename);
306 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells",
307 FDT_PLIC_ADDR_CELLS);
308 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells",
309 FDT_PLIC_INT_CELLS);
310 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
311 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
312 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
313 cells, s->soc.num_harts * sizeof(uint32_t) * 4);
314 qemu_fdt_setprop_cells(fdt, nodename, "reg",
315 0x0, memmap[VIRT_PLIC].base,
316 0x0, memmap[VIRT_PLIC].size);
317 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV);
318 qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
319 plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
320 g_free(cells);
321 g_free(nodename);
322
323 for (i = 0; i < VIRTIO_COUNT; i++) {
324 nodename = g_strdup_printf("/virtio_mmio@%lx",
325 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
326 qemu_fdt_add_subnode(fdt, nodename);
327 qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio");
328 qemu_fdt_setprop_cells(fdt, nodename, "reg",
329 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
330 0x0, memmap[VIRT_VIRTIO].size);
331 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
332 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", VIRTIO_IRQ + i);
333 g_free(nodename);
334 }
335
336 nodename = g_strdup_printf("/soc/pci@%lx",
337 (long) memmap[VIRT_PCIE_ECAM].base);
338 qemu_fdt_add_subnode(fdt, nodename);
339 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells",
340 FDT_PCI_ADDR_CELLS);
341 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells",
342 FDT_PCI_INT_CELLS);
343 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0x2);
344 qemu_fdt_setprop_string(fdt, nodename, "compatible",
345 "pci-host-ecam-generic");
346 qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");
347 qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0);
348 qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0,
349 memmap[VIRT_PCIE_ECAM].size /
350 PCIE_MMCFG_SIZE_MIN - 1);
351 qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
352 qemu_fdt_setprop_cells(fdt, nodename, "reg", 0, memmap[VIRT_PCIE_ECAM].base,
353 0, memmap[VIRT_PCIE_ECAM].size);
354 qemu_fdt_setprop_sized_cells(fdt, nodename, "ranges",
355 1, FDT_PCI_RANGE_IOPORT, 2, 0,
356 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
357 1, FDT_PCI_RANGE_MMIO,
358 2, memmap[VIRT_PCIE_MMIO].base,
359 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size);
360 create_pcie_irq_map(fdt, nodename, plic_phandle);
361 g_free(nodename);
362
363 test_phandle = phandle++;
364 nodename = g_strdup_printf("/test@%lx",
365 (long)memmap[VIRT_TEST].base);
366 qemu_fdt_add_subnode(fdt, nodename);
367 {
368 const char compat[] = "sifive,test1\0sifive,test0\0syscon";
369 qemu_fdt_setprop(fdt, nodename, "compatible", compat, sizeof(compat));
370 }
371 qemu_fdt_setprop_cells(fdt, nodename, "reg",
372 0x0, memmap[VIRT_TEST].base,
373 0x0, memmap[VIRT_TEST].size);
374 qemu_fdt_setprop_cell(fdt, nodename, "phandle", test_phandle);
375 test_phandle = qemu_fdt_get_phandle(fdt, nodename);
376 g_free(nodename);
377
378 nodename = g_strdup_printf("/reboot");
379 qemu_fdt_add_subnode(fdt, nodename);
380 qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-reboot");
381 qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_phandle);
382 qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0);
383 qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_RESET);
384 g_free(nodename);
385
386 nodename = g_strdup_printf("/poweroff");
387 qemu_fdt_add_subnode(fdt, nodename);
388 qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-poweroff");
389 qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_phandle);
390 qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0);
391 qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_PASS);
392 g_free(nodename);
393
394 nodename = g_strdup_printf("/uart@%lx",
395 (long)memmap[VIRT_UART0].base);
396 qemu_fdt_add_subnode(fdt, nodename);
397 qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a");
398 qemu_fdt_setprop_cells(fdt, nodename, "reg",
399 0x0, memmap[VIRT_UART0].base,
400 0x0, memmap[VIRT_UART0].size);
401 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400);
402 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
403 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", UART0_IRQ);
404
405 qemu_fdt_add_subnode(fdt, "/chosen");
406 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
407 if (cmdline) {
408 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
409 }
410 g_free(nodename);
411
412 nodename = g_strdup_printf("/rtc@%lx",
413 (long)memmap[VIRT_RTC].base);
414 qemu_fdt_add_subnode(fdt, nodename);
415 qemu_fdt_setprop_string(fdt, nodename, "compatible",
416 "google,goldfish-rtc");
417 qemu_fdt_setprop_cells(fdt, nodename, "reg",
418 0x0, memmap[VIRT_RTC].base,
419 0x0, memmap[VIRT_RTC].size);
420 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
421 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", RTC_IRQ);
422 g_free(nodename);
423
424 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
425 qemu_fdt_add_subnode(s->fdt, nodename);
426 qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "cfi-flash");
427 qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg",
428 2, flashbase, 2, flashsize,
429 2, flashbase + flashsize, 2, flashsize);
430 qemu_fdt_setprop_cell(s->fdt, nodename, "bank-width", 4);
431 g_free(nodename);
432 }
433
434
gpex_pcie_init(MemoryRegion * sys_mem,hwaddr ecam_base,hwaddr ecam_size,hwaddr mmio_base,hwaddr mmio_size,hwaddr pio_base,DeviceState * plic,bool link_up)435 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
436 hwaddr ecam_base, hwaddr ecam_size,
437 hwaddr mmio_base, hwaddr mmio_size,
438 hwaddr pio_base,
439 DeviceState *plic, bool link_up)
440 {
441 DeviceState *dev;
442 MemoryRegion *ecam_alias, *ecam_reg;
443 MemoryRegion *mmio_alias, *mmio_reg;
444 qemu_irq irq;
445 int i;
446
447 dev = qdev_create(NULL, TYPE_GPEX_HOST);
448
449 qdev_init_nofail(dev);
450
451 ecam_alias = g_new0(MemoryRegion, 1);
452 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
453 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
454 ecam_reg, 0, ecam_size);
455 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias);
456
457 mmio_alias = g_new0(MemoryRegion, 1);
458 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
459 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
460 mmio_reg, mmio_base, mmio_size);
461 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias);
462
463 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);
464
465 for (i = 0; i < GPEX_NUM_IRQS; i++) {
466 irq = qdev_get_gpio_in(plic, PCIE_IRQ + i);
467
468 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
469 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
470 }
471
472 return dev;
473 }
474
riscv_virt_board_init(MachineState * machine)475 static void riscv_virt_board_init(MachineState *machine)
476 {
477 const struct MemmapEntry *memmap = virt_memmap;
478 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
479 MemoryRegion *system_memory = get_system_memory();
480 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
481 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
482 char *plic_hart_config;
483 size_t plic_hart_config_len;
484 target_ulong start_addr = memmap[VIRT_DRAM].base;
485 int i;
486 unsigned int smp_cpus = machine->smp.cpus;
487
488 /* Initialize SOC */
489 object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
490 TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
491 object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
492 &error_abort);
493 object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
494 &error_abort);
495 object_property_set_bool(OBJECT(&s->soc), true, "realized",
496 &error_abort);
497
498 /* register system main memory (actual RAM) */
499 memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
500 machine->ram_size, &error_fatal);
501 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
502 main_mem);
503 #ifdef TARGET_CHERI
504 cheri_tag_init(main_mem, machine->ram_size);
505 #endif
506
507 /* create device tree */
508 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
509
510 /* boot rom */
511 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
512 memmap[VIRT_MROM].size, &error_fatal);
513 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
514 mask_rom);
515
516 start_addr =
517 riscv_find_and_load_firmware(machine, BIOS_FILENAME, start_addr);
518
519 if (machine->kernel_filename) {
520 uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
521 NULL);
522
523 if (machine->initrd_filename) {
524 hwaddr start;
525 hwaddr end = riscv_load_initrd(machine->initrd_filename,
526 machine->ram_size, kernel_entry,
527 &start);
528 qemu_fdt_setprop_cell(s->fdt, "/chosen",
529 "linux,initrd-start", start);
530 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
531 end);
532 }
533 }
534
535 if (drive_get(IF_PFLASH, 0, 0)) {
536 /*
537 * Pflash was supplied, let's overwrite the address we jump to after
538 * reset to the base of the flash.
539 */
540 start_addr = virt_memmap[VIRT_FLASH].base;
541 }
542
543 /* reset vector */
544 uint32_t reset_vec[8] = {
545 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
546 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
547 0xf1402573, /* csrr a0, mhartid */
548 #if defined(TARGET_RISCV32)
549 0x0182a283, /* lw t0, 24(t0) */
550 #elif defined(TARGET_RISCV64)
551 0x0182b283, /* ld t0, 24(t0) */
552 #endif
553 0x00028067, /* jr t0 */
554 0x00000000,
555 start_addr, /* start: .dword */
556 0x00000000,
557 /* dtb: */
558 };
559
560 /* copy in the reset vector in little_endian byte order */
561 for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
562 reset_vec[i] = cpu_to_le32(reset_vec[i]);
563 }
564 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
565 memmap[VIRT_MROM].base, &address_space_memory);
566
567 /* copy in the device tree */
568 if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
569 memmap[VIRT_MROM].size - sizeof(reset_vec)) {
570 error_report("not enough space to store device-tree");
571 exit(1);
572 }
573 qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
574 rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
575 memmap[VIRT_MROM].base + sizeof(reset_vec),
576 &address_space_memory);
577
578 /* create PLIC hart topology configuration string */
579 plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus;
580 plic_hart_config = g_malloc0(plic_hart_config_len);
581 for (i = 0; i < smp_cpus; i++) {
582 if (i != 0) {
583 strncat(plic_hart_config, ",", plic_hart_config_len);
584 }
585 strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, plic_hart_config_len);
586 plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1);
587 }
588
589 /* MMIO */
590 s->plic = sifive_plic_create(memmap[VIRT_PLIC].base,
591 plic_hart_config,
592 VIRT_PLIC_NUM_SOURCES,
593 VIRT_PLIC_NUM_PRIORITIES,
594 VIRT_PLIC_PRIORITY_BASE,
595 VIRT_PLIC_PENDING_BASE,
596 VIRT_PLIC_ENABLE_BASE,
597 VIRT_PLIC_ENABLE_STRIDE,
598 VIRT_PLIC_CONTEXT_BASE,
599 VIRT_PLIC_CONTEXT_STRIDE,
600 memmap[VIRT_PLIC].size);
601 sifive_clint_create(memmap[VIRT_CLINT].base,
602 memmap[VIRT_CLINT].size, smp_cpus,
603 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true);
604 sifive_test_create(memmap[VIRT_TEST].base);
605
606 for (i = 0; i < VIRTIO_COUNT; i++) {
607 sysbus_create_simple("virtio-mmio",
608 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
609 qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i));
610 }
611
612 gpex_pcie_init(system_memory,
613 memmap[VIRT_PCIE_ECAM].base,
614 memmap[VIRT_PCIE_ECAM].size,
615 memmap[VIRT_PCIE_MMIO].base,
616 memmap[VIRT_PCIE_MMIO].size,
617 memmap[VIRT_PCIE_PIO].base,
618 DEVICE(s->plic), true);
619
620 serial_mm_init(system_memory, memmap[VIRT_UART0].base,
621 0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
622 serial_hd(0), DEVICE_LITTLE_ENDIAN);
623
624 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
625 qdev_get_gpio_in(DEVICE(s->plic), RTC_IRQ));
626
627 virt_flash_create(s);
628
629 for (i = 0; i < ARRAY_SIZE(s->flash); i++) {
630 /* Map legacy -drive if=pflash to machine properties */
631 pflash_cfi01_legacy_drive(s->flash[i],
632 drive_get(IF_PFLASH, 0, i));
633 }
634 virt_flash_map(s, system_memory);
635
636 g_free(plic_hart_config);
637 }
638
riscv_virt_machine_instance_init(Object * obj)639 static void riscv_virt_machine_instance_init(Object *obj)
640 {
641 }
642
riscv_virt_machine_class_init(ObjectClass * oc,void * data)643 static void riscv_virt_machine_class_init(ObjectClass *oc, void *data)
644 {
645 MachineClass *mc = MACHINE_CLASS(oc);
646
647 mc->desc = "RISC-V VirtIO board";
648 mc->init = riscv_virt_board_init;
649 mc->max_cpus = 8;
650 mc->default_cpu_type = VIRT_CPU;
651 mc->pci_allow_0_address = true;
652 }
653
654 static const TypeInfo riscv_virt_machine_typeinfo = {
655 .name = MACHINE_TYPE_NAME("virt"),
656 .parent = TYPE_MACHINE,
657 .class_init = riscv_virt_machine_class_init,
658 .instance_init = riscv_virt_machine_instance_init,
659 .instance_size = sizeof(RISCVVirtState),
660 };
661
riscv_virt_machine_init_register_types(void)662 static void riscv_virt_machine_init_register_types(void)
663 {
664 type_register_static(&riscv_virt_machine_typeinfo);
665 }
666
667 type_init(riscv_virt_machine_init_register_types)
668