1 /*
2 * QEMU RISC-V PMP (Physical Memory Protection)
3 *
4 * Author: Daire McNamara, daire.mcnamara@emdalo.com
5 * Ivan Griffin, ivan.griffin@emdalo.com
6 *
7 * This provides a RISC-V Physical Memory Protection interface
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2 or later, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #ifndef RISCV_PMP_H
23 #define RISCV_PMP_H
24
25 typedef enum {
26 PMP_READ = 1 << 0,
27 PMP_WRITE = 1 << 1,
28 PMP_EXEC = 1 << 2,
29 PMP_LOCK = 1 << 7
30 } pmp_priv_t;
31
access_type_to_pmp_priv(MMUAccessType at)32 static inline pmp_priv_t access_type_to_pmp_priv(MMUAccessType at)
33 {
34 switch (at) {
35 #ifdef CONFIG_CHERI
36 case MMU_DATA_CAP_LOAD: return PMP_READ;
37 case MMU_DATA_CAP_STORE: return PMP_WRITE;
38 #endif
39 case MMU_DATA_LOAD: return PMP_READ;
40 case MMU_DATA_STORE: return PMP_WRITE;
41 case MMU_INST_FETCH: return PMP_EXEC;
42 }
43 abort();
44 }
45
46 typedef enum {
47 PMP_AMATCH_OFF, /* Null (off) */
48 PMP_AMATCH_TOR, /* Top of Range */
49 PMP_AMATCH_NA4, /* Naturally aligned four-byte region */
50 PMP_AMATCH_NAPOT /* Naturally aligned power-of-two region */
51 } pmp_am_t;
52
53 typedef struct {
54 target_ulong addr_reg;
55 uint8_t cfg_reg;
56 } pmp_entry_t;
57
58 typedef struct {
59 target_ulong sa;
60 target_ulong ea;
61 } pmp_addr_t;
62
63 typedef struct {
64 pmp_entry_t pmp[MAX_RISCV_PMPS];
65 pmp_addr_t addr[MAX_RISCV_PMPS];
66 uint32_t num_rules;
67 } pmp_table_t;
68
69 void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
70 target_ulong val);
71 target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index);
72 void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
73 target_ulong val);
74 target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
75 bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
76 target_ulong size, pmp_priv_t priv, target_ulong mode);
77
78 #endif
79