1 /** @file
2 PCI Library functions that use the 256 MB PCI Express MMIO window to perform PCI
3 Configuration cycles. Layers on PCI Express Library.
4
5 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
7
8 **/
9
10
11 #include <Base.h>
12
13 #include <Library/PciLib.h>
14 #include <Library/PciExpressLib.h>
15
16 /**
17 Registers a PCI device so PCI configuration registers may be accessed after
18 SetVirtualAddressMap().
19
20 Registers the PCI device specified by Address so all the PCI configuration registers
21 associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
22
23 If Address > 0x0FFFFFFF, then ASSERT().
24
25 @param Address The address that encodes the PCI Bus, Device, Function and
26 Register.
27
28 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
29 @retval RETURN_UNSUPPORTED An attempt was made to call this function
30 after ExitBootServices().
31 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
32 at runtime could not be mapped.
33 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
34 complete the registration.
35
36 **/
37 RETURN_STATUS
38 EFIAPI
PciRegisterForRuntimeAccess(IN UINTN Address)39 PciRegisterForRuntimeAccess (
40 IN UINTN Address
41 )
42 {
43 return PciExpressRegisterForRuntimeAccess (Address);
44 }
45
46 /**
47 Reads an 8-bit PCI configuration register.
48
49 Reads and returns the 8-bit PCI configuration register specified by Address.
50 This function must guarantee that all PCI read and write operations are
51 serialized.
52
53 If Address > 0x0FFFFFFF, then ASSERT().
54
55 @param Address The address that encodes the PCI Bus, Device, Function and
56 Register.
57
58 @return The read value from the PCI configuration register.
59
60 **/
61 UINT8
62 EFIAPI
PciRead8(IN UINTN Address)63 PciRead8 (
64 IN UINTN Address
65 )
66 {
67 return PciExpressRead8 (Address);
68 }
69
70 /**
71 Writes an 8-bit PCI configuration register.
72
73 Writes the 8-bit PCI configuration register specified by Address with the
74 value specified by Value. Value is returned. This function must guarantee
75 that all PCI read and write operations are serialized.
76
77 If Address > 0x0FFFFFFF, then ASSERT().
78
79 @param Address The address that encodes the PCI Bus, Device, Function and
80 Register.
81 @param Value The value to write.
82
83 @return The value written to the PCI configuration register.
84
85 **/
86 UINT8
87 EFIAPI
PciWrite8(IN UINTN Address,IN UINT8 Value)88 PciWrite8 (
89 IN UINTN Address,
90 IN UINT8 Value
91 )
92 {
93 return PciExpressWrite8 (Address, Value);
94 }
95
96 /**
97 Performs a bitwise OR of an 8-bit PCI configuration register with
98 an 8-bit value.
99
100 Reads the 8-bit PCI configuration register specified by Address, performs a
101 bitwise OR between the read result and the value specified by
102 OrData, and writes the result to the 8-bit PCI configuration register
103 specified by Address. The value written to the PCI configuration register is
104 returned. This function must guarantee that all PCI read and write operations
105 are serialized.
106
107 If Address > 0x0FFFFFFF, then ASSERT().
108
109 @param Address The address that encodes the PCI Bus, Device, Function and
110 Register.
111 @param OrData The value to OR with the PCI configuration register.
112
113 @return The value written back to the PCI configuration register.
114
115 **/
116 UINT8
117 EFIAPI
PciOr8(IN UINTN Address,IN UINT8 OrData)118 PciOr8 (
119 IN UINTN Address,
120 IN UINT8 OrData
121 )
122 {
123 return PciExpressOr8 (Address, OrData);
124 }
125
126 /**
127 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
128 value.
129
130 Reads the 8-bit PCI configuration register specified by Address, performs a
131 bitwise AND between the read result and the value specified by AndData, and
132 writes the result to the 8-bit PCI configuration register specified by
133 Address. The value written to the PCI configuration register is returned.
134 This function must guarantee that all PCI read and write operations are
135 serialized.
136
137 If Address > 0x0FFFFFFF, then ASSERT().
138
139 @param Address The address that encodes the PCI Bus, Device, Function and
140 Register.
141 @param AndData The value to AND with the PCI configuration register.
142
143 @return The value written back to the PCI configuration register.
144
145 **/
146 UINT8
147 EFIAPI
PciAnd8(IN UINTN Address,IN UINT8 AndData)148 PciAnd8 (
149 IN UINTN Address,
150 IN UINT8 AndData
151 )
152 {
153 return PciExpressAnd8 (Address, AndData);
154 }
155
156 /**
157 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
158 value, followed a bitwise OR with another 8-bit value.
159
160 Reads the 8-bit PCI configuration register specified by Address, performs a
161 bitwise AND between the read result and the value specified by AndData,
162 performs a bitwise OR between the result of the AND operation and
163 the value specified by OrData, and writes the result to the 8-bit PCI
164 configuration register specified by Address. The value written to the PCI
165 configuration register is returned. This function must guarantee that all PCI
166 read and write operations are serialized.
167
168 If Address > 0x0FFFFFFF, then ASSERT().
169
170 @param Address The address that encodes the PCI Bus, Device, Function and
171 Register.
172 @param AndData The value to AND with the PCI configuration register.
173 @param OrData The value to OR with the result of the AND operation.
174
175 @return The value written back to the PCI configuration register.
176
177 **/
178 UINT8
179 EFIAPI
PciAndThenOr8(IN UINTN Address,IN UINT8 AndData,IN UINT8 OrData)180 PciAndThenOr8 (
181 IN UINTN Address,
182 IN UINT8 AndData,
183 IN UINT8 OrData
184 )
185 {
186 return PciExpressAndThenOr8 (Address, AndData, OrData);
187 }
188
189 /**
190 Reads a bit field of a PCI configuration register.
191
192 Reads the bit field in an 8-bit PCI configuration register. The bit field is
193 specified by the StartBit and the EndBit. The value of the bit field is
194 returned.
195
196 If Address > 0x0FFFFFFF, then ASSERT().
197 If StartBit is greater than 7, then ASSERT().
198 If EndBit is greater than 7, then ASSERT().
199 If EndBit is less than StartBit, then ASSERT().
200
201 @param Address The PCI configuration register to read.
202 @param StartBit The ordinal of the least significant bit in the bit field.
203 Range 0..7.
204 @param EndBit The ordinal of the most significant bit in the bit field.
205 Range 0..7.
206
207 @return The value of the bit field read from the PCI configuration register.
208
209 **/
210 UINT8
211 EFIAPI
PciBitFieldRead8(IN UINTN Address,IN UINTN StartBit,IN UINTN EndBit)212 PciBitFieldRead8 (
213 IN UINTN Address,
214 IN UINTN StartBit,
215 IN UINTN EndBit
216 )
217 {
218 return PciExpressBitFieldRead8 (Address, StartBit, EndBit);
219 }
220
221 /**
222 Writes a bit field to a PCI configuration register.
223
224 Writes Value to the bit field of the PCI configuration register. The bit
225 field is specified by the StartBit and the EndBit. All other bits in the
226 destination PCI configuration register are preserved. The new value of the
227 8-bit register is returned.
228
229 If Address > 0x0FFFFFFF, then ASSERT().
230 If StartBit is greater than 7, then ASSERT().
231 If EndBit is greater than 7, then ASSERT().
232 If EndBit is less than StartBit, then ASSERT().
233 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
234
235 @param Address The PCI configuration register to write.
236 @param StartBit The ordinal of the least significant bit in the bit field.
237 Range 0..7.
238 @param EndBit The ordinal of the most significant bit in the bit field.
239 Range 0..7.
240 @param Value The new value of the bit field.
241
242 @return The value written back to the PCI configuration register.
243
244 **/
245 UINT8
246 EFIAPI
PciBitFieldWrite8(IN UINTN Address,IN UINTN StartBit,IN UINTN EndBit,IN UINT8 Value)247 PciBitFieldWrite8 (
248 IN UINTN Address,
249 IN UINTN StartBit,
250 IN UINTN EndBit,
251 IN UINT8 Value
252 )
253 {
254 return PciExpressBitFieldWrite8 (Address, StartBit, EndBit, Value);
255 }
256
257 /**
258 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
259 writes the result back to the bit field in the 8-bit port.
260
261 Reads the 8-bit PCI configuration register specified by Address, performs a
262 bitwise OR between the read result and the value specified by
263 OrData, and writes the result to the 8-bit PCI configuration register
264 specified by Address. The value written to the PCI configuration register is
265 returned. This function must guarantee that all PCI read and write operations
266 are serialized. Extra left bits in OrData are stripped.
267
268 If Address > 0x0FFFFFFF, then ASSERT().
269 If StartBit is greater than 7, then ASSERT().
270 If EndBit is greater than 7, then ASSERT().
271 If EndBit is less than StartBit, then ASSERT().
272 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
273
274 @param Address The PCI configuration register to write.
275 @param StartBit The ordinal of the least significant bit in the bit field.
276 Range 0..7.
277 @param EndBit The ordinal of the most significant bit in the bit field.
278 Range 0..7.
279 @param OrData The value to OR with the PCI configuration register.
280
281 @return The value written back to the PCI configuration register.
282
283 **/
284 UINT8
285 EFIAPI
PciBitFieldOr8(IN UINTN Address,IN UINTN StartBit,IN UINTN EndBit,IN UINT8 OrData)286 PciBitFieldOr8 (
287 IN UINTN Address,
288 IN UINTN StartBit,
289 IN UINTN EndBit,
290 IN UINT8 OrData
291 )
292 {
293 return PciExpressBitFieldOr8 (Address, StartBit, EndBit, OrData);
294 }
295
296 /**
297 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
298 AND, and writes the result back to the bit field in the 8-bit register.
299
300 Reads the 8-bit PCI configuration register specified by Address, performs a
301 bitwise AND between the read result and the value specified by AndData, and
302 writes the result to the 8-bit PCI configuration register specified by
303 Address. The value written to the PCI configuration register is returned.
304 This function must guarantee that all PCI read and write operations are
305 serialized. Extra left bits in AndData are stripped.
306
307 If Address > 0x0FFFFFFF, then ASSERT().
308 If StartBit is greater than 7, then ASSERT().
309 If EndBit is greater than 7, then ASSERT().
310 If EndBit is less than StartBit, then ASSERT().
311 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
312
313 @param Address The PCI configuration register to write.
314 @param StartBit The ordinal of the least significant bit in the bit field.
315 Range 0..7.
316 @param EndBit The ordinal of the most significant bit in the bit field.
317 Range 0..7.
318 @param AndData The value to AND with the PCI configuration register.
319
320 @return The value written back to the PCI configuration register.
321
322 **/
323 UINT8
324 EFIAPI
PciBitFieldAnd8(IN UINTN Address,IN UINTN StartBit,IN UINTN EndBit,IN UINT8 AndData)325 PciBitFieldAnd8 (
326 IN UINTN Address,
327 IN UINTN StartBit,
328 IN UINTN EndBit,
329 IN UINT8 AndData
330 )
331 {
332 return PciExpressBitFieldAnd8 (Address, StartBit, EndBit, AndData);
333 }
334
335 /**
336 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
337 bitwise OR, and writes the result back to the bit field in the
338 8-bit port.
339
340 Reads the 8-bit PCI configuration register specified by Address, performs a
341 bitwise AND followed by a bitwise OR between the read result and
342 the value specified by AndData, and writes the result to the 8-bit PCI
343 configuration register specified by Address. The value written to the PCI
344 configuration register is returned. This function must guarantee that all PCI
345 read and write operations are serialized. Extra left bits in both AndData and
346 OrData are stripped.
347
348 If Address > 0x0FFFFFFF, then ASSERT().
349 If StartBit is greater than 7, then ASSERT().
350 If EndBit is greater than 7, then ASSERT().
351 If EndBit is less than StartBit, then ASSERT().
352 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
353 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
354
355 @param Address The PCI configuration register to write.
356 @param StartBit The ordinal of the least significant bit in the bit field.
357 Range 0..7.
358 @param EndBit The ordinal of the most significant bit in the bit field.
359 Range 0..7.
360 @param AndData The value to AND with the PCI configuration register.
361 @param OrData The value to OR with the result of the AND operation.
362
363 @return The value written back to the PCI configuration register.
364
365 **/
366 UINT8
367 EFIAPI
PciBitFieldAndThenOr8(IN UINTN Address,IN UINTN StartBit,IN UINTN EndBit,IN UINT8 AndData,IN UINT8 OrData)368 PciBitFieldAndThenOr8 (
369 IN UINTN Address,
370 IN UINTN StartBit,
371 IN UINTN EndBit,
372 IN UINT8 AndData,
373 IN UINT8 OrData
374 )
375 {
376 return PciExpressBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData);
377 }
378
379 /**
380 Reads a 16-bit PCI configuration register.
381
382 Reads and returns the 16-bit PCI configuration register specified by Address.
383 This function must guarantee that all PCI read and write operations are
384 serialized.
385
386 If Address > 0x0FFFFFFF, then ASSERT().
387 If Address is not aligned on a 16-bit boundary, then ASSERT().
388
389 @param Address The address that encodes the PCI Bus, Device, Function and
390 Register.
391
392 @return The read value from the PCI configuration register.
393
394 **/
395 UINT16
396 EFIAPI
PciRead16(IN UINTN Address)397 PciRead16 (
398 IN UINTN Address
399 )
400 {
401 return PciExpressRead16 (Address);
402 }
403
404 /**
405 Writes a 16-bit PCI configuration register.
406
407 Writes the 16-bit PCI configuration register specified by Address with the
408 value specified by Value. Value is returned. This function must guarantee
409 that all PCI read and write operations are serialized.
410
411 If Address > 0x0FFFFFFF, then ASSERT().
412 If Address is not aligned on a 16-bit boundary, then ASSERT().
413
414 @param Address The address that encodes the PCI Bus, Device, Function and
415 Register.
416 @param Value The value to write.
417
418 @return The value written to the PCI configuration register.
419
420 **/
421 UINT16
422 EFIAPI
PciWrite16(IN UINTN Address,IN UINT16 Value)423 PciWrite16 (
424 IN UINTN Address,
425 IN UINT16 Value
426 )
427 {
428 return PciExpressWrite16 (Address, Value);
429 }
430
431 /**
432 Performs a bitwise OR of a 16-bit PCI configuration register with
433 a 16-bit value.
434
435 Reads the 16-bit PCI configuration register specified by Address, performs a
436 bitwise OR between the read result and the value specified by
437 OrData, and writes the result to the 16-bit PCI configuration register
438 specified by Address. The value written to the PCI configuration register is
439 returned. This function must guarantee that all PCI read and write operations
440 are serialized.
441
442 If Address > 0x0FFFFFFF, then ASSERT().
443 If Address is not aligned on a 16-bit boundary, then ASSERT().
444
445 @param Address The address that encodes the PCI Bus, Device, Function and
446 Register.
447 @param OrData The value to OR with the PCI configuration register.
448
449 @return The value written back to the PCI configuration register.
450
451 **/
452 UINT16
453 EFIAPI
PciOr16(IN UINTN Address,IN UINT16 OrData)454 PciOr16 (
455 IN UINTN Address,
456 IN UINT16 OrData
457 )
458 {
459 return PciExpressOr16 (Address, OrData);
460 }
461
462 /**
463 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
464 value.
465
466 Reads the 16-bit PCI configuration register specified by Address, performs a
467 bitwise AND between the read result and the value specified by AndData, and
468 writes the result to the 16-bit PCI configuration register specified by
469 Address. The value written to the PCI configuration register is returned.
470 This function must guarantee that all PCI read and write operations are
471 serialized.
472
473 If Address > 0x0FFFFFFF, then ASSERT().
474 If Address is not aligned on a 16-bit boundary, then ASSERT().
475
476 @param Address The address that encodes the PCI Bus, Device, Function and
477 Register.
478 @param AndData The value to AND with the PCI configuration register.
479
480 @return The value written back to the PCI configuration register.
481
482 **/
483 UINT16
484 EFIAPI
PciAnd16(IN UINTN Address,IN UINT16 AndData)485 PciAnd16 (
486 IN UINTN Address,
487 IN UINT16 AndData
488 )
489 {
490 return PciExpressAnd16 (Address, AndData);
491 }
492
493 /**
494 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
495 value, followed a bitwise OR with another 16-bit value.
496
497 Reads the 16-bit PCI configuration register specified by Address, performs a
498 bitwise AND between the read result and the value specified by AndData,
499 performs a bitwise OR between the result of the AND operation and
500 the value specified by OrData, and writes the result to the 16-bit PCI
501 configuration register specified by Address. The value written to the PCI
502 configuration register is returned. This function must guarantee that all PCI
503 read and write operations are serialized.
504
505 If Address > 0x0FFFFFFF, then ASSERT().
506 If Address is not aligned on a 16-bit boundary, then ASSERT().
507
508 @param Address The address that encodes the PCI Bus, Device, Function and
509 Register.
510 @param AndData The value to AND with the PCI configuration register.
511 @param OrData The value to OR with the result of the AND operation.
512
513 @return The value written back to the PCI configuration register.
514
515 **/
516 UINT16
517 EFIAPI
PciAndThenOr16(IN UINTN Address,IN UINT16 AndData,IN UINT16 OrData)518 PciAndThenOr16 (
519 IN UINTN Address,
520 IN UINT16 AndData,
521 IN UINT16 OrData
522 )
523 {
524 return PciExpressAndThenOr16 (Address, AndData, OrData);
525 }
526
527 /**
528 Reads a bit field of a PCI configuration register.
529
530 Reads the bit field in a 16-bit PCI configuration register. The bit field is
531 specified by the StartBit and the EndBit. The value of the bit field is
532 returned.
533
534 If Address > 0x0FFFFFFF, then ASSERT().
535 If Address is not aligned on a 16-bit boundary, then ASSERT().
536 If StartBit is greater than 15, then ASSERT().
537 If EndBit is greater than 15, then ASSERT().
538 If EndBit is less than StartBit, then ASSERT().
539
540 @param Address The PCI configuration register to read.
541 @param StartBit The ordinal of the least significant bit in the bit field.
542 Range 0..15.
543 @param EndBit The ordinal of the most significant bit in the bit field.
544 Range 0..15.
545
546 @return The value of the bit field read from the PCI configuration register.
547
548 **/
549 UINT16
550 EFIAPI
PciBitFieldRead16(IN UINTN Address,IN UINTN StartBit,IN UINTN EndBit)551 PciBitFieldRead16 (
552 IN UINTN Address,
553 IN UINTN StartBit,
554 IN UINTN EndBit
555 )
556 {
557 return PciExpressBitFieldRead16 (Address, StartBit, EndBit);
558 }
559
560 /**
561 Writes a bit field to a PCI configuration register.
562
563 Writes Value to the bit field of the PCI configuration register. The bit
564 field is specified by the StartBit and the EndBit. All other bits in the
565 destination PCI configuration register are preserved. The new value of the
566 16-bit register is returned.
567
568 If Address > 0x0FFFFFFF, then ASSERT().
569 If Address is not aligned on a 16-bit boundary, then ASSERT().
570 If StartBit is greater than 15, then ASSERT().
571 If EndBit is greater than 15, then ASSERT().
572 If EndBit is less than StartBit, then ASSERT().
573 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
574
575 @param Address The PCI configuration register to write.
576 @param StartBit The ordinal of the least significant bit in the bit field.
577 Range 0..15.
578 @param EndBit The ordinal of the most significant bit in the bit field.
579 Range 0..15.
580 @param Value The new value of the bit field.
581
582 @return The value written back to the PCI configuration register.
583
584 **/
585 UINT16
586 EFIAPI
PciBitFieldWrite16(IN UINTN Address,IN UINTN StartBit,IN UINTN EndBit,IN UINT16 Value)587 PciBitFieldWrite16 (
588 IN UINTN Address,
589 IN UINTN StartBit,
590 IN UINTN EndBit,
591 IN UINT16 Value
592 )
593 {
594 return PciExpressBitFieldWrite16 (Address, StartBit, EndBit, Value);
595 }
596
597 /**
598 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
599 writes the result back to the bit field in the 16-bit port.
600
601 Reads the 16-bit PCI configuration register specified by Address, performs a
602 bitwise OR between the read result and the value specified by
603 OrData, and writes the result to the 16-bit PCI configuration register
604 specified by Address. The value written to the PCI configuration register is
605 returned. This function must guarantee that all PCI read and write operations
606 are serialized. Extra left bits in OrData are stripped.
607
608 If Address > 0x0FFFFFFF, then ASSERT().
609 If Address is not aligned on a 16-bit boundary, then ASSERT().
610 If StartBit is greater than 15, then ASSERT().
611 If EndBit is greater than 15, then ASSERT().
612 If EndBit is less than StartBit, then ASSERT().
613 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
614
615 @param Address The PCI configuration register to write.
616 @param StartBit The ordinal of the least significant bit in the bit field.
617 Range 0..15.
618 @param EndBit The ordinal of the most significant bit in the bit field.
619 Range 0..15.
620 @param OrData The value to OR with the PCI configuration register.
621
622 @return The value written back to the PCI configuration register.
623
624 **/
625 UINT16
626 EFIAPI
PciBitFieldOr16(IN UINTN Address,IN UINTN StartBit,IN UINTN EndBit,IN UINT16 OrData)627 PciBitFieldOr16 (
628 IN UINTN Address,
629 IN UINTN StartBit,
630 IN UINTN EndBit,
631 IN UINT16 OrData
632 )
633 {
634 return PciExpressBitFieldOr16 (Address, StartBit, EndBit, OrData);
635 }
636
637 /**
638 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
639 AND, and writes the result back to the bit field in the 16-bit register.
640
641 Reads the 16-bit PCI configuration register specified by Address, performs a
642 bitwise AND between the read result and the value specified by AndData, and
643 writes the result to the 16-bit PCI configuration register specified by
644 Address. The value written to the PCI configuration register is returned.
645 This function must guarantee that all PCI read and write operations are
646 serialized. Extra left bits in AndData are stripped.
647
648 If Address > 0x0FFFFFFF, then ASSERT().
649 If Address is not aligned on a 16-bit boundary, then ASSERT().
650 If StartBit is greater than 15, then ASSERT().
651 If EndBit is greater than 15, then ASSERT().
652 If EndBit is less than StartBit, then ASSERT().
653 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
654
655 @param Address The PCI configuration register to write.
656 @param StartBit The ordinal of the least significant bit in the bit field.
657 Range 0..15.
658 @param EndBit The ordinal of the most significant bit in the bit field.
659 Range 0..15.
660 @param AndData The value to AND with the PCI configuration register.
661
662 @return The value written back to the PCI configuration register.
663
664 **/
665 UINT16
666 EFIAPI
PciBitFieldAnd16(IN UINTN Address,IN UINTN StartBit,IN UINTN EndBit,IN UINT16 AndData)667 PciBitFieldAnd16 (
668 IN UINTN Address,
669 IN UINTN StartBit,
670 IN UINTN EndBit,
671 IN UINT16 AndData
672 )
673 {
674 return PciExpressBitFieldAnd16 (Address, StartBit, EndBit, AndData);
675 }
676
677 /**
678 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
679 bitwise OR, and writes the result back to the bit field in the
680 16-bit port.
681
682 Reads the 16-bit PCI configuration register specified by Address, performs a
683 bitwise AND followed by a bitwise OR between the read result and
684 the value specified by AndData, and writes the result to the 16-bit PCI
685 configuration register specified by Address. The value written to the PCI
686 configuration register is returned. This function must guarantee that all PCI
687 read and write operations are serialized. Extra left bits in both AndData and
688 OrData are stripped.
689
690 If Address > 0x0FFFFFFF, then ASSERT().
691 If Address is not aligned on a 16-bit boundary, then ASSERT().
692 If StartBit is greater than 15, then ASSERT().
693 If EndBit is greater than 15, then ASSERT().
694 If EndBit is less than StartBit, then ASSERT().
695 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
696 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
697
698 @param Address The PCI configuration register to write.
699 @param StartBit The ordinal of the least significant bit in the bit field.
700 Range 0..15.
701 @param EndBit The ordinal of the most significant bit in the bit field.
702 Range 0..15.
703 @param AndData The value to AND with the PCI configuration register.
704 @param OrData The value to OR with the result of the AND operation.
705
706 @return The value written back to the PCI configuration register.
707
708 **/
709 UINT16
710 EFIAPI
PciBitFieldAndThenOr16(IN UINTN Address,IN UINTN StartBit,IN UINTN EndBit,IN UINT16 AndData,IN UINT16 OrData)711 PciBitFieldAndThenOr16 (
712 IN UINTN Address,
713 IN UINTN StartBit,
714 IN UINTN EndBit,
715 IN UINT16 AndData,
716 IN UINT16 OrData
717 )
718 {
719 return PciExpressBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData);
720 }
721
722 /**
723 Reads a 32-bit PCI configuration register.
724
725 Reads and returns the 32-bit PCI configuration register specified by Address.
726 This function must guarantee that all PCI read and write operations are
727 serialized.
728
729 If Address > 0x0FFFFFFF, then ASSERT().
730 If Address is not aligned on a 32-bit boundary, then ASSERT().
731
732 @param Address The address that encodes the PCI Bus, Device, Function and
733 Register.
734
735 @return The read value from the PCI configuration register.
736
737 **/
738 UINT32
739 EFIAPI
PciRead32(IN UINTN Address)740 PciRead32 (
741 IN UINTN Address
742 )
743 {
744 return PciExpressRead32 (Address);
745 }
746
747 /**
748 Writes a 32-bit PCI configuration register.
749
750 Writes the 32-bit PCI configuration register specified by Address with the
751 value specified by Value. Value is returned. This function must guarantee
752 that all PCI read and write operations are serialized.
753
754 If Address > 0x0FFFFFFF, then ASSERT().
755 If Address is not aligned on a 32-bit boundary, then ASSERT().
756
757 @param Address The address that encodes the PCI Bus, Device, Function and
758 Register.
759 @param Value The value to write.
760
761 @return The value written to the PCI configuration register.
762
763 **/
764 UINT32
765 EFIAPI
PciWrite32(IN UINTN Address,IN UINT32 Value)766 PciWrite32 (
767 IN UINTN Address,
768 IN UINT32 Value
769 )
770 {
771 return PciExpressWrite32 (Address, Value);
772 }
773
774 /**
775 Performs a bitwise OR of a 32-bit PCI configuration register with
776 a 32-bit value.
777
778 Reads the 32-bit PCI configuration register specified by Address, performs a
779 bitwise OR between the read result and the value specified by
780 OrData, and writes the result to the 32-bit PCI configuration register
781 specified by Address. The value written to the PCI configuration register is
782 returned. This function must guarantee that all PCI read and write operations
783 are serialized.
784
785 If Address > 0x0FFFFFFF, then ASSERT().
786 If Address is not aligned on a 32-bit boundary, then ASSERT().
787
788 @param Address The address that encodes the PCI Bus, Device, Function and
789 Register.
790 @param OrData The value to OR with the PCI configuration register.
791
792 @return The value written back to the PCI configuration register.
793
794 **/
795 UINT32
796 EFIAPI
PciOr32(IN UINTN Address,IN UINT32 OrData)797 PciOr32 (
798 IN UINTN Address,
799 IN UINT32 OrData
800 )
801 {
802 return PciExpressOr32 (Address, OrData);
803 }
804
805 /**
806 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
807 value.
808
809 Reads the 32-bit PCI configuration register specified by Address, performs a
810 bitwise AND between the read result and the value specified by AndData, and
811 writes the result to the 32-bit PCI configuration register specified by
812 Address. The value written to the PCI configuration register is returned.
813 This function must guarantee that all PCI read and write operations are
814 serialized.
815
816 If Address > 0x0FFFFFFF, then ASSERT().
817 If Address is not aligned on a 32-bit boundary, then ASSERT().
818
819 @param Address The address that encodes the PCI Bus, Device, Function and
820 Register.
821 @param AndData The value to AND with the PCI configuration register.
822
823 @return The value written back to the PCI configuration register.
824
825 **/
826 UINT32
827 EFIAPI
PciAnd32(IN UINTN Address,IN UINT32 AndData)828 PciAnd32 (
829 IN UINTN Address,
830 IN UINT32 AndData
831 )
832 {
833 return PciExpressAnd32 (Address, AndData);
834 }
835
836 /**
837 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
838 value, followed a bitwise OR with another 32-bit value.
839
840 Reads the 32-bit PCI configuration register specified by Address, performs a
841 bitwise AND between the read result and the value specified by AndData,
842 performs a bitwise OR between the result of the AND operation and
843 the value specified by OrData, and writes the result to the 32-bit PCI
844 configuration register specified by Address. The value written to the PCI
845 configuration register is returned. This function must guarantee that all PCI
846 read and write operations are serialized.
847
848 If Address > 0x0FFFFFFF, then ASSERT().
849 If Address is not aligned on a 32-bit boundary, then ASSERT().
850
851 @param Address The address that encodes the PCI Bus, Device, Function and
852 Register.
853 @param AndData The value to AND with the PCI configuration register.
854 @param OrData The value to OR with the result of the AND operation.
855
856 @return The value written back to the PCI configuration register.
857
858 **/
859 UINT32
860 EFIAPI
PciAndThenOr32(IN UINTN Address,IN UINT32 AndData,IN UINT32 OrData)861 PciAndThenOr32 (
862 IN UINTN Address,
863 IN UINT32 AndData,
864 IN UINT32 OrData
865 )
866 {
867 return PciExpressAndThenOr32 (Address, AndData, OrData);
868 }
869
870 /**
871 Reads a bit field of a PCI configuration register.
872
873 Reads the bit field in a 32-bit PCI configuration register. The bit field is
874 specified by the StartBit and the EndBit. The value of the bit field is
875 returned.
876
877 If Address > 0x0FFFFFFF, then ASSERT().
878 If Address is not aligned on a 32-bit boundary, then ASSERT().
879 If StartBit is greater than 31, then ASSERT().
880 If EndBit is greater than 31, then ASSERT().
881 If EndBit is less than StartBit, then ASSERT().
882
883 @param Address The PCI configuration register to read.
884 @param StartBit The ordinal of the least significant bit in the bit field.
885 Range 0..31.
886 @param EndBit The ordinal of the most significant bit in the bit field.
887 Range 0..31.
888
889 @return The value of the bit field read from the PCI configuration register.
890
891 **/
892 UINT32
893 EFIAPI
PciBitFieldRead32(IN UINTN Address,IN UINTN StartBit,IN UINTN EndBit)894 PciBitFieldRead32 (
895 IN UINTN Address,
896 IN UINTN StartBit,
897 IN UINTN EndBit
898 )
899 {
900 return PciExpressBitFieldRead32 (Address, StartBit, EndBit);
901 }
902
903 /**
904 Writes a bit field to a PCI configuration register.
905
906 Writes Value to the bit field of the PCI configuration register. The bit
907 field is specified by the StartBit and the EndBit. All other bits in the
908 destination PCI configuration register are preserved. The new value of the
909 32-bit register is returned.
910
911 If Address > 0x0FFFFFFF, then ASSERT().
912 If Address is not aligned on a 32-bit boundary, then ASSERT().
913 If StartBit is greater than 31, then ASSERT().
914 If EndBit is greater than 31, then ASSERT().
915 If EndBit is less than StartBit, then ASSERT().
916 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
917
918 @param Address The PCI configuration register to write.
919 @param StartBit The ordinal of the least significant bit in the bit field.
920 Range 0..31.
921 @param EndBit The ordinal of the most significant bit in the bit field.
922 Range 0..31.
923 @param Value The new value of the bit field.
924
925 @return The value written back to the PCI configuration register.
926
927 **/
928 UINT32
929 EFIAPI
PciBitFieldWrite32(IN UINTN Address,IN UINTN StartBit,IN UINTN EndBit,IN UINT32 Value)930 PciBitFieldWrite32 (
931 IN UINTN Address,
932 IN UINTN StartBit,
933 IN UINTN EndBit,
934 IN UINT32 Value
935 )
936 {
937 return PciExpressBitFieldWrite32 (Address, StartBit, EndBit, Value);
938 }
939
940 /**
941 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
942 writes the result back to the bit field in the 32-bit port.
943
944 Reads the 32-bit PCI configuration register specified by Address, performs a
945 bitwise OR between the read result and the value specified by
946 OrData, and writes the result to the 32-bit PCI configuration register
947 specified by Address. The value written to the PCI configuration register is
948 returned. This function must guarantee that all PCI read and write operations
949 are serialized. Extra left bits in OrData are stripped.
950
951 If Address > 0x0FFFFFFF, then ASSERT().
952 If Address is not aligned on a 32-bit boundary, then ASSERT().
953 If StartBit is greater than 31, then ASSERT().
954 If EndBit is greater than 31, then ASSERT().
955 If EndBit is less than StartBit, then ASSERT().
956 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
957
958 @param Address The PCI configuration register to write.
959 @param StartBit The ordinal of the least significant bit in the bit field.
960 Range 0..31.
961 @param EndBit The ordinal of the most significant bit in the bit field.
962 Range 0..31.
963 @param OrData The value to OR with the PCI configuration register.
964
965 @return The value written back to the PCI configuration register.
966
967 **/
968 UINT32
969 EFIAPI
PciBitFieldOr32(IN UINTN Address,IN UINTN StartBit,IN UINTN EndBit,IN UINT32 OrData)970 PciBitFieldOr32 (
971 IN UINTN Address,
972 IN UINTN StartBit,
973 IN UINTN EndBit,
974 IN UINT32 OrData
975 )
976 {
977 return PciExpressBitFieldOr32 (Address, StartBit, EndBit, OrData);
978 }
979
980 /**
981 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
982 AND, and writes the result back to the bit field in the 32-bit register.
983
984 Reads the 32-bit PCI configuration register specified by Address, performs a
985 bitwise AND between the read result and the value specified by AndData, and
986 writes the result to the 32-bit PCI configuration register specified by
987 Address. The value written to the PCI configuration register is returned.
988 This function must guarantee that all PCI read and write operations are
989 serialized. Extra left bits in AndData are stripped.
990
991 If Address > 0x0FFFFFFF, then ASSERT().
992 If Address is not aligned on a 32-bit boundary, then ASSERT().
993 If StartBit is greater than 31, then ASSERT().
994 If EndBit is greater than 31, then ASSERT().
995 If EndBit is less than StartBit, then ASSERT().
996 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
997
998 @param Address The PCI configuration register to write.
999 @param StartBit The ordinal of the least significant bit in the bit field.
1000 Range 0..31.
1001 @param EndBit The ordinal of the most significant bit in the bit field.
1002 Range 0..31.
1003 @param AndData The value to AND with the PCI configuration register.
1004
1005 @return The value written back to the PCI configuration register.
1006
1007 **/
1008 UINT32
1009 EFIAPI
PciBitFieldAnd32(IN UINTN Address,IN UINTN StartBit,IN UINTN EndBit,IN UINT32 AndData)1010 PciBitFieldAnd32 (
1011 IN UINTN Address,
1012 IN UINTN StartBit,
1013 IN UINTN EndBit,
1014 IN UINT32 AndData
1015 )
1016 {
1017 return PciExpressBitFieldAnd32 (Address, StartBit, EndBit, AndData);
1018 }
1019
1020 /**
1021 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1022 bitwise OR, and writes the result back to the bit field in the
1023 32-bit port.
1024
1025 Reads the 32-bit PCI configuration register specified by Address, performs a
1026 bitwise AND followed by a bitwise OR between the read result and
1027 the value specified by AndData, and writes the result to the 32-bit PCI
1028 configuration register specified by Address. The value written to the PCI
1029 configuration register is returned. This function must guarantee that all PCI
1030 read and write operations are serialized. Extra left bits in both AndData and
1031 OrData are stripped.
1032
1033 If Address > 0x0FFFFFFF, then ASSERT().
1034 If Address is not aligned on a 32-bit boundary, then ASSERT().
1035 If StartBit is greater than 31, then ASSERT().
1036 If EndBit is greater than 31, then ASSERT().
1037 If EndBit is less than StartBit, then ASSERT().
1038 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1039 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1040
1041 @param Address The PCI configuration register to write.
1042 @param StartBit The ordinal of the least significant bit in the bit field.
1043 Range 0..31.
1044 @param EndBit The ordinal of the most significant bit in the bit field.
1045 Range 0..31.
1046 @param AndData The value to AND with the PCI configuration register.
1047 @param OrData The value to OR with the result of the AND operation.
1048
1049 @return The value written back to the PCI configuration register.
1050
1051 **/
1052 UINT32
1053 EFIAPI
PciBitFieldAndThenOr32(IN UINTN Address,IN UINTN StartBit,IN UINTN EndBit,IN UINT32 AndData,IN UINT32 OrData)1054 PciBitFieldAndThenOr32 (
1055 IN UINTN Address,
1056 IN UINTN StartBit,
1057 IN UINTN EndBit,
1058 IN UINT32 AndData,
1059 IN UINT32 OrData
1060 )
1061 {
1062 return PciExpressBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData);
1063 }
1064
1065 /**
1066 Reads a range of PCI configuration registers into a caller supplied buffer.
1067
1068 Reads the range of PCI configuration registers specified by StartAddress and
1069 Size into the buffer specified by Buffer. This function only allows the PCI
1070 configuration registers from a single PCI function to be read. Size is
1071 returned. When possible 32-bit PCI configuration read cycles are used to read
1072 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1073 and 16-bit PCI configuration read cycles may be used at the beginning and the
1074 end of the range.
1075
1076 If StartAddress > 0x0FFFFFFF, then ASSERT().
1077 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1078 If Size > 0 and Buffer is NULL, then ASSERT().
1079
1080 @param StartAddress The starting address that encodes the PCI Bus, Device,
1081 Function and Register.
1082 @param Size The size in bytes of the transfer.
1083 @param Buffer The pointer to a buffer receiving the data read.
1084
1085 @return Size
1086
1087 **/
1088 UINTN
1089 EFIAPI
PciReadBuffer(IN UINTN StartAddress,IN UINTN Size,OUT VOID * Buffer)1090 PciReadBuffer (
1091 IN UINTN StartAddress,
1092 IN UINTN Size,
1093 OUT VOID *Buffer
1094 )
1095 {
1096 return PciExpressReadBuffer (StartAddress, Size, Buffer);
1097 }
1098
1099 /**
1100 Copies the data in a caller supplied buffer to a specified range of PCI
1101 configuration space.
1102
1103 Writes the range of PCI configuration registers specified by StartAddress and
1104 Size from the buffer specified by Buffer. This function only allows the PCI
1105 configuration registers from a single PCI function to be written. Size is
1106 returned. When possible 32-bit PCI configuration write cycles are used to
1107 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1108 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1109 and the end of the range.
1110
1111 If StartAddress > 0x0FFFFFFF, then ASSERT().
1112 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1113 If Size > 0 and Buffer is NULL, then ASSERT().
1114
1115 @param StartAddress The starting address that encodes the PCI Bus, Device,
1116 Function and Register.
1117 @param Size The size in bytes of the transfer.
1118 @param Buffer The pointer to a buffer containing the data to write.
1119
1120 @return Size written to StartAddress.
1121
1122 **/
1123 UINTN
1124 EFIAPI
PciWriteBuffer(IN UINTN StartAddress,IN UINTN Size,IN VOID * Buffer)1125 PciWriteBuffer (
1126 IN UINTN StartAddress,
1127 IN UINTN Size,
1128 IN VOID *Buffer
1129 )
1130 {
1131 return PciExpressWriteBuffer (StartAddress, Size, Buffer);
1132 }
1133